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ppc4xx: Enable 405EX PCIe UTL register configuration

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Till now the UTL registers on 405EX were not initialized but left with
their default values. This patch new initializes some of the UTL
registers on 405EX.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-11-16 14:16:54 +01:00
parent ecdcbd4f8c
commit f31d38b9ee
4 changed files with 45 additions and 5 deletions
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44
cpu/ppc4xx/4xx_pcie.c
View file

@ -401,6 +401,48 @@ int ppc4xx_init_pcie(void)
return 0;
}
#else
static void ppc4xx_setup_utl(u32 port)
{
u32 utl_base;
/*
* Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK
*/
switch (port) {
case 0:
mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000);
mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE);
mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0xfffffc01); /* 4k region, valid */
mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0);
break;
case 1:
mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000);
mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE);
mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0xfffffc01); /* 4k region, valid */
mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0);
break;
}
utl_base = (port==0) ? CFG_PCIE0_UTLBASE : CFG_PCIE1_UTLBASE;
/*
* Set buffer allocations and then assert VRB and TXE.
*/
out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x02000000);
out_be32((u32 *)(utl_base + PEUTL_INTR), 0x02000000);
out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000);
out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000);
out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000);
out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000);
out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000);
out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066);
out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c);
out_be32((u32 *)(utl_base + PEUTL_RCSTA),
in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000);
}
int ppc4xx_init_pcie(void)
{
/*
@ -643,14 +685,12 @@ int ppc4xx_init_pcie_port(int port, int rootport)
return -1;
}
#if defined(CONFIG_440SPE)
/*
* Setup UTL registers - but only on revA!
* We use default settings for revB chip.
*/
if (!ppc440spe_revB())
ppc4xx_setup_utl(port);
#endif
/*
* We map PCI Express configuration access into the 512MB regions

2
cpu/ppc4xx/cpu.c
View file

@ -510,7 +510,6 @@ int checkcpu (void)
return 0;
}
#if defined (CONFIG_440SPE)
int ppc440spe_revB() {
unsigned int pvr;
@ -520,7 +519,6 @@ int ppc440spe_revB() {
else
return 0;
}
#endif
/* ------------------------------------------------------------------------- */

2
include/asm-ppc/4xx_pcie.h
View file

@ -203,6 +203,7 @@
/*
* UTL register offsets
*/
#define PEUTL_PBCTL 0x00
#define PEUTL_PBBSZ 0x20
#define PEUTL_OPDBSZ 0x68
#define PEUTL_IPHBSZ 0x70
@ -210,6 +211,7 @@
#define PEUTL_OUTTR 0x90
#define PEUTL_INTR 0x98
#define PEUTL_PCTL 0xa0
#define PEUTL_RCSTA 0xb0
#define PEUTL_RCIRQEN 0xb8
/*

2
include/common.h
View file

@ -516,10 +516,10 @@ void get_sys_info ( sys_info_t * );
# if defined(CONFIG_440SPE)
unsigned long determine_sysper(void);
unsigned long determine_pci_clock_per(void);
int ppc440spe_revB(void);
# endif
# endif
typedef PPC4xx_SYS_INFO sys_info_t;
int ppc440spe_revB(void);
void get_sys_info ( sys_info_t * );
#endif