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spi: xilinx_spi: Add support for spi memory operations
Add support for spi memory operations for xilinx AXI qspi driver. This provides an high-level interface to execute SPI memory operations by the controller. Remove existing spi transfer based implementation and use spi memory based exec_op() implementation for qspi IO operations. Simplified existing startup_block implementation. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/1657954727-31972-2-git-send-email-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
T Karthik Reddy
Michal Simek
parent
b524f8fb1e
commit
f2dd6599df
1 changed files with 115 additions and 77 deletions
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@ -19,6 +19,7 @@
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#include <log.h>
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#include <malloc.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <asm/io.h>
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#include <wait_bit.h>
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#include <linux/bitops.h>
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@ -73,7 +74,7 @@
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#define XILSPI_MAX_XFER_BITS 8
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#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | SPICR_MASTER_MODE | \
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SPICR_SPE)
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SPICR_SPE | SPICR_MASTER_INHIBIT)
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#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
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#define XILINX_SPI_IDLE_VAL GENMASK(7, 0)
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@ -119,6 +120,15 @@ static int xilinx_spi_probe(struct udevice *bus)
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writel(SPISSR_RESET_VALUE, ®s->srr);
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/*
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* Reset RX & TX FIFO
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* Enable Manual Slave Select Assertion,
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* Set SPI controller into master mode, and enable it
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*/
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writel(SPICR_RXFIFO_RESEST | SPICR_TXFIFO_RESEST |
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SPICR_MANUAL_SS | SPICR_MASTER_MODE | SPICR_SPE,
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®s->spicr);
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return 0;
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}
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@ -136,7 +146,10 @@ static void spi_cs_deactivate(struct udevice *dev)
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struct udevice *bus = dev_get_parent(dev);
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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struct xilinx_spi_regs *regs = priv->regs;
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u32 reg;
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reg = readl(®s->spicr) | SPICR_RXFIFO_RESEST | SPICR_TXFIFO_RESEST;
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writel(reg, ®s->spicr);
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writel(SPISSR_OFF, ®s->spissr);
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}
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@ -205,81 +218,24 @@ static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32 rxbytes)
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return i;
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}
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static void xilinx_spi_startup_block(struct udevice *dev, unsigned int bytes,
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const void *dout, void *din)
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static int start_transfer(struct spi_slave *spi, const void *dout, void *din, u32 len)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct udevice *bus = spi->dev->parent;
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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struct xilinx_spi_regs *regs = priv->regs;
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
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const unsigned char *txp = dout;
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unsigned char *rxp = din;
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u32 reg;
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u32 txbytes = bytes;
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u32 rxbytes = bytes;
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u32 count, txbytes, rxbytes;
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int reg, ret;
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const unsigned char *txp = (const unsigned char *)dout;
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unsigned char *rxp = (unsigned char *)din;
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/*
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* This loop runs two times. First time to send the command.
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* Second time to transfer data. After transferring data,
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* it sets txp to the initial value for the normal operation.
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*/
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for ( ; priv->startup < 2; priv->startup++) {
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xilinx_spi_fill_txfifo(bus, txp, txbytes);
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reg = readl(®s->spicr) & ~SPICR_MASTER_INHIBIT;
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txbytes = len;
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rxbytes = len;
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while (txbytes || rxbytes) {
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/* Disable master transaction */
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reg = readl(®s->spicr) | SPICR_MASTER_INHIBIT;
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writel(reg, ®s->spicr);
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xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
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txp = din;
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if (priv->startup) {
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spi_cs_deactivate(dev);
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spi_cs_activate(dev, slave_plat->cs);
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txp = dout;
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}
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}
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}
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static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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struct xilinx_spi_regs *regs = priv->regs;
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
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/* assume spi core configured to do 8 bit transfers */
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unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
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const unsigned char *txp = dout;
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unsigned char *rxp = din;
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u32 txbytes = bytes;
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u32 rxbytes = bytes;
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u32 reg, count;
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int ret;
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debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
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dev_seq(bus), slave_plat->cs, bitlen, bytes, flags);
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if (bitlen == 0)
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goto done;
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if (bitlen % XILSPI_MAX_XFER_BITS) {
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printf("XILSPI warning: Not a multiple of %d bits\n",
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XILSPI_MAX_XFER_BITS);
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flags |= SPI_XFER_END;
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goto done;
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}
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(dev, slave_plat->cs);
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/*
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* This is the work around for the startup block issue in
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* the spi controller. SPI clock is passing through STARTUP
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* block to FLASH. STARTUP block don't provide clock as soon
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* as QSPI provides command. So first command fails.
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*/
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xilinx_spi_startup_block(dev, bytes, dout, din);
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while (txbytes && rxbytes) {
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count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
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/* Enable master transaction */
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reg = readl(®s->spicr) & ~SPICR_MASTER_INHIBIT;
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writel(reg, ®s->spicr);
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txbytes -= count;
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@ -293,21 +249,99 @@ static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
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return ret;
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}
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debug("txbytes:0x%x,txp:0x%p\n", txbytes, txp);
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reg = readl(®s->spicr) | SPICR_MASTER_INHIBIT;
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writel(reg, ®s->spicr);
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count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
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rxbytes -= count;
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if (rxp)
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rxp += count;
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debug("rxbytes:0x%x rxp:0x%p\n", rxbytes, rxp);
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}
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done:
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(dev);
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return 0;
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}
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static void xilinx_spi_startup_block(struct spi_slave *spi)
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{
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struct dm_spi_slave_plat *slave_plat =
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dev_get_parent_plat(spi->dev);
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unsigned char txp;
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unsigned char rxp[8];
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/*
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* Perform a dummy read as a work around for
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* the startup block issue.
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*/
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spi_cs_activate(spi->dev, slave_plat->cs);
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txp = 0x9f;
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start_transfer(spi, (void *)&txp, NULL, 1);
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start_transfer(spi, NULL, (void *)rxp, 6);
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spi_cs_deactivate(spi->dev);
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}
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static int xilinx_spi_mem_exec_op(struct spi_slave *spi,
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const struct spi_mem_op *op)
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{
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struct dm_spi_slave_plat *slave_plat =
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dev_get_parent_plat(spi->dev);
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static u32 startup;
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u32 dummy_len, ret;
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/*
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* This is the work around for the startup block issue in
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* the spi controller. SPI clock is passing through STARTUP
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* block to FLASH. STARTUP block don't provide clock as soon
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* as QSPI provides command. So first command fails.
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*/
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if (!startup) {
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xilinx_spi_startup_block(spi);
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startup++;
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}
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spi_cs_activate(spi->dev, slave_plat->cs);
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if (op->cmd.opcode) {
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ret = start_transfer(spi, (void *)&op->cmd.opcode, NULL, 1);
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if (ret)
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goto done;
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}
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if (op->addr.nbytes) {
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int i;
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u8 addr_buf[4];
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for (i = 0; i < op->addr.nbytes; i++)
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addr_buf[i] = op->addr.val >>
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(8 * (op->addr.nbytes - i - 1));
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ret = start_transfer(spi, (void *)addr_buf, NULL,
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op->addr.nbytes);
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if (ret)
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goto done;
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}
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if (op->dummy.nbytes) {
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dummy_len = op->dummy.nbytes * op->data.buswidth;
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ret = start_transfer(spi, NULL, NULL, dummy_len);
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if (ret)
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goto done;
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}
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if (op->data.nbytes) {
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if (op->data.dir == SPI_MEM_DATA_IN) {
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ret = start_transfer(spi, NULL,
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op->data.buf.in, op->data.nbytes);
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} else {
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ret = start_transfer(spi, op->data.buf.out,
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NULL, op->data.nbytes);
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}
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if (ret)
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goto done;
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}
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done:
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spi_cs_deactivate(spi->dev);
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return ret;
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}
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static int xilinx_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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@ -343,12 +377,16 @@ static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
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return 0;
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}
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static const struct spi_controller_mem_ops xilinx_spi_mem_ops = {
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.exec_op = xilinx_spi_mem_exec_op,
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};
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static const struct dm_spi_ops xilinx_spi_ops = {
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.claim_bus = xilinx_spi_claim_bus,
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.release_bus = xilinx_spi_release_bus,
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.xfer = xilinx_spi_xfer,
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.set_speed = xilinx_spi_set_speed,
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.set_mode = xilinx_spi_set_mode,
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.mem_ops = &xilinx_spi_mem_ops,
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};
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static const struct udevice_id xilinx_spi_ids[] = {
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