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ARM: tegra: use CONFIG_SYS_INIT_SP_BSS_OFFSET
Enable CONFIG_SYS_INIT_SP_BSS_OFFSET for all 64-bit Tegra boards. Place the stack/... 512KiB from the end of the U-Boot binary. This should be plenty to accommodate the current DTBs (max 64 KiB), early malloc region (6KiB), stack usage, and plenty of slack, while still not placing it too far away from the U-Boot binary. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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5 changed files with 8 additions and 10 deletions
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@ -21,6 +21,9 @@ endchoice
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config SYS_SOC
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default "tegra186"
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config SYS_INIT_SP_BSS_OFFSET
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default 524288
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source "board/nvidia/p2771-0000/Kconfig"
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endif
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@ -40,6 +40,9 @@ endchoice
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config SYS_SOC
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default "tegra210"
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config SYS_INIT_SP_BSS_OFFSET
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default 524288
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source "board/nvidia/e2220-1170/Kconfig"
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source "board/nvidia/p2371-0000/Kconfig"
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source "board/nvidia/p2371-2180/Kconfig"
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@ -78,11 +78,13 @@
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
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#ifndef CONFIG_ARM64
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
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#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#endif
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#ifndef CONFIG_ARM64
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/* Defines for SPL */
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@ -14,11 +14,6 @@
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*/
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#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_STACKBASE 0x82800000 /* 40MB */
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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@ -15,11 +15,6 @@
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*/
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#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_STACKBASE 0x82800000 /* 40MB */
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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