From 166e5b82a3f49239f67ac5f0d6df8abeb6ca0bdd Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Fri, 10 Jun 2022 19:18:00 +0800 Subject: [PATCH 01/10] intel: n5x: ddr: update license All the source code of sdram_n5x.c are from Intel, update the license to use both GPL2.0 and BSD-3 Clause because this copy of code may used for open source and internal project. Signed-off-by: Tien Fong Chee --- drivers/ddr/altera/sdram_n5x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c index ac13ac4319..737a4e2ff1 100644 --- a/drivers/ddr/altera/sdram_n5x.c +++ b/drivers/ddr/altera/sdram_n5x.c @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause /* - * Copyright (C) 2020-2021 Intel Corporation + * Copyright (C) 2020-2022 Intel Corporation * */ From f70e00fa7da69d16379c0b3526b793be45cd055d Mon Sep 17 00:00:00 2001 From: Yau Wai Gan Date: Tue, 24 May 2022 15:02:28 +0800 Subject: [PATCH 02/10] arm: dts: socfpga: stratix10: Update MMC smplsel value This new MMC sample select value is obtained from running tests on multiple Stratix 10 boards and proven working. Signed-off-by: Yau Wai Gan Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_stratix10_socdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index b7b48a5d31..8aa55a60ab 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -92,7 +92,7 @@ broken-cd; bus-width = <4>; drvsel = <3>; - smplsel = <0>; + smplsel = <2>; }; &qspi { From ee06c5390f2f1e2f1bc23e14a7cd8665c1e42ff4 Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Wed, 27 Apr 2022 12:27:21 +0800 Subject: [PATCH 03/10] ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS Bit[7-4] for both register seq2core and core2seq handshake in HPS are not required for triggering DDR re-calibration or resetting EMIF. So, ignoring these bits just for playing it safe. Signed-off-by: Tien Fong Chee --- drivers/ddr/altera/sdram_soc64.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 7460f8c220..07a0f9f2ae 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -53,7 +53,7 @@ struct altera_sdram_plat { #define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1) #define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16) #define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) -#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff +#define DDR_HMC_RSTHANDSHAKE_MASK 0x0000000f #define DDR_HMC_CORE2SEQ_INT_REQ 0xF #define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f From 39bbcc341bda435899cb623a19d20727ca98c67a Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Wed, 27 Apr 2022 12:52:42 +0800 Subject: [PATCH 04/10] ddr: altera: Stratix10: Use phys_size_t for memory size Replace with phys_size_t for all memory size variables declaration for the sake of scalability. phys_size_t is defined in /arch/arm/include/asm/types.h. Signed-off-by: Tien Fong Chee --- drivers/ddr/altera/sdram_s10.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index d3a6d21860..4d36fb4533 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2018 Intel Corporation + * Copyright (C) 2016-2022 Intel Corporation * */ @@ -277,7 +277,7 @@ int sdram_mmr_init_full(struct udevice *dev) DDR_SCH_DEVTODEV); /* assigning the SDRAM size */ - unsigned long long size = sdram_calculate_size(plat); + phys_size_t size = sdram_calculate_size(plat); /* If the size is invalid, use default Config size */ if (size <= 0) hw_size = PHYS_SDRAM_1_SIZE; From 163863d572a7bc52b58743b3de4aafbc24dd12c8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 20 Dec 2021 22:57:57 +0100 Subject: [PATCH 05/10] arm: socfpga: vining: Unmount UBIFS and detach UBI in ubi_load script Clean up in ubiload script. Unmount UBIFS from which kernel image was loaded and detach UBI on which the UBIFS is located, otherwise message similar to the following is printed just before booting kernel: Removing MTD device #7 (rootfs) with use count 1 Error when deleting partition "rootfs" (-16) Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee Reviewed-by: Tien Fong Chee --- include/configs/socfpga_vining_fpga.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 9455e4cb56..c333c931ab 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -116,7 +116,8 @@ "addargs=run addcons addmtd addmisc\0" \ "ubiload=" \ "ubi part ${ubimtd} ; ubifsmount ${ubipart} ; " \ - "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \ + "ubifsload ${kernel_addr_r} /boot/${bootfile} ; " \ + "ubifsumount ; ubi detach\0" \ "netload=" \ "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ "miscargs=nohlt panic=1\0" \ From 373c1428a0374c29f19cca76f12c0e93378a634a Mon Sep 17 00:00:00 2001 From: Dinesh Maniyam Date: Wed, 1 Jun 2022 15:54:59 +0800 Subject: [PATCH 06/10] arch: arm: socfpga: timer_s10: Override udelay for secure section Override __udelay() as 'always inlined' function so that PSCI code run in '__secure' section can call this delay function as well. Signed-off-by: Chee Hong Ang Signed-off-by: Dinesh Maniyam Reviewed-by: Tien Fong Chee --- arch/arm/mach-socfpga/timer_s10.c | 34 ++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c index 7d5598e1a3..84b13ce9d3 100644 --- a/arch/arm/mach-socfpga/timer_s10.c +++ b/arch/arm/mach-socfpga/timer_s10.c @@ -1,11 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2017-2018 Intel Corporation + * Copyright (C) 2017-2022 Intel Corporation * */ #include #include +#include #include #include @@ -26,3 +27,34 @@ int timer_init(void) #endif return 0; } + +__always_inline u64 __get_time_stamp(void) +{ + u64 cntpct; + + isb(); + asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct)); + + return cntpct; +} + +__always_inline uint64_t __usec_to_tick(unsigned long usec) +{ + u64 tick = usec; + u64 cntfrq; + + asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq)); + tick *= cntfrq; + do_div(tick, 1000000); + + return tick; +} + +__always_inline void __udelay(unsigned long usec) +{ + /* get current timestamp */ + u64 tmp = __get_time_stamp() + __usec_to_tick(usec); + + while (__get_time_stamp() < tmp + 1) /* loop till event */ + ; +} \ No newline at end of file From 7f8533078291bc1c96125ec0619ffd5d01ecc83d Mon Sep 17 00:00:00 2001 From: Dinesh Maniyam Date: Tue, 31 May 2022 16:05:56 +0800 Subject: [PATCH 07/10] arm: dts: socfpga: agilex: Add freeze controller node The freeze controller is required for FPGA partial reconfig. This node is disable on default. Enable this node via u-boot fdt command when needed. Signed-off-by: Yau Wai Gan Signed-off-by: Dinesh Maniyam Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index 6cac36a1fc..2400fad18a 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -2,7 +2,7 @@ /* * U-Boot additions * - * Copyright (C) 2019 Intel Corporation + * Copyright (C) 2019-2022 Intel Corporation */ #include "socfpga_agilex-u-boot.dtsi" @@ -11,6 +11,15 @@ aliases { spi0 = &qspi; i2c0 = &i2c1; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@f9000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0xf9000450 0x00000010>; + status = "disabled"; + }; }; memory { From 5474fb894cba4de1f8735e02155ca85d81af03de Mon Sep 17 00:00:00 2001 From: Dinesh Maniyam Date: Tue, 31 May 2022 16:15:17 +0800 Subject: [PATCH 08/10] arm: dts: socfpga: stratix10: Add freeze controller node The freeze controller is required for FPGA partial reconfig. This node is disable on default. Enable this node via u-boot fdt command when needed. Signed-off-by: Yau Wai Gan Signed-off-by: Dinesh Maniyam Reviewed-by: Tien Fong Chee --- arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi index 61df425f14..75a29045da 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi @@ -2,7 +2,7 @@ /* * U-Boot additions * - * Copyright (C) 2019-2020 Intel Corporation + * Copyright (C) 2019-2022 Intel Corporation */ #include "socfpga_stratix10-u-boot.dtsi" @@ -10,6 +10,15 @@ /{ aliases { spi0 = &qspi; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@f9000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0xf9000450 0x00000010>; + status = "disabled"; + }; }; }; From d192adafebcd5e742a229aedbdcc7d6957d68f02 Mon Sep 17 00:00:00 2001 From: Dinesh Maniyam Date: Wed, 1 Jun 2022 15:57:25 +0800 Subject: [PATCH 09/10] drivers: cache: ncore: Disable snoop filter There is hardware bug in NCORE CCU IP and it is causing an issue in the coherent directory tracking of outstanding cache lines. The workaround is disabling snoop filter. Signed-off-by: Dinesh Maniyam Reviewed-by: Tien Fong Chee --- drivers/cache/cache-ncore.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/cache/cache-ncore.c b/drivers/cache/cache-ncore.c index 3beff780de..117d2b91ab 100644 --- a/drivers/cache/cache-ncore.c +++ b/drivers/cache/cache-ncore.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019 Intel Corporation + * Copyright (C) 2019-2022 Intel Corporation * */ #include @@ -81,8 +81,8 @@ static void ncore_ccu_init_dirs(void __iomem *base) hang(); } - /* Enable snoop filter, a bit per snoop filter */ - setbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i), + /* Disable snoop filter, a bit per snoop filter */ + clrbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i), BIT(f)); } } From 32e0379143b433e29d76404f5f4c279067e48853 Mon Sep 17 00:00:00 2001 From: Dinesh Maniyam Date: Wed, 1 Jun 2022 18:49:02 +0800 Subject: [PATCH 10/10] ddr: altera: soc64: Integer fix overflow that caused DDR size mismatched Convert the constant integer to 'phys_size_t' to avoid overflow when calculating the SDRAM size. Signed-off-by: Dinesh Maniyam Reviewed-by: Tien Fong Chee --- drivers/ddr/altera/sdram_soc64.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index d6baac2410..9b1710c135 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2021 Intel Corporation + * Copyright (C) 2016-2022 Intel Corporation * */ @@ -239,7 +239,8 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat) { u32 dramaddrw = hmc_readl(plat, DRAMADDRW); - phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + + phys_size_t size = (phys_size_t)1 << + (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +