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https://github.com/AsahiLinux/u-boot
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imx8mn: synchronise device tree with linux
Synchronise device tree with linux v6.1-rc3.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8m{m,n,p}-venice-*
This commit is contained in:
Marcel Ziswiler
Stefano Babic
parent
0b42fdca2d
commit
f067b59743
6 changed files with 101 additions and 18 deletions
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@ -47,6 +47,11 @@
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linux,autosuspend-period = <125>;
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};
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audio_codec_bt_sco: audio-codec-bt-sco {
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compatible = "linux,bt-sco";
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#sound-dai-cells = <1>;
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};
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wm8524: audio-codec {
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#sound-dai-cells = <0>;
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compatible = "wlf,wm8524";
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@ -57,6 +62,25 @@
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clock-names = "mclk";
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};
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sound-bt-sco {
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compatible = "simple-audio-card";
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simple-audio-card,name = "bt-sco-audio";
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simple-audio-card,format = "dsp_a";
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simple-audio-card,bitclock-inversion;
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simple-audio-card,frame-master = <&btcpu>;
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simple-audio-card,bitclock-master = <&btcpu>;
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btcpu: simple-audio-card,cpu {
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sound-dai = <&sai2>;
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dai-tdm-slot-num = <2>;
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dai-tdm-slot-width = <16>;
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};
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simple-audio-card,codec {
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sound-dai = <&audio_codec_bt_sco 1>;
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};
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};
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sound-wm8524 {
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compatible = "fsl,imx-audio-wm8524";
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model = "wm8524-audio";
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@ -183,6 +207,16 @@
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};
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};
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&sai2 {
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#sound-dai-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai2>;
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assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
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assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
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assigned-clock-rates = <24576000>;
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status = "okay";
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};
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&sai3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai3>;
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@ -354,6 +388,15 @@
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>;
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};
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pinctrl_sai2: sai2grp {
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fsl,pins = <
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MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
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MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
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MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
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MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
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>;
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};
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pinctrl_sai3: sai3grp {
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fsl,pins = <
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MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
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@ -26,19 +26,19 @@
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gpio-keys {
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compatible = "gpio-keys";
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back {
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key-back {
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label = "Back";
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gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_BACK>;
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};
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home {
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key-home {
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label = "Home";
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gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_HOME>;
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};
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menu {
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key-menu {
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label = "Menu";
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gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_MENU>;
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@ -39,13 +39,13 @@
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gpio-keys {
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compatible = "gpio-keys";
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user-pb {
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key-user-pb {
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label = "user_pb";
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gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
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linux,code = <BTN_0>;
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};
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user-pb1x {
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key-user-pb1x {
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label = "user_pb1x";
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linux,code = <BTN_1>;
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interrupt-parent = <&gsc>;
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@ -59,14 +59,14 @@
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interrupts = <1>;
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};
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eeprom-wp {
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key-eeprom-wp {
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label = "eeprom_wp";
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linux,code = <BTN_3>;
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interrupt-parent = <&gsc>;
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interrupts = <2>;
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};
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tamper {
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key-tamper {
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label = "tamper";
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linux,code = <BTN_4>;
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interrupt-parent = <&gsc>;
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@ -213,7 +213,6 @@
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compatible = "microchip,mcp2515";
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reg = <0>;
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clocks = <&can20m>;
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oscillator-frequency = <20000000>;
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interrupt-parent = <&gpio2>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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spi-max-frequency = <10000000>;
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@ -269,7 +269,7 @@
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arm,no-tick-in-suspend;
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};
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soc@0 {
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soc: soc@0 {
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compatible = "fsl,imx8mn-soc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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@ -672,7 +672,6 @@
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<&clk IMX8MN_CLK_GPU_SHADER>,
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<&clk IMX8MN_CLK_GPU_BUS_ROOT>,
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<&clk IMX8MN_CLK_GPU_AHB>;
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resets = <&src IMX8MQ_RESET_GPU_RESET>;
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};
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pgc_dispmix: power-domain@3 {
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@ -857,6 +856,7 @@
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compatible = "fsl,sec-v4.0-job-ring";
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reg = <0x1000 0x1000>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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sec_jr1: jr@2000 {
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41
include/dt-bindings/interconnect/imx8mn.h
Normal file
41
include/dt-bindings/interconnect/imx8mn.h
Normal file
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@ -0,0 +1,41 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Interconnect framework driver for i.MX SoC
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*
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* Copyright (c) 2019-2020, NXP
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MN_H
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#define __DT_BINDINGS_INTERCONNECT_IMX8MN_H
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#define IMX8MN_ICN_NOC 1
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#define IMX8MN_ICS_DRAM 2
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#define IMX8MN_ICS_OCRAM 3
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#define IMX8MN_ICM_A53 4
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#define IMX8MN_ICM_GPU 5
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#define IMX8MN_ICN_GPU 6
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#define IMX8MN_ICM_CSI1 7
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#define IMX8MN_ICM_CSI2 8
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#define IMX8MN_ICM_ISI 9
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#define IMX8MN_ICM_LCDIF 10
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#define IMX8MN_ICN_MIPI 11
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#define IMX8MN_ICM_USB 12
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#define IMX8MN_ICM_SDMA2 13
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#define IMX8MN_ICM_SDMA3 14
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#define IMX8MN_ICN_AUDIO 15
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#define IMX8MN_ICN_ENET 16
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#define IMX8MN_ICM_ENET 17
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#define IMX8MN_ICM_NAND 18
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#define IMX8MN_ICM_SDMA1 19
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#define IMX8MN_ICM_USDHC1 20
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#define IMX8MN_ICM_USDHC2 21
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#define IMX8MN_ICM_USDHC3 22
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#define IMX8MN_ICN_MAIN 23
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#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MN_H */
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