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Tegra30: Add/enable Cardhu build (T30 reference board)
This build is stripped down. It boots to the command prompt. GPIO is the only peripheral supported. Others TBD. include/configs/tegra-common.h now holds common config options for Tegra SoCs. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Tom Warren
Tom Warren
parent
6d6c0baebe
commit
f01b631f7d
9 changed files with 867 additions and 175 deletions
44
board/nvidia/cardhu/Makefile
Normal file
44
board/nvidia/cardhu/Makefile
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@ -0,0 +1,44 @@
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#
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# (C) Copyright 2010-2012
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# NVIDIA Corporation <www.nvidia.com>
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#
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := $(BOARD).o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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39
board/nvidia/cardhu/cardhu.c
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39
board/nvidia/cardhu/cardhu.c
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@ -0,0 +1,39 @@
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/*
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* (C) Copyright 2010-2012
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/pinmux.h>
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#include "pinmux-config-cardhu.h"
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/*
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* Routine: pinmux_init
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* Description: Do individual peripheral pinmux configs
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*/
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void pinmux_init(void)
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{
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pinmux_config_table(tegra3_pinmux_common,
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ARRAY_SIZE(tegra3_pinmux_common));
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pinmux_config_table(unused_pins_lowpower,
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ARRAY_SIZE(unused_pins_lowpower));
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}
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151
board/nvidia/cardhu/cardhu.c.mmc
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151
board/nvidia/cardhu/cardhu.c.mmc
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@ -0,0 +1,151 @@
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/*
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* (C) Copyright 2010-2012
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/pinmux.h>
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#include "pinmux-config-cardhu.h"
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#include <asm/arch/clock.h>
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#include <asm/arch/gp_padctrl.h>
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#include <asm/arch/pmu.h>
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#include <asm/arch/sdmmc.h>
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#include <asm/arch-tegra/mmc.h>
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#include <asm/arch-tegra/tegra_mmc.h>
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#include <mmc.h>
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#include <i2c.h>
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/*
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* Routine: pinmux_init
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* Description: Do individual peripheral pinmux configs
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*/
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void pinmux_init(void)
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{
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pinmux_config_table(tegra3_pinmux_common,
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ARRAY_SIZE(tegra3_pinmux_common));
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pinmux_config_table(unused_pins_lowpower,
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ARRAY_SIZE(unused_pins_lowpower));
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}
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#if defined(CONFIG_MMC)
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/*
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* Routine: pin_mux_mmc
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* Description: setup the pin muxes/tristate values for the SDMMC(s)
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*/
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static void pin_mux_mmc(void)
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{
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}
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/* Do I2C/PMU writes to bring up SD card bus power */
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static void board_sdmmc_voltage_init(void)
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{
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uchar reg, data_buffer[1];
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int i;
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i2c_set_bus_num(0); /* PMU is on bus 0 */
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data_buffer[0] = 0x65;
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reg = 0x32;
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for (i = 0; i < MAX_I2C_RETRY; ++i) {
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if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
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udelay(100);
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}
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data_buffer[0] = 0x09;
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reg = 0x67;
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for (i = 0; i < MAX_I2C_RETRY; ++i) {
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if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
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udelay(100);
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}
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}
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static void pad_init_mmc(struct tegra_mmc *reg)
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{
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struct apb_misc_gp_ctlr *const gpc =
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(struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
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struct sdmmc_ctlr *const sdmmc = (struct sdmmc_ctlr *)reg;
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u32 val, offset = (unsigned int)reg;
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u32 padcfg, padmask;
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debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)sdmmc);
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/* Set the pad drive strength for SDMMC1 or 3 only */
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if (offset != TEGRA_SDMMC1_BASE && offset != TEGRA_SDMMC3_BASE) {
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debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
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__func__);
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return;
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}
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/* Set pads as per T30 TRM, section 24.6.1.2 */
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padcfg = (GP_SDIOCFG_DRVUP_SLWF | GP_SDIOCFG_DRVDN_SLWR | \
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GP_SDIOCFG_DRVUP | GP_SDIOCFG_DRVDN);
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padmask = 0x00000FFF;
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if (offset == TEGRA_SDMMC1_BASE) {
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val = readl(&gpc->sdio1cfg);
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val &= padmask;
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val |= padcfg;
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writel(val, &gpc->sdio1cfg);
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} else { /* SDMMC3 */
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val = readl(&gpc->sdio3cfg);
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val &= padmask;
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val |= padcfg;
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writel(val, &gpc->sdio3cfg);
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}
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val = readl(&sdmmc->sdmmc_sdmemcomp_pad_ctrl);
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val &= 0xFFFFFFF0;
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val |= MEMCOMP_PADCTRL_VREF;
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writel(val, &sdmmc->sdmmc_sdmemcomp_pad_ctrl);
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val = readl(&sdmmc->sdmmc_auto_cal_config);
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val &= 0xFFFF0000;
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val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
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writel(val, &sdmmc->sdmmc_auto_cal_config);
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}
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/* this is a weak define that we are overriding */
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int board_mmc_init(bd_t *bd)
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{
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debug("board_mmc_init called\n");
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/* Turn on SD-card bus power */
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board_sdmmc_voltage_init();
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/* Set up the SDMMC pads as per the TRM */
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pad_init_mmc((struct tegra_mmc *)TEGRA_SDMMC1_BASE);
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/* Enable muxes, etc. for SDMMC controllers */
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pin_mux_mmc();
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/* init dev 0 (SDMMC4), ("HSMMC") with 8-bit bus */
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tegra_mmc_init(0, 8, -1, -1);
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/* init dev 1 (SDMMC0), ("SDIO") with 8-bit bus */
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tegra_mmc_init(1, 8, -1, -1);
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return 0;
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}
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#endif /* MMC */
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329
board/nvidia/cardhu/pinmux-config-cardhu.h
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329
board/nvidia/cardhu/pinmux-config-cardhu.h
Normal file
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@ -0,0 +1,329 @@
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/*
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* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _PINMUX_CONFIG_CARDHU_H_
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#define _PINMUX_CONFIG_CARDHU_H_
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#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
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{ \
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.pingroup = PINGRP_##_pingroup, \
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.func = PMUX_FUNC_##_mux, \
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.pull = PMUX_PULL_##_pull, \
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.tristate = PMUX_TRI_##_tri, \
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.io = PMUX_PIN_##_io, \
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.lock = PMUX_PIN_LOCK_DEFAULT, \
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.od = PMUX_PIN_OD_DEFAULT, \
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.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
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}
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#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
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{ \
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.pingroup = PINGRP_##_pingroup, \
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.func = PMUX_FUNC_##_mux, \
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.pull = PMUX_PULL_##_pull, \
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.tristate = PMUX_TRI_##_tri, \
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.io = PMUX_PIN_##_io, \
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.lock = PMUX_PIN_LOCK_##_lock, \
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.od = PMUX_PIN_OD_##_od, \
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.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
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}
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#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
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{ \
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.pingroup = PINGRP_##_pingroup, \
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.func = PMUX_FUNC_##_mux, \
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.pull = PMUX_PULL_##_pull, \
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.tristate = PMUX_TRI_##_tri, \
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.io = PMUX_PIN_##_io, \
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.lock = PMUX_PIN_LOCK_##_lock, \
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.od = PMUX_PIN_OD_DEFAULT, \
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.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
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}
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static struct pingroup_config tegra3_pinmux_common[] = {
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/* SDMMC1 pinmux */
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DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
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/* SDMMC3 pinmux */
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DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT6, RSVD1, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(SDMMC3_DAT7, RSVD1, NORMAL, NORMAL, INPUT),
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/* SDMMC4 pinmux */
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LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
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LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
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/* I2C1 pinmux */
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I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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/* I2C2 pinmux */
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I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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|
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/* I2C3 pinmux */
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I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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|
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/* I2C4 pinmux */
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I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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|
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/* Power I2C pinmux */
|
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I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
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|
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DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
|
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DEFAULT_PINMUX(ULPI_DATA3, RSVD1, NORMAL, NORMAL, INPUT),
|
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DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
|
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DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
|
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DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(GPIO_PV2, OWR, NORMAL, NORMAL, OUTPUT),
|
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DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
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DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT),
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DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
|
||||
LV_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D2, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_MCLK, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_CS2_N, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
|
||||
DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
|
||||
DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
|
||||
DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* KBC keys */
|
||||
DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW11, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
|
||||
|
||||
DEFAULT_PINMUX(SPI2_CS1_N, SPI2, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
|
||||
|
||||
/* GPIOs */
|
||||
/* SDMMC1 CD gpio */
|
||||
DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT),
|
||||
/* SDMMC1 WP gpio */
|
||||
LV_PINMUX(VI_D11, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
|
||||
/* Touch panel GPIO */
|
||||
/* Touch IRQ */
|
||||
DEFAULT_PINMUX(GMI_AD12, NAND, UP, NORMAL, INPUT),
|
||||
|
||||
/* Touch RESET */
|
||||
DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, OUTPUT),
|
||||
|
||||
/* Power rails GPIO */
|
||||
DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT),
|
||||
|
||||
LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D8, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_D9, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_PCLK, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_HSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
LV_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
|
||||
};
|
||||
|
||||
static struct pingroup_config unused_pins_lowpower[] = {
|
||||
DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
|
||||
DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
|
||||
};
|
||||
|
||||
#endif /* _PINMUX_CONFIG_CARDHU_H_ */
|
||||
|
|
@ -290,6 +290,7 @@ harmony arm armv7:arm720t harmony nvidia
|
|||
seaboard arm armv7:arm720t seaboard nvidia tegra20
|
||||
ventana arm armv7:arm720t ventana nvidia tegra20
|
||||
whistler arm armv7:arm720t whistler nvidia tegra20
|
||||
cardhu arm armv7:arm720t cardhu nvidia tegra30
|
||||
colibri_t20_iris arm armv7:arm720t colibri_t20_iris toradex tegra20
|
||||
u8500_href arm armv7 u8500 st-ericsson u8500
|
||||
snowball arm armv7 snowball st-ericsson u8500
|
||||
|
|
|
|||
|
|
@ -119,33 +119,6 @@
|
|||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Memory layout for where various images get loaded by boot scripts:
|
||||
*
|
||||
* scriptaddr can be pretty much anywhere that doesn't conflict with something
|
||||
* else. Put it above BOOTMAPSZ to eliminate conflicts.
|
||||
*
|
||||
* kernel_addr_r must be within the first 128M of RAM in order for the
|
||||
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
|
||||
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
|
||||
* should not overlap that area, or the kernel will have to copy itself
|
||||
* somewhere else before decompression. Similarly, the address of any other
|
||||
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
|
||||
* this up to 16M allows for a sizable kernel to be decompressed below the
|
||||
* compressed load address.
|
||||
*
|
||||
* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
|
||||
* the compressed kernel to be up to 16M too.
|
||||
*
|
||||
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
|
||||
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
|
||||
*/
|
||||
#define MEM_LAYOUT_ENV_SETTINGS \
|
||||
"scriptaddr=0x10000000\0" \
|
||||
"kernel_addr_r=0x01000000\0" \
|
||||
"fdt_addr_r=0x02000000\0" \
|
||||
"ramdisk_addr_r=0x02100000\0" \
|
||||
|
||||
#ifdef CONFIG_TEGRA_KEYBOARD
|
||||
#define STDIN_KBD_KBC ",tegra-kbc"
|
||||
#else
|
||||
|
|
|
|||
160
include/configs/tegra-common.h
Normal file
160
include/configs/tegra-common.h
Normal file
|
|
@ -0,0 +1,160 @@
|
|||
/*
|
||||
* (C) Copyright 2010-2012
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __TEGRA_COMMON_H
|
||||
#define __TEGRA_COMMON_H
|
||||
#include <asm/sizes.h>
|
||||
#include <linux/stringify.h>
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
|
||||
#define CONFIG_TEGRA /* which is a Tegra generic machine */
|
||||
#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
|
||||
#include <asm/arch/tegra.h> /* get chip and board defs */
|
||||
|
||||
/*
|
||||
* Display CPU and Board information
|
||||
*/
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
|
||||
|
||||
/* Environment */
|
||||
#define CONFIG_ENV_VARS_UBOOT_CONFIG
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
|
||||
|
||||
/*
|
||||
* PllX Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
|
||||
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* include default commands */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
/* remove unused commands */
|
||||
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
|
||||
#undef CONFIG_CMD_FPGA /* FPGA configuration support */
|
||||
#undef CONFIG_CMD_IMI
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#undef CONFIG_CMD_NFS /* NFS support */
|
||||
#undef CONFIG_CMD_NET /* network support */
|
||||
|
||||
/* turn on command-line edit/hist/auto */
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_COMMAND_HISTORY
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
#define CONFIG_CONSOLE_MUX
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#define CONFIG_SYS_PROMPT V_PROMPT
|
||||
/*
|
||||
* Increasing the size of the IO buffer as default nfsargs size is more
|
||||
* than 256 and so it is not possible to edit it
|
||||
*/
|
||||
#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
|
||||
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
|
||||
|
||||
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
|
||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#define CONFIG_TEGRA_GPIO
|
||||
#define CONFIG_CMD_GPIO
|
||||
#define CONFIG_CMD_ENTERRCM
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_RAM_DEVICE
|
||||
#define CONFIG_SPL_BOARD_INIT
|
||||
#define CONFIG_SPL_NAND_SIMPLE
|
||||
#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \
|
||||
CONFIG_SPL_TEXT_BASE)
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
|
||||
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_GPIO_SUPPORT
|
||||
|
||||
#endif /* _TEGRA_COMMON_H_ */
|
||||
|
|
@ -21,80 +21,81 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __TEGRA20_COMMON_H
|
||||
#define __TEGRA20_COMMON_H
|
||||
#include <asm/sizes.h>
|
||||
#include <linux/stringify.h>
|
||||
#ifndef _TEGRA20_COMMON_H_
|
||||
#define _TEGRA20_COMMON_H_
|
||||
#include "tegra-common.h"
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
|
||||
#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
|
||||
#define CONFIG_TEGRA /* which is a Tegra generic machine */
|
||||
#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
|
||||
#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
/* Environment information, boards can override if required */
|
||||
#define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */
|
||||
|
||||
#include <asm/arch/tegra.h> /* get chip and board defs */
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */
|
||||
#define CONFIG_STACKBASE 0x02800000 /* 40MB */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0010E000
|
||||
|
||||
/*
|
||||
* Memory layout for where various images get loaded by boot scripts:
|
||||
*
|
||||
* scriptaddr can be pretty much anywhere that doesn't conflict with something
|
||||
* else. Put it above BOOTMAPSZ to eliminate conflicts.
|
||||
*
|
||||
* kernel_addr_r must be within the first 128M of RAM in order for the
|
||||
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
|
||||
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
|
||||
* should not overlap that area, or the kernel will have to copy itself
|
||||
* somewhere else before decompression. Similarly, the address of any other
|
||||
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
|
||||
* this up to 16M allows for a sizable kernel to be decompressed below the
|
||||
* compressed load address.
|
||||
*
|
||||
* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
|
||||
* the compressed kernel to be up to 16M too.
|
||||
*
|
||||
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
|
||||
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
|
||||
*/
|
||||
#define MEM_LAYOUT_ENV_SETTINGS \
|
||||
"scriptaddr=0x10000000\0" \
|
||||
"kernel_addr_r=0x01000000\0" \
|
||||
"fdt_addr_r=0x02000000\0" \
|
||||
"ramdisk_addr_r=0x02100000\0"
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x00108000
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
|
||||
#define CONFIG_SPL_STACK 0x000ffffc
|
||||
|
||||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
|
||||
|
||||
/* Align LCD to 1MB boundary */
|
||||
#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
|
||||
|
||||
/*
|
||||
* Display CPU and Board information
|
||||
*/
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
|
||||
|
||||
#ifdef CONFIG_TEGRA_LP0
|
||||
#define TEGRA_LP0_ADDR 0x1C406000
|
||||
#define TEGRA_LP0_SIZE 0x2000
|
||||
#define TEGRA_LP0_VEC \
|
||||
"lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
|
||||
"lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
|
||||
"@" __stringify(TEGRA_LP0_ADDR) " "
|
||||
#else
|
||||
#define TEGRA_LP0_VEC
|
||||
#endif
|
||||
|
||||
/* Environment */
|
||||
#define CONFIG_ENV_VARS_UBOOT_CONFIG
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
|
||||
|
||||
/*
|
||||
* PllX Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
|
||||
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
|
||||
115200}
|
||||
|
||||
/*
|
||||
* This parameter affects a TXFILLTUNING field that controls how much data is
|
||||
* sent to the latency fifo before it is sent to the wire. Without this
|
||||
|
|
@ -107,105 +108,13 @@
|
|||
/* Total I2C ports on Tegra20 */
|
||||
#define TEGRA_I2C_NUM_CONTROLLERS 4
|
||||
|
||||
/* include default commands */
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_PARTITION_UUIDS
|
||||
#define CONFIG_CMD_PART
|
||||
|
||||
/* remove unused commands */
|
||||
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
|
||||
#undef CONFIG_CMD_FPGA /* FPGA configuration support */
|
||||
#undef CONFIG_CMD_IMI
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#undef CONFIG_CMD_NFS /* NFS support */
|
||||
#undef CONFIG_CMD_NET /* network support */
|
||||
|
||||
/* turn on command-line edit/hist/auto */
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_COMMAND_HISTORY
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
#define CONFIG_CONSOLE_MUX
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
|
||||
#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
|
||||
#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#define CONFIG_SYS_PROMPT V_PROMPT
|
||||
/*
|
||||
* Increasing the size of the IO buffer as default nfsargs size is more
|
||||
* than 256 and so it is not possible to edit it
|
||||
*/
|
||||
#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_STACKBASE 0x2800000 /* 40MB */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
|
||||
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0010c000
|
||||
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
|
||||
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#define CONFIG_TEGRA_GPIO
|
||||
#define CONFIG_CMD_GPIO
|
||||
#define CONFIG_CMD_ENTERRCM
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_RAM_DEVICE
|
||||
#define CONFIG_SPL_BOARD_INIT
|
||||
#define CONFIG_SPL_NAND_SIMPLE
|
||||
#define CONFIG_SPL_TEXT_BASE 0x00108000
|
||||
#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \
|
||||
CONFIG_SPL_TEXT_BASE)
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
|
||||
#define CONFIG_SPL_STACK 0x000ffffc
|
||||
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
#define CONFIG_SPL_GPIO_SUPPORT
|
||||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
|
||||
|
||||
#define CONFIG_SYS_NAND_SELF_INIT
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* Misc utility code */
|
||||
#define CONFIG_BOUNCE_BUFFER
|
||||
|
||||
#endif /* __TEGRA20_COMMON_H */
|
||||
#endif /* _TEGRA20_COMMON_H_ */
|
||||
|
|
|
|||
86
include/configs/tegra30-common.h
Normal file
86
include/configs/tegra30-common.h
Normal file
|
|
@ -0,0 +1,86 @@
|
|||
/*
|
||||
* (C) Copyright 2010-2012
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA30_COMMON_H_
|
||||
#define _TEGRA30_COMMON_H_
|
||||
#include "tegra-common.h"
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */
|
||||
|
||||
/* Environment information, boards can override if required */
|
||||
#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
|
||||
#define CONFIG_STACKBASE 0x82800000 /* 40MB */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_SYS_TEXT_BASE 0x8010E000
|
||||
|
||||
/*
|
||||
* Memory layout for where various images get loaded by boot scripts:
|
||||
*
|
||||
* scriptaddr can be pretty much anywhere that doesn't conflict with something
|
||||
* else. Put it above BOOTMAPSZ to eliminate conflicts.
|
||||
*
|
||||
* kernel_addr_r must be within the first 128M of RAM in order for the
|
||||
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
|
||||
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
|
||||
* should not overlap that area, or the kernel will have to copy itself
|
||||
* somewhere else before decompression. Similarly, the address of any other
|
||||
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
|
||||
* this up to 16M allows for a sizable kernel to be decompressed below the
|
||||
* compressed load address.
|
||||
*
|
||||
* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
|
||||
* the compressed kernel to be up to 16M too.
|
||||
*
|
||||
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
|
||||
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
|
||||
*/
|
||||
#define MEM_LAYOUT_ENV_SETTINGS \
|
||||
"scriptaddr=0x90000000\0" \
|
||||
"kernel_addr_r=0x81000000\0" \
|
||||
"fdt_addr_r=0x82000000\0" \
|
||||
"ramdisk_addr_r=0x82100000\0"
|
||||
|
||||
/* Defines for SPL */
|
||||
#define CONFIG_SPL_TEXT_BASE 0x80108000
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
|
||||
#define CONFIG_SPL_STACK 0x800ffffc
|
||||
|
||||
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra30/u-boot-spl.lds"
|
||||
|
||||
#endif /* _TEGRA30_COMMON_H_ */
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||||
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