Motion-PRO: Add setting of SDelay reg. to SDRAM controller configuration.

Per AN3221 (MPC5200B SDRAM Initialization and Configuration), the SDelay
register must be written a value of 0x00000004 as the first step of the
SDRAM contorller configuration.

Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
This commit is contained in:
Bartlomiej Sieka 2007-10-23 11:36:07 +02:00
parent 5441f61a3d
commit eff501904d

View file

@ -138,6 +138,12 @@ long int initdram(int board_type)
#ifndef CFG_RAMBOOT #ifndef CFG_RAMBOOT
ulong test1, test2; ulong test1, test2;
/* According to AN3221 (MPC5200B SDRAM Initialization and
* Configuration), the SDelay register must be written a value of
* 0x00000004 as the first step of the SDRAM contorller configuration.
*/
*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
/* configure SDRAM start/end for detection */ /* configure SDRAM start/end for detection */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */