mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 21:54:01 +00:00
* Add start-up delay to make sure power has stabilized before
attempting to switch on USB on SX1 board. * Patch by Josef Wagner, 18 Mar 2004: - Add support for MicroSys XM250 board (PXA255) - Add support for MicroSys PM828 board (MPC8280) - Add support for 32 MB Flash on PM825/826 - new SDRAM refresh rate for PM825/PM826 - added support for MicroSys PM520 (MPC5200) - replaced Query by Identify command in CPU86/flash.c to support 28F160F3B * Fix wrap around problem with udelay() on ARM920T * Add support for Macronix flash on TRAB board
This commit is contained in:
parent
7d7ce4125f
commit
efa329cb89
35 changed files with 4510 additions and 78 deletions
16
CHANGELOG
16
CHANGELOG
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@ -2,6 +2,22 @@
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Changes for U-Boot 1.0.2:
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======================================================================
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* Add start-up delay to make sure power has stabilized before
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attempting to switch on USB on SX1 board.
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* Patch by Josef Wagner, 18 Mar 2004:
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- Add support for MicroSys XM250 board (PXA255)
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- Add support for MicroSys PM828 board (MPC8280)
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- Add support for 32 MB Flash on PM825/826
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- new SDRAM refresh rate for PM825/PM826
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- added support for MicroSys PM520 (MPC5200)
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- replaced Query by Identify command in CPU86/flash.c
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to support 28F160F3B
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* Fix wrap around problem with udelay() on ARM920T
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* Add support for Macronix flash on TRAB board
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* Patch by Pierre Aubert, 15 Mar 2004:
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Fix buffer overflow in IDE identification
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11
MAKEALL
11
MAKEALL
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@ -25,7 +25,7 @@ LIST_5xx=" \
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#########################################################################
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LIST_5xxx=" \
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IceCube_5100 IceCube_5200 EVAL5200 \
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IceCube_5100 IceCube_5200 EVAL5200 PM520 \
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"
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#########################################################################
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@ -85,9 +85,10 @@ LIST_824x=" \
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LIST_8260=" \
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atc cogent_mpc8260 CPU86 ep8260 \
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gw8260 hymod IPHASE4539 MPC8260ADS \
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MPC8266ADS PM826 ppmc8260 RPXsuper \
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rsdproto sacsng sbc8260 SCM \
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TQM8260_AC TQM8260_AD TQM8260_AE ZPC1900 \
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MPC8266ADS PM826 PM828 ppmc8260 \
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RPXsuper rsdproto sacsng sbc8260 \
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SCM TQM8260_AC TQM8260_AD TQM8260_AE \
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ZPC1900 \
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"
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#########################################################################
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@ -145,7 +146,7 @@ LIST_ARM9=" \
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## Xscale Systems
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#########################################################################
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LIST_pxa="cradle csb226 innokom lubbock wepep250"
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LIST_pxa="cradle csb226 innokom lubbock wepep250 xm250"
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LIST_ixp="ixdp425"
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76
Makefile
76
Makefile
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@ -244,6 +244,9 @@ TOP5200_config: unconfig
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@ echo "#define CONFIG_$(@:_config=) 1" >include/config.h
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@./mkconfig -a TOP5200 ppc mpc5xxx top5200 emk
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PM520_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc5xxx pm520
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#########################################################################
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## MPC8xx Systems
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#########################################################################
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@ -652,7 +655,7 @@ XPEDITE1K_config:unconfig
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#########################################################################
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## MPC824x Systems
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#########################################################################
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xtract_82xx = $(subst _ROMBOOT,,$(subst _L2,,$(subst _266MHz,,$(subst _300MHz,,$(subst _config,,$1)))))
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xtract_82xx = $(subst _BIGFLASH,,$(subst _ROMBOOT,,$(subst _L2,,$(subst _266MHz,,$(subst _300MHz,,$(subst _config,,$1))))))
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A3000_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc824x a3000
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@ -747,32 +750,56 @@ MPC8260ADS_config: unconfig
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MPC8266ADS_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc8260 mpc8266ads
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# PM825/PM826 default configuration: small (= 8 MB) Flash / boot from 64-bit flash
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PM825_config \
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PM825_ROMBOOT_config: unconfig
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@echo "#define CONFIG_PCI" >include/config.h
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@./mkconfig -a PM826 ppc mpc8260 pm826
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@cd ./include ; \
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if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
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echo "CONFIG_BOOT_ROM = y" >> config.mk ; \
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echo "... booting from 8-bit flash" ; \
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else \
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echo "CONFIG_BOOT_ROM = n" >> config.mk ; \
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echo "... booting from 64-bit flash" ; \
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fi; \
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echo "export CONFIG_BOOT_ROM" >> config.mk; \
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PM825_ROMBOOT_config \
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PM825_BIGFLASH_config \
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PM825_ROMBOOT_BIGFLASH_config \
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PM826_config \
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PM826_ROMBOOT_config: unconfig
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@./mkconfig $(call xtract_82xx,$@) ppc mpc8260 pm826
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@cd ./include ; \
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if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
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echo "CONFIG_BOOT_ROM = y" >> config.mk ; \
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echo "... booting from 8-bit flash" ; \
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PM826_ROMBOOT_config \
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PM826_BIGFLASH_config \
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PM826_ROMBOOT_BIGFLASH_config: unconfig
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@if [ "$(findstring PM825_,$@)" ] ; then \
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echo "#define CONFIG_PCI" >include/config.h ; \
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else \
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>include/config.h ; \
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fi
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@if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
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echo "... booting from 8-bit flash" ; \
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echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \
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echo "TEXT_BASE = 0xFF800000" >board/pm826/config.tmp ; \
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if [ "$(findstring _BIGFLASH_,$@)" ] ; then \
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echo "... with 32 MB Flash" ; \
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echo "#define CONFIG_FLASH_32MB" >>include/config.h ; \
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fi; \
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else \
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echo "CONFIG_BOOT_ROM = n" >> config.mk ; \
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echo "... booting from 64-bit flash" ; \
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fi; \
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echo "export CONFIG_BOOT_ROM" >> config.mk; \
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if [ "$(findstring _BIGFLASH_,$@)" ] ; then \
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echo "... with 32 MB Flash" ; \
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echo "#define CONFIG_FLASH_32MB" >>include/config.h ; \
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echo "TEXT_BASE = 0x40000000" >board/pm826/config.tmp ; \
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else \
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echo "TEXT_BASE = 0xFF000000" >board/pm826/config.tmp ; \
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fi; \
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fi
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@./mkconfig -a PM826 ppc mpc8260 pm826
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PM828_config \
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PM828_PCI_config \
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PM828_ROMBOOT_config \
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PM828_ROMBOOT_PCI_config: unconfig
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@if [ -z "$(findstring _PCI_,$@)" ] ; then \
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echo "#define CONFIG_PCI" >>include/config.h ; \
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echo "... with PCI enabled" ; \
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else \
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>include/config.h ; \
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fi
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@if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
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echo "... booting from 8-bit flash" ; \
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echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \
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echo "TEXT_BASE = 0xFF800000" >board/pm826/config.tmp ; \
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fi
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@./mkconfig -a PM828 ppc mpc8260 pm828
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ppmc8260_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc8260 ppmc8260
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@ -1042,6 +1069,9 @@ logodl_config : unconfig
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wepep250_config : unconfig
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@./mkconfig $(@:_config=) arm pxa wepep250
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xm250_config : unconfig
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@./mkconfig $(@:_config=) arm pxa xm250
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#========================================================================
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# i386
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#========================================================================
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@ -41,10 +41,10 @@ ulong flash_int_get_size (volatile unsigned long *baseaddr,
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info->sector_count = info->size = 0;
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info->flash_id = FLASH_UNKNOWN;
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/* Write query command sequence and test FLASH answer
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/* Write identify command sequence and test FLASH answer
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*/
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baseaddr[0] = 0x00980098;
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baseaddr[1] = 0x00980098;
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baseaddr[0] = 0x00900090;
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baseaddr[1] = 0x00900090;
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flashtest_h = baseaddr[0]; /* manufacturer ID */
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flashtest_l = baseaddr[1];
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47
board/pm520/Makefile
Normal file
47
board/pm520/Makefile
Normal file
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@ -0,0 +1,47 @@
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#
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# (C) Copyright 2003-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o flash.o
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend
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#########################################################################
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31
board/pm520/config.mk
Normal file
31
board/pm520/config.mk
Normal file
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@ -0,0 +1,31 @@
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#
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# (C) Copyright 2003-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
|
||||
#
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# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# PM520 board
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#
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TEXT_BASE = 0xfff00000
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# TEXT_BASE = 0x00100000
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PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
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545
board/pm520/flash.c
Normal file
545
board/pm520/flash.c
Normal file
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@ -0,0 +1,545 @@
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/*
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* (C) Copyright 2001
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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||||
* (C) Copyright 2001-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
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||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
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#include <linux/byteorder/swab.h>
|
||||
|
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/* Board support for 1 or 2 flash devices */
|
||||
#define FLASH_PORT_WIDTH32
|
||||
#undef FLASH_PORT_WIDTH16
|
||||
|
||||
#ifdef FLASH_PORT_WIDTH16
|
||||
#define FLASH_PORT_WIDTH ushort
|
||||
#define FLASH_PORT_WIDTHV vu_short
|
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#define SWAP(x) (x)
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#else
|
||||
#define FLASH_PORT_WIDTH ulong
|
||||
#define FLASH_PORT_WIDTHV vu_long
|
||||
#define SWAP(x) (x)
|
||||
#endif
|
||||
|
||||
/* Intel-compatible flash ID */
|
||||
#define INTEL_COMPAT 0x00890089
|
||||
#define INTEL_ALT 0x00B000B0
|
||||
|
||||
/* Intel-compatible flash commands */
|
||||
#define INTEL_PROGRAM 0x00100010
|
||||
#define INTEL_ERASE 0x00200020
|
||||
#define INTEL_CLEAR 0x00500050
|
||||
#define INTEL_LOCKBIT 0x00600060
|
||||
#define INTEL_PROTECT 0x00010001
|
||||
#define INTEL_STATUS 0x00700070
|
||||
#define INTEL_READID 0x00900090
|
||||
#define INTEL_CONFIRM 0x00D000D0
|
||||
#define INTEL_RESET 0xFFFFFFFF
|
||||
|
||||
/* Intel-compatible flash status bits */
|
||||
#define INTEL_FINISHED 0x00800080
|
||||
#define INTEL_OK 0x00800080
|
||||
|
||||
#define FPW FLASH_PORT_WIDTH
|
||||
#define FPWV FLASH_PORT_WIDTHV
|
||||
|
||||
#define mb() __asm__ __volatile__ ("" : : : "memory")
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (FPW *addr, flash_info_t *info);
|
||||
static int write_data (flash_info_t *info, ulong dest, FPW data);
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info);
|
||||
void inline spin_wheel (void);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
int i;
|
||||
ulong size = 0;
|
||||
|
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[i]);
|
||||
flash_get_offsets (CFG_FLASH_BASE, &flash_info[i]);
|
||||
break;
|
||||
default:
|
||||
panic ("configured to many flash banks!\n");
|
||||
break;
|
||||
}
|
||||
size += flash_info[i].size;
|
||||
}
|
||||
|
||||
/* Protect monitor and environment sectors
|
||||
*/
|
||||
flash_protect ( FLAG_PROTECT_SET,
|
||||
CFG_MONITOR_BASE,
|
||||
CFG_MONITOR_BASE + monitor_flash_len - 1,
|
||||
&flash_info[0] );
|
||||
|
||||
flash_protect ( FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR,
|
||||
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
return;
|
||||
}
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
|
||||
info->protect[i] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info (flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_INTEL:
|
||||
printf ("INTEL ");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_28F128J3A:
|
||||
printf ("28F128J3A\n");
|
||||
break;
|
||||
|
||||
case FLASH_28F640J3A:
|
||||
printf ("28F640J3A\n");
|
||||
break;
|
||||
|
||||
case FLASH_28F320J3A:
|
||||
printf ("28F320J3A\n");
|
||||
break;
|
||||
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; ++i) {
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
printf (" %08lX%s",
|
||||
info->start[i],
|
||||
info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
printf ("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
static ulong flash_get_size (FPW *addr, flash_info_t *info)
|
||||
{
|
||||
volatile FPW value;
|
||||
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
addr[0x5555] = (FPW) 0x00AA00AA;
|
||||
addr[0x2AAA] = (FPW) 0x00550055;
|
||||
addr[0x5555] = (FPW) 0x00900090;
|
||||
|
||||
mb ();
|
||||
value = addr[0];
|
||||
|
||||
switch (value) {
|
||||
|
||||
case (FPW) INTEL_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_INTEL;
|
||||
break;
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
mb ();
|
||||
value = addr[1]; /* device ID */
|
||||
|
||||
switch (value) {
|
||||
|
||||
case (FPW) INTEL_ID_28F128J3A:
|
||||
info->flash_id += FLASH_28F128J3A;
|
||||
info->sector_count = 128;
|
||||
info->size = 0x02000000;
|
||||
break; /* => 32 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F640J3A:
|
||||
info->flash_id += FLASH_28F640J3A;
|
||||
info->sector_count = 64;
|
||||
info->size = 0x01000000;
|
||||
break; /* => 16 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F320J3A:
|
||||
info->flash_id += FLASH_28F320J3A;
|
||||
info->sector_count = 32;
|
||||
info->size = 0x00800000;
|
||||
break; /* => 8 MB */
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
break;
|
||||
}
|
||||
|
||||
if (info->sector_count > CFG_MAX_FLASH_SECT) {
|
||||
printf ("** ERROR: sector count %d > max (%d) **\n",
|
||||
info->sector_count, CFG_MAX_FLASH_SECT);
|
||||
info->sector_count = CFG_MAX_FLASH_SECT;
|
||||
}
|
||||
|
||||
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
int flag, prot, sect;
|
||||
ulong type, start, last;
|
||||
int rcode = 0;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
type = (info->flash_id & FLASH_VENDMASK);
|
||||
if ((type != FLASH_MAN_INTEL)) {
|
||||
printf ("Can't erase unknown flash type %08lx - aborted\n",
|
||||
info->flash_id);
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
FPWV *addr = (FPWV *) (info->start[sect]);
|
||||
FPW status;
|
||||
|
||||
printf ("Erasing sector %2d ... ", sect);
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
start = get_timer(0);
|
||||
|
||||
*addr = (FPW) 0x00500050; /* clear status register */
|
||||
*addr = (FPW) 0x00200020; /* erase setup */
|
||||
*addr = (FPW) 0x00D000D0; /* erase confirm */
|
||||
|
||||
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
|
||||
if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
*addr = (FPW) 0x00B000B0; /* suspend erase */
|
||||
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
|
||||
rcode = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
*addr = 0x00500050; /* clear status register cmd. */
|
||||
*addr = 0x00FF00FF; /* resest to read mode */
|
||||
|
||||
printf (" done\n");
|
||||
}
|
||||
}
|
||||
return rcode;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
* 4 - Flash not identified
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp;
|
||||
FPW data;
|
||||
int count, i, l, rc, port_width;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
return 4;
|
||||
}
|
||||
/* get lower word aligned address */
|
||||
#ifdef FLASH_PORT_WIDTH16
|
||||
wp = (addr & ~1);
|
||||
port_width = 2;
|
||||
#else
|
||||
wp = (addr & ~3);
|
||||
port_width = 4;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
}
|
||||
for (; i < port_width && cnt > 0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt == 0 && i < port_width; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
}
|
||||
|
||||
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += port_width;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
count = 0;
|
||||
while (cnt >= port_width) {
|
||||
data = 0;
|
||||
for (i = 0; i < port_width; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += port_width;
|
||||
cnt -= port_width;
|
||||
if (count++ > 0x800) {
|
||||
spin_wheel ();
|
||||
count = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i < port_width; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
}
|
||||
|
||||
return (write_data (info, wp, SWAP (data)));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word or halfword to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_data (flash_info_t *info, ulong dest, FPW data)
|
||||
{
|
||||
FPWV *addr = (FPWV *) dest;
|
||||
ulong status;
|
||||
ulong start;
|
||||
int flag;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*addr & data) != data) {
|
||||
printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
|
||||
return (2);
|
||||
}
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
|
||||
*addr = (FPW) 0x00400040; /* write setup */
|
||||
*addr = data;
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
start = get_timer(0);
|
||||
|
||||
/* wait while polling the status register */
|
||||
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
|
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
||||
*addr = (FPW) 0x00FF00FF; /* restore read mode */
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
|
||||
*addr = (FPW) 0x00FF00FF; /* restore read mode */
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
void inline spin_wheel (void)
|
||||
{
|
||||
static int p = 0;
|
||||
static char w[] = "\\/-";
|
||||
|
||||
printf ("\010%c", w[p]);
|
||||
(++p == 3) ? (p = 0) : 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Set/Clear sector's lock bit, returns:
|
||||
* 0 - OK
|
||||
* 1 - Error (timeout, voltage problems, etc.)
|
||||
*/
|
||||
int flash_real_protect(flash_info_t *info, long sector, int prot)
|
||||
{
|
||||
ulong start;
|
||||
int i;
|
||||
int rc = 0;
|
||||
vu_long *addr = (vu_long *)(info->start[sector]);
|
||||
int flag = disable_interrupts();
|
||||
|
||||
*addr = INTEL_CLEAR; /* Clear status register */
|
||||
if (prot) { /* Set sector lock bit */
|
||||
*addr = INTEL_LOCKBIT; /* Sector lock bit */
|
||||
*addr = INTEL_PROTECT; /* set */
|
||||
}
|
||||
else { /* Clear sector lock bit */
|
||||
*addr = INTEL_LOCKBIT; /* All sectors lock bits */
|
||||
*addr = INTEL_CONFIRM; /* clear */
|
||||
}
|
||||
|
||||
start = get_timer(0);
|
||||
|
||||
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
|
||||
if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
|
||||
printf("Flash lock bit operation timed out\n");
|
||||
rc = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (*addr != INTEL_OK) {
|
||||
printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
|
||||
(uint)addr, (uint)*addr);
|
||||
rc = 1;
|
||||
}
|
||||
|
||||
if (!rc)
|
||||
info->protect[sector] = prot;
|
||||
|
||||
/*
|
||||
* Clear lock bit command clears all sectors lock bits, so
|
||||
* we have to restore lock bits of protected sectors.
|
||||
*/
|
||||
if (!prot)
|
||||
{
|
||||
for (i = 0; i < info->sector_count; i++)
|
||||
{
|
||||
if (info->protect[i])
|
||||
{
|
||||
start = get_timer(0);
|
||||
addr = (vu_long *)(info->start[i]);
|
||||
*addr = INTEL_LOCKBIT; /* Sector lock bit */
|
||||
*addr = INTEL_PROTECT; /* set */
|
||||
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED)
|
||||
{
|
||||
if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT)
|
||||
{
|
||||
printf("Flash lock bit operation timed out\n");
|
||||
rc = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
*addr = INTEL_RESET; /* Reset to read array mode */
|
||||
|
||||
return rc;
|
||||
}
|
193
board/pm520/pm520.c
Normal file
193
board/pm520/pm520.c
Normal file
|
@ -0,0 +1,193 @@
|
|||
/*
|
||||
* (C) Copyright 2003-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc5xxx.h>
|
||||
#include <pci.h>
|
||||
|
||||
#ifndef CFG_RAMBOOT
|
||||
static long int dram_size(long int *base, long int maxsize)
|
||||
{
|
||||
volatile long int *addr;
|
||||
ulong cnt, val;
|
||||
ulong save[32]; /* to make test non-destructive */
|
||||
unsigned char i = 0;
|
||||
|
||||
for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
|
||||
addr = base + cnt; /* pointer arith! */
|
||||
|
||||
save[i++] = *addr;
|
||||
*addr = ~cnt;
|
||||
}
|
||||
|
||||
/* write 0 to base address */
|
||||
addr = base;
|
||||
save[i] = *addr;
|
||||
*addr = 0;
|
||||
|
||||
/* check at base address */
|
||||
if ((val = *addr) != 0) {
|
||||
*addr = save[i];
|
||||
return (0);
|
||||
}
|
||||
|
||||
for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
|
||||
addr = base + cnt; /* pointer arith! */
|
||||
|
||||
val = *addr;
|
||||
*addr = save[--i];
|
||||
|
||||
if (val != (~cnt)) {
|
||||
return (cnt * sizeof (long));
|
||||
}
|
||||
}
|
||||
return (maxsize);
|
||||
}
|
||||
|
||||
static void sdram_start (int hi_addr)
|
||||
{
|
||||
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
|
||||
|
||||
/* unlock mode register */
|
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000 | hi_addr_bit;
|
||||
/* precharge all banks */
|
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
|
||||
/* set mode register */
|
||||
#if defined(CONFIG_MPC5200)
|
||||
*(vu_long *)MPC5XXX_SDRAM_MODE = 0x408d0000;
|
||||
#elif defined(CONFIG_MGT5100)
|
||||
*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
|
||||
#endif
|
||||
/* precharge all banks */
|
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002 | hi_addr_bit;
|
||||
/* auto refresh */
|
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004 | hi_addr_bit;
|
||||
/* set mode register */
|
||||
*(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000;
|
||||
/* normal operation */
|
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit;
|
||||
}
|
||||
#endif
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
ulong dramsize = 0;
|
||||
#ifndef CFG_RAMBOOT
|
||||
ulong test1, test2;
|
||||
|
||||
/* configure SDRAM start/end */
|
||||
#if defined(CONFIG_MPC5200)
|
||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
|
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
|
||||
|
||||
/* setup config registers */
|
||||
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2233a00;
|
||||
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
|
||||
|
||||
#elif defined(CONFIG_MGT5100)
|
||||
*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
|
||||
*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
|
||||
*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
|
||||
|
||||
/* setup config registers */
|
||||
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2222600;
|
||||
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004;
|
||||
|
||||
/* address select register */
|
||||
*(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
|
||||
#endif
|
||||
sdram_start(0);
|
||||
test1 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
|
||||
sdram_start(1);
|
||||
test2 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
|
||||
if (test1 > test2) {
|
||||
sdram_start(0);
|
||||
dramsize = test1;
|
||||
} else {
|
||||
dramsize = test2;
|
||||
}
|
||||
#if defined(CONFIG_MPC5200)
|
||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG =
|
||||
(0x13 + __builtin_ffs(dramsize >> 20) - 1);
|
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
|
||||
#elif defined(CONFIG_MGT5100)
|
||||
*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
|
||||
#endif
|
||||
|
||||
#else
|
||||
#ifdef CONFIG_MGT5100
|
||||
*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
|
||||
dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
|
||||
#else
|
||||
dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
|
||||
#endif
|
||||
#endif /* CFG_RAMBOOT */
|
||||
/* return total ram size */
|
||||
return dramsize;
|
||||
}
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
#if defined(CONFIG_MPC5200)
|
||||
puts ("Board: MicroSys PM520 \n");
|
||||
#elif defined(CONFIG_MGT5100)
|
||||
puts ("Board: MicroSys PM510 \n");
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
void flash_preinit(void)
|
||||
{
|
||||
/*
|
||||
* Now, when we are in RAM, enable flash write
|
||||
* access for detection process.
|
||||
* Note that CS_BOOT cannot be cleared when
|
||||
* executing in flash.
|
||||
*/
|
||||
#if defined(CONFIG_MGT5100)
|
||||
*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
|
||||
*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
|
||||
#endif
|
||||
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
|
||||
}
|
||||
|
||||
void flash_afterinit(ulong size)
|
||||
{
|
||||
if (size == 0x800000) { /* adjust mapping */
|
||||
*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
|
||||
START_REG(CFG_BOOTCS_START | size);
|
||||
*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
|
||||
STOP_REG(CFG_BOOTCS_START | size, size);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static struct pci_controller hose;
|
||||
|
||||
extern void pci_mpc5xxx_init(struct pci_controller *);
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
pci_mpc5xxx_init(&hose);
|
||||
}
|
||||
#endif
|
122
board/pm520/u-boot.lds
Normal file
122
board/pm520/u-boot.lds
Normal file
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* (C) Copyright 2003-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
cpu/mpc5xxx/start.o (.text)
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
. = ALIGN(16);
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# (C) Copyright 2001, 2002
|
||||
# (C) Copyright 2001-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
|
@ -22,21 +22,16 @@
|
|||
#
|
||||
|
||||
#
|
||||
# PM826 boards
|
||||
# MicroSys PM826 board:
|
||||
#
|
||||
|
||||
# This should be equal to the CFG_FLASH_BASE or
|
||||
# CFG_BOOTROM_BASE define in config_PM826.h
|
||||
# for the "final" configuration, with U-Boot
|
||||
# in flash, or the address in RAM where
|
||||
# U-Boot is loaded at for debugging.
|
||||
#
|
||||
|
||||
ifeq ($(CONFIG_BOOT_ROM),y)
|
||||
TEXT_BASE := 0xFF800000
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM
|
||||
else
|
||||
TEXT_BASE := 0xFF000000
|
||||
sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
|
||||
|
||||
ifndef TEXT_BASE
|
||||
## Standard: boot 64-bit flash
|
||||
TEXT_BASE = 0xFF000000
|
||||
|
||||
endif
|
||||
|
||||
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
|
||||
|
|
|
@ -69,6 +69,11 @@ ulong flash_get_size (volatile unsigned long *baseaddr,
|
|||
info->sector_count = 39;
|
||||
info->size = 0x00800000; /* 4 * 2 MB = 8 MB */
|
||||
break;
|
||||
case INTEL_ID_28F640C3B:
|
||||
info->flash_id = FLASH_28F640C3B;
|
||||
info->sector_count = 135;
|
||||
info->size = 0x02000000; /* 16 * 2 MB = 32 MB */
|
||||
break;
|
||||
default:
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
@ -79,10 +84,11 @@ ulong flash_get_size (volatile unsigned long *baseaddr,
|
|||
volatile unsigned long *tmp = baseaddr;
|
||||
|
||||
/* set up sector start adress table (bottom sector type)
|
||||
* AND unlock the sectors (if our chip is 160C3)
|
||||
* AND unlock the sectors (if our chip is 160C3 or 640C3)
|
||||
*/
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) {
|
||||
if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) {
|
||||
tmp[0] = 0x00600060;
|
||||
tmp[1] = 0x00600060;
|
||||
tmp[0] = 0x00D000D0;
|
||||
|
@ -177,6 +183,9 @@ void flash_print_info (flash_info_t * info)
|
|||
case FLASH_28F160F3B:
|
||||
printf ("28F160F3B (16 M, bottom sector)\n");
|
||||
break;
|
||||
case FLASH_28F640C3B:
|
||||
printf ("28F640C3B (64 M, bottom sector)\n");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
|
|
40
board/pm828/Makefile
Normal file
40
board/pm828/Makefile
Normal file
|
@ -0,0 +1,40 @@
|
|||
#
|
||||
# (C) Copyright 2001-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS = $(BOARD).o flash.o
|
||||
|
||||
$(LIB): .depend $(OBJS)
|
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
|
||||
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend
|
||||
|
||||
#########################################################################
|
37
board/pm828/config.mk
Normal file
37
board/pm828/config.mk
Normal file
|
@ -0,0 +1,37 @@
|
|||
#
|
||||
# (C) Copyright 2003-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# MicroSys PM828 board:
|
||||
#
|
||||
|
||||
|
||||
sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
|
||||
|
||||
ifndef TEXT_BASE
|
||||
## Standard: boot 64-bit flash
|
||||
TEXT_BASE = 0x40000000
|
||||
|
||||
endif
|
||||
|
||||
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
|
386
board/pm828/flash.c
Normal file
386
board/pm828/flash.c
Normal file
|
@ -0,0 +1,386 @@
|
|||
/*
|
||||
* (C) Copyright 2001-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Flash Routines for Intel devices
|
||||
*
|
||||
*--------------------------------------------------------------------
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc8xx.h>
|
||||
|
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
ulong flash_get_size (volatile unsigned long *baseaddr,
|
||||
flash_info_t * info)
|
||||
{
|
||||
short i;
|
||||
unsigned long flashtest_h, flashtest_l;
|
||||
|
||||
info->sector_count = info->size = 0;
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
|
||||
/* Write query command sequence and test FLASH answer
|
||||
*/
|
||||
baseaddr[0] = 0x00980098;
|
||||
baseaddr[1] = 0x00980098;
|
||||
|
||||
flashtest_h = baseaddr[0]; /* manufacturer ID */
|
||||
flashtest_l = baseaddr[1];
|
||||
|
||||
if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
|
||||
return (0); /* no or unknown flash */
|
||||
|
||||
flashtest_h = baseaddr[2]; /* device ID */
|
||||
flashtest_l = baseaddr[3];
|
||||
|
||||
if (flashtest_h != flashtest_l)
|
||||
return (0);
|
||||
|
||||
switch (flashtest_h) {
|
||||
case INTEL_ID_28F160C3B:
|
||||
info->flash_id = FLASH_28F160C3B;
|
||||
info->sector_count = 39;
|
||||
info->size = 0x00800000; /* 4 * 2 MB = 8 MB */
|
||||
break;
|
||||
case INTEL_ID_28F160F3B:
|
||||
info->flash_id = FLASH_28F160F3B;
|
||||
info->sector_count = 39;
|
||||
info->size = 0x00800000; /* 4 * 2 MB = 8 MB */
|
||||
break;
|
||||
case INTEL_ID_28F640C3B:
|
||||
info->flash_id = FLASH_28F640C3B;
|
||||
info->sector_count = 135;
|
||||
info->size = 0x02000000; /* 16 * 2 MB = 32 MB */
|
||||
break;
|
||||
default:
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
|
||||
|
||||
if (info->flash_id & FLASH_BTYPE) {
|
||||
volatile unsigned long *tmp = baseaddr;
|
||||
|
||||
/* set up sector start adress table (bottom sector type)
|
||||
* AND unlock the sectors (if our chip is 160C3 or 640c3)
|
||||
*/
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) ||
|
||||
((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) {
|
||||
tmp[0] = 0x00600060;
|
||||
tmp[1] = 0x00600060;
|
||||
tmp[0] = 0x00D000D0;
|
||||
tmp[1] = 0x00D000D0;
|
||||
}
|
||||
info->start[i] = (uint) tmp;
|
||||
tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith */
|
||||
}
|
||||
}
|
||||
|
||||
memset (info->protect, 0, info->sector_count);
|
||||
|
||||
baseaddr[0] = 0x00FF00FF;
|
||||
baseaddr[1] = 0x00FF00FF;
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0 = 0;
|
||||
int i;
|
||||
|
||||
/* Init: no FLASHes known
|
||||
*/
|
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* Static FLASH Bank configuration here (only one bank) */
|
||||
|
||||
size_b0 = flash_get_size ((ulong *) CFG_FLASH0_BASE, &flash_info[0]);
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b0, size_b0 >> 20);
|
||||
}
|
||||
|
||||
/* protect monitor and environment sectors
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_BOOT_ROM
|
||||
/* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH0_BASE
|
||||
* but we shouldn't protect it.
|
||||
*/
|
||||
|
||||
# if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CFG_MONITOR_BASE,
|
||||
CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
|
||||
);
|
||||
# endif
|
||||
#endif /* CONFIG_BOOT_ROM */
|
||||
|
||||
#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
|
||||
# ifndef CFG_ENV_SIZE
|
||||
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
|
||||
# endif
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR,
|
||||
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
|
||||
#endif
|
||||
|
||||
return (size_b0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info (flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch ((info->flash_id >> 16) & 0xff) {
|
||||
case 0x89:
|
||||
printf ("INTEL ");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_28F160C3B:
|
||||
printf ("28F160C3B (16 M, bottom sector)\n");
|
||||
break;
|
||||
case FLASH_28F160F3B:
|
||||
printf ("28F160F3B (16 M, bottom sector)\n");
|
||||
break;
|
||||
case FLASH_28F640C3B:
|
||||
printf ("28F640C3B (64 M, bottom sector)\n");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; ++i) {
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
printf (" %08lX%s",
|
||||
info->start[i],
|
||||
info->protect[i] ? " (RO)" : " "
|
||||
);
|
||||
}
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
int flag, prot, sect;
|
||||
ulong start, now, last;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect])
|
||||
prot++;
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
/* Start erase on unprotected sectors
|
||||
*/
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
volatile ulong *addr =
|
||||
(volatile unsigned long *) info->start[sect];
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
if (info->protect[sect] == 0) {
|
||||
/* Disable interrupts which might cause a timeout here
|
||||
*/
|
||||
flag = disable_interrupts ();
|
||||
|
||||
/* Erase the block
|
||||
*/
|
||||
addr[0] = 0x00200020;
|
||||
addr[1] = 0x00200020;
|
||||
addr[0] = 0x00D000D0;
|
||||
addr[1] = 0x00D000D0;
|
||||
|
||||
/* re-enable interrupts if necessary
|
||||
*/
|
||||
if (flag)
|
||||
enable_interrupts ();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms
|
||||
*/
|
||||
udelay (1000);
|
||||
|
||||
last = start;
|
||||
while ((addr[0] & 0x00800080) != 0x00800080 ||
|
||||
(addr[1] & 0x00800080) != 0x00800080) {
|
||||
if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout (erase suspended!)\n");
|
||||
/* Suspend erase
|
||||
*/
|
||||
addr[0] = 0x00B000B0;
|
||||
addr[1] = 0x00B000B0;
|
||||
goto DONE;
|
||||
}
|
||||
/* show that we're waiting
|
||||
*/
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
serial_putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
|
||||
printf ("*** ERROR: erase failed!\n");
|
||||
goto DONE;
|
||||
}
|
||||
}
|
||||
/* Clear status register and reset to read mode
|
||||
*/
|
||||
addr[0] = 0x00500050;
|
||||
addr[1] = 0x00500050;
|
||||
addr[0] = 0x00FF00FF;
|
||||
addr[1] = 0x00FF00FF;
|
||||
}
|
||||
|
||||
printf (" done\n");
|
||||
|
||||
DONE:
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int write_word (flash_info_t *, volatile unsigned long *, ulong);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong v;
|
||||
int i, l, cc = cnt, res = 0;
|
||||
|
||||
|
||||
for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
|
||||
l = (addr & 3);
|
||||
addr &= ~3;
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
v = (v << 8) + (i < l || i - l >= cc ?
|
||||
*((unsigned char *) addr + i) : *src++);
|
||||
}
|
||||
|
||||
if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
|
||||
break;
|
||||
}
|
||||
|
||||
return (res);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word (flash_info_t * info, volatile unsigned long *addr,
|
||||
ulong data)
|
||||
{
|
||||
int flag, res = 0;
|
||||
ulong start;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased
|
||||
*/
|
||||
if ((*addr & data) != data)
|
||||
return (2);
|
||||
|
||||
/* Disable interrupts which might cause a timeout here
|
||||
*/
|
||||
flag = disable_interrupts ();
|
||||
|
||||
*addr = 0x00400040;
|
||||
*addr = data;
|
||||
|
||||
/* re-enable interrupts if necessary
|
||||
*/
|
||||
if (flag)
|
||||
enable_interrupts ();
|
||||
|
||||
start = get_timer (0);
|
||||
while ((*addr & 0x00800080) != 0x00800080) {
|
||||
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
|
||||
/* Suspend program
|
||||
*/
|
||||
*addr = 0x00B000B0;
|
||||
res = 1;
|
||||
goto OUT;
|
||||
}
|
||||
}
|
||||
|
||||
if (*addr & 0x00220022) {
|
||||
printf ("*** ERROR: program failed!\n");
|
||||
res = 1;
|
||||
}
|
||||
|
||||
OUT:
|
||||
/* Clear status register and reset to read mode
|
||||
*/
|
||||
*addr = 0x00500050;
|
||||
*addr = 0x00FF00FF;
|
||||
|
||||
return (res);
|
||||
}
|
363
board/pm828/pm828.c
Normal file
363
board/pm828/pm828.c
Normal file
|
@ -0,0 +1,363 @@
|
|||
/*
|
||||
* (C) Copyright 2001-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ioports.h>
|
||||
#include <mpc8260.h>
|
||||
#include <pci.h>
|
||||
|
||||
/*
|
||||
* I/O Port configuration table
|
||||
*
|
||||
* if conf is 1, then that port pin will be configured at boot time
|
||||
* according to the five values podr/pdir/ppar/psor/pdat for that entry
|
||||
*/
|
||||
|
||||
const iop_conf_t iop_conf_tab[4][32] = {
|
||||
|
||||
/* Port A configuration */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
|
||||
/* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
|
||||
/* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
|
||||
/* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
|
||||
/* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
|
||||
/* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
|
||||
/* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* PA25 */
|
||||
/* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
|
||||
/* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
|
||||
/* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* PA22 */
|
||||
/* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
|
||||
/* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
|
||||
/* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
|
||||
/* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
|
||||
/* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
|
||||
/* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1*/
|
||||
/* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
|
||||
/* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
|
||||
/* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* PA13 */
|
||||
/* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* PA12 */
|
||||
/* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* PA11 */
|
||||
/* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* PA10 */
|
||||
/* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* PA9 */
|
||||
/* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* PA8 */
|
||||
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
|
||||
/* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
|
||||
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
|
||||
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
|
||||
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
|
||||
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
|
||||
/* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
|
||||
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
|
||||
},
|
||||
|
||||
/* Port B configuration */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TX_ER */
|
||||
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_DV */
|
||||
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 TX_EN */
|
||||
#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
|
||||
#ifdef CONFIG_ETHER_ON_FCC2
|
||||
#error "SCC1 conflicts with FCC2"
|
||||
#endif
|
||||
/* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
|
||||
#else
|
||||
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RX_ER */
|
||||
#endif
|
||||
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 COL */
|
||||
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 CRS */
|
||||
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[3] */
|
||||
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[2] */
|
||||
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[1] */
|
||||
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 TxD[0] */
|
||||
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[0] */
|
||||
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[1] */
|
||||
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[2] */
|
||||
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RxD[3] */
|
||||
/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
|
||||
/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
|
||||
/* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
|
||||
/* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */
|
||||
/* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
|
||||
/* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
|
||||
/* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
|
||||
/* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
|
||||
/* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
|
||||
/* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TXD */
|
||||
/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
|
||||
/* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
|
||||
/* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
|
||||
/* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
|
||||
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
||||
},
|
||||
|
||||
/* Port C */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
|
||||
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
|
||||
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 CTS */
|
||||
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 CTS */
|
||||
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
|
||||
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
|
||||
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
|
||||
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
|
||||
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */
|
||||
/* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */
|
||||
/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */
|
||||
/* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK(2) */
|
||||
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RXCK */
|
||||
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 TXCK */
|
||||
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
|
||||
/* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
|
||||
/* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
|
||||
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 DCD */
|
||||
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
|
||||
/* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 DCD */
|
||||
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 CTS */
|
||||
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 DCD */
|
||||
/* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 CTS */
|
||||
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 DCD */
|
||||
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
|
||||
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
|
||||
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
|
||||
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
|
||||
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
|
||||
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* PC2 */
|
||||
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* PC1 */
|
||||
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* PC0 */
|
||||
},
|
||||
|
||||
/* Port D */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
|
||||
/* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* PD30 */
|
||||
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 RTS */
|
||||
/* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
|
||||
/* PD27 */ { 0, 1, 0, 1, 0, 0 }, /* SCC2 RTS */
|
||||
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
|
||||
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
|
||||
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
|
||||
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 RTS */
|
||||
/* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RXD */
|
||||
/* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4 TXD */
|
||||
/* PD20 */ { 0, 0, 1, 1, 0, 0 }, /* SCC4 RTS */
|
||||
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
|
||||
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
|
||||
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */
|
||||
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */
|
||||
#if defined(CONFIG_SOFT_I2C)
|
||||
/* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
|
||||
/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
|
||||
#else
|
||||
#if defined(CONFIG_HARD_I2C)
|
||||
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
|
||||
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
|
||||
#else /* normal I/O port pins */
|
||||
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
|
||||
/* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
|
||||
#endif
|
||||
#endif
|
||||
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
|
||||
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
|
||||
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
|
||||
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
|
||||
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* PD9 */
|
||||
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* PD8 */
|
||||
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
|
||||
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
|
||||
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
|
||||
/* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* SMC2 RXD */
|
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
|
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
||||
}
|
||||
};
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/* Check Board Identity:
|
||||
*/
|
||||
int checkboard (void)
|
||||
{
|
||||
puts ("Board: PM828\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
|
||||
*
|
||||
* This routine performs standard 8260 initialization sequence
|
||||
* and calculates the available memory size. It may be called
|
||||
* several times to try different SDRAM configurations on both
|
||||
* 60x and local buses.
|
||||
*/
|
||||
static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
|
||||
ulong orx, volatile uchar * base)
|
||||
{
|
||||
volatile uchar c = 0xff;
|
||||
volatile ulong cnt, val;
|
||||
volatile ulong *addr;
|
||||
volatile uint *sdmr_ptr;
|
||||
volatile uint *orx_ptr;
|
||||
int i;
|
||||
ulong save[32]; /* to make test non-destructive */
|
||||
ulong maxsize;
|
||||
|
||||
/* We must be able to test a location outsize the maximum legal size
|
||||
* to find out THAT we are outside; but this address still has to be
|
||||
* mapped by the controller. That means, that the initial mapping has
|
||||
* to be (at least) twice as large as the maximum expected size.
|
||||
*/
|
||||
maxsize = (1 + (~orx | 0x7fff)) / 2;
|
||||
|
||||
sdmr_ptr = &memctl->memc_psdmr;
|
||||
orx_ptr = &memctl->memc_or2;
|
||||
|
||||
*orx_ptr = orx;
|
||||
|
||||
/*
|
||||
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
|
||||
*
|
||||
* "At system reset, initialization software must set up the
|
||||
* programmable parameters in the memory controller banks registers
|
||||
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
|
||||
* system software should execute the following initialization sequence
|
||||
* for each SDRAM device.
|
||||
*
|
||||
* 1. Issue a PRECHARGE-ALL-BANKS command
|
||||
* 2. Issue eight CBR REFRESH commands
|
||||
* 3. Issue a MODE-SET command to initialize the mode register
|
||||
*
|
||||
* The initial commands are executed by setting P/LSDMR[OP] and
|
||||
* accessing the SDRAM with a single-byte transaction."
|
||||
*
|
||||
* The appropriate BRx/ORx registers have already been set when we
|
||||
* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
|
||||
*/
|
||||
|
||||
*sdmr_ptr = sdmr | PSDMR_OP_PREA;
|
||||
*base = c;
|
||||
|
||||
*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
|
||||
for (i = 0; i < 8; i++)
|
||||
*base = c;
|
||||
|
||||
*sdmr_ptr = sdmr | PSDMR_OP_MRW;
|
||||
*(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
|
||||
|
||||
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
||||
*base = c;
|
||||
|
||||
/*
|
||||
* Check memory range for valid RAM. A simple memory test determines
|
||||
* the actually available RAM size between addresses `base' and
|
||||
* `base + maxsize'. Some (not all) hardware errors are detected:
|
||||
* - short between address lines
|
||||
* - short between data lines
|
||||
*/
|
||||
i = 0;
|
||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
||||
addr = (volatile ulong *) base + cnt; /* pointer arith! */
|
||||
save[i++] = *addr;
|
||||
*addr = ~cnt;
|
||||
}
|
||||
|
||||
addr = (volatile ulong *) base;
|
||||
save[i] = *addr;
|
||||
*addr = 0;
|
||||
|
||||
if ((val = *addr) != 0) {
|
||||
*addr = save[i];
|
||||
return (0);
|
||||
}
|
||||
|
||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
||||
addr = (volatile ulong *) base + cnt; /* pointer arith! */
|
||||
val = *addr;
|
||||
*addr = save[--i];
|
||||
if (val != ~cnt) {
|
||||
/* Write the actual size to ORx
|
||||
*/
|
||||
*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
|
||||
return (cnt * sizeof (long));
|
||||
}
|
||||
}
|
||||
return (maxsize);
|
||||
}
|
||||
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||
volatile memctl8260_t *memctl = &immap->im_memctl;
|
||||
|
||||
#ifndef CFG_RAMBOOT
|
||||
ulong size8, size9;
|
||||
#endif
|
||||
ulong psize = 32 * 1024 * 1024;
|
||||
|
||||
memctl->memc_psrt = CFG_PSRT;
|
||||
memctl->memc_mptpr = CFG_MPTPR;
|
||||
|
||||
#ifndef CFG_RAMBOOT
|
||||
size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
|
||||
(uchar *) CFG_SDRAM_BASE);
|
||||
size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
|
||||
(uchar *) CFG_SDRAM_BASE);
|
||||
|
||||
if (size8 < size9) {
|
||||
psize = size9;
|
||||
printf ("(60x:9COL) ");
|
||||
} else {
|
||||
psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
|
||||
(uchar *) CFG_SDRAM_BASE);
|
||||
printf ("(60x:8COL) ");
|
||||
}
|
||||
#endif
|
||||
return (psize);
|
||||
}
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
|
||||
extern void doc_probe (ulong physadr);
|
||||
void doc_init (void)
|
||||
{
|
||||
doc_probe (CFG_DOC_BASE);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
struct pci_controller hose;
|
||||
|
||||
extern void pci_mpc8250_init(struct pci_controller *);
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
pci_mpc8250_init(&hose);
|
||||
}
|
||||
#endif
|
123
board/pm828/u-boot.lds
Normal file
123
board/pm828/u-boot.lds
Normal file
|
@ -0,0 +1,123 @@
|
|||
/*
|
||||
* (C) Copyright 2001-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
cpu/mpc8260/start.o (.text)
|
||||
*(.text)
|
||||
common/environment.o(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
. = ALIGN(16);
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
|
@ -118,30 +118,21 @@ platformsetup:
|
|||
str r1, [r0] /* EMIFS GlB Configuration. (value 0x12 most likely) */
|
||||
|
||||
ldr r0, _GPIO_PIN_CONTROL_REG
|
||||
ldrh r1,[r0]
|
||||
mov r1,#0
|
||||
orr r1, r1, #0x0001 /* M_PCM_SYNC */
|
||||
orr r1, r1, #0x4000 /* IPC_ACTIVE */
|
||||
orr r1, r1, #0x0002 /* A_IRDA_OFF */
|
||||
orr r1, r1, #0x0800 /* A_SWITCH */
|
||||
orr r1, r1, #0x8000 /* A_USB_ON */
|
||||
strh r1,[r0]
|
||||
|
||||
ldr r0, _GPIO_DIR_CONTROL_REG
|
||||
ldrh r1,[r0]
|
||||
mov r1,#0
|
||||
bic r1, r1, #0x0001 /* M_PCM_SYNC */
|
||||
bic r1, r1, #0x4000 /* IPC_ACTIVE */
|
||||
bic r1, r1, #0x0002 /* A_IRDA_OFF */
|
||||
bic r1, r1, #0x0800 /* A_SWITCH */
|
||||
bic r1, r1, #0x8000 /* A_USB_ON */
|
||||
strh r1,[r0]
|
||||
|
||||
ldr r0, _GPIO_DATA_OUTPUT_REG
|
||||
ldrh r1,[r0]
|
||||
mov r1,#0
|
||||
bic r1, r1, #0x0001 /* M_PCM_SYNC */
|
||||
orr r1, r1, #0x4000 /* IPC_ACTIVE */
|
||||
orr r1, r1, #0x0002 /* A_IRDA_OFF */
|
||||
bic r1, r1, #0x0800 /* A_SWITCH */
|
||||
bic r1, r1, #0x8000 /* A_USB_ON */
|
||||
strh r1,[r0]
|
||||
|
||||
/* Setup some clock domains */
|
||||
|
|
|
@ -83,6 +83,7 @@ ulong flash_init (void)
|
|||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case (FLASH_AM320B & FLASH_TYPEMASK):
|
||||
case (FLASH_MXLV320B & FLASH_TYPEMASK):
|
||||
/* Boot sector type: 8 x 8 + N x 128 kB */
|
||||
flashbase += (j < 8) ? 0x4000 : 0x20000;
|
||||
break;
|
||||
|
@ -130,6 +131,8 @@ void flash_print_info (flash_info_t * info)
|
|||
printf ("AMD "); break;
|
||||
case (FLASH_MAN_FUJ & FLASH_VENDMASK):
|
||||
printf ("FUJITSU "); break;
|
||||
case (FLASH_MAN_MX & FLASH_VENDMASK):
|
||||
printf ("MACRONIX "); break;
|
||||
default: printf ("Unknown Vendor "); break;
|
||||
}
|
||||
|
||||
|
@ -137,6 +140,9 @@ void flash_print_info (flash_info_t * info)
|
|||
case (FLASH_AM320B & FLASH_TYPEMASK):
|
||||
printf ("2x Am29LV320DB (32Mbit)\n");
|
||||
break;
|
||||
case (FLASH_MXLV320B & FLASH_TYPEMASK):
|
||||
printf ("2x MX29LV320DB (32Mbit)\n");
|
||||
break;
|
||||
case (FLASH_AM640U & FLASH_TYPEMASK):
|
||||
printf ("2x Am29LV640D (64Mbit)\n");
|
||||
break;
|
||||
|
@ -191,6 +197,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
|
|||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case (FLASH_MAN_AMD & FLASH_VENDMASK): break; /* OK */
|
||||
case (FLASH_MAN_FUJ & FLASH_VENDMASK): break; /* OK */
|
||||
case (FLASH_MAN_MX & FLASH_VENDMASK): break; /* OK */
|
||||
default:
|
||||
debug ("## flash_erase: unknown manufacturer\n");
|
||||
return (ERR_UNKNOWN_FLASH_VENDOR);
|
||||
|
@ -502,6 +509,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
|
|||
case FUJ_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_FUJ;
|
||||
break;
|
||||
case MX_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_MX;
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
|
@ -532,6 +542,14 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
|
|||
addr[0] = 0x00F000F0; /* restore read mode */
|
||||
break; /* => 16 MB */
|
||||
|
||||
case MX_ID_LV320B:
|
||||
info->flash_id += FLASH_MXLV320B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00800000;
|
||||
|
||||
addr[0] = 0x00FF00FF; /* restore read mode */
|
||||
break; /* => 8 MB */
|
||||
|
||||
default:
|
||||
debug ("## flash_init: unknown flash chip\n");
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
|
|
47
board/xm250/Makefile
Normal file
47
board/xm250/Makefile
Normal file
|
@ -0,0 +1,47 @@
|
|||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS := xm250.o flash.o
|
||||
SOBJS := memsetup.o
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(AR) crv $@ $^
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
|
||||
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
-include .depend
|
||||
|
||||
#########################################################################
|
35
board/xm250/config.mk
Normal file
35
board/xm250/config.mk
Normal file
|
@ -0,0 +1,35 @@
|
|||
#
|
||||
# (C) Copyright 2003-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# MicroSys XM250 board:
|
||||
#
|
||||
|
||||
|
||||
# This is the address where U-Boot lives in flash:
|
||||
#TEXT_BASE = 0
|
||||
|
||||
# FIXME: armboot does only work correctly when being compiled
|
||||
# for the addresses _after_ relocation to RAM!! Otherwhise the
|
||||
# .bss segment is assumed in flash...
|
||||
TEXT_BASE = 0xA3F80000
|
536
board/xm250/flash.c
Normal file
536
board/xm250/flash.c
Normal file
|
@ -0,0 +1,536 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
|
||||
*
|
||||
* (C) Copyright 2001-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/byteorder/swab.h>
|
||||
|
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/* Board support for 1 or 2 flash devices */
|
||||
#define FLASH_PORT_WIDTH32
|
||||
#undef FLASH_PORT_WIDTH16
|
||||
|
||||
#ifdef FLASH_PORT_WIDTH16
|
||||
#define FLASH_PORT_WIDTH ushort
|
||||
#define FLASH_PORT_WIDTHV vu_short
|
||||
#define SWAP(x) __swab16(x)
|
||||
#else
|
||||
#define FLASH_PORT_WIDTH ulong
|
||||
#define FLASH_PORT_WIDTHV vu_long
|
||||
#define SWAP(x) __swab32(x)
|
||||
#endif
|
||||
|
||||
/* Intel-compatible flash ID */
|
||||
#define INTEL_COMPAT 0x00890089
|
||||
#define INTEL_ALT 0x00B000B0
|
||||
|
||||
/* Intel-compatible flash commands */
|
||||
#define INTEL_PROGRAM 0x00100010
|
||||
#define INTEL_ERASE 0x00200020
|
||||
#define INTEL_CLEAR 0x00500050
|
||||
#define INTEL_LOCKBIT 0x00600060
|
||||
#define INTEL_PROTECT 0x00010001
|
||||
#define INTEL_STATUS 0x00700070
|
||||
#define INTEL_READID 0x00900090
|
||||
#define INTEL_CONFIRM 0x00D000D0
|
||||
#define INTEL_RESET 0xFFFFFFFF
|
||||
|
||||
/* Intel-compatible flash status bits */
|
||||
#define INTEL_FINISHED 0x00800080
|
||||
#define INTEL_OK 0x00800080
|
||||
|
||||
#define FPW FLASH_PORT_WIDTH
|
||||
#define FPWV FLASH_PORT_WIDTHV
|
||||
|
||||
#define mb() __asm__ __volatile__ ("" : : : "memory")
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (FPW *addr, flash_info_t *info);
|
||||
static int write_data (flash_info_t *info, ulong dest, FPW data);
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info);
|
||||
void inline spin_wheel (void);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
int i;
|
||||
ulong size = 0;
|
||||
|
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
|
||||
flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
|
||||
break;
|
||||
case 1:
|
||||
flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
|
||||
flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
|
||||
break;
|
||||
default:
|
||||
panic ("configured to many flash banks!\n");
|
||||
break;
|
||||
}
|
||||
size += flash_info[i].size;
|
||||
}
|
||||
|
||||
/* Protect monitor and environment sectors
|
||||
*/
|
||||
flash_protect ( FLAG_PROTECT_SET,
|
||||
CFG_FLASH_BASE,
|
||||
CFG_FLASH_BASE + monitor_flash_len - 1,
|
||||
&flash_info[0] );
|
||||
|
||||
flash_protect ( FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR,
|
||||
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
return;
|
||||
}
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
|
||||
info->protect[i] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info (flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_INTEL:
|
||||
printf ("INTEL ");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_28F128J3A:
|
||||
printf ("28F128J3A\n");
|
||||
break;
|
||||
|
||||
case FLASH_28F640J3A:
|
||||
printf ("28F640J3A\n");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; ++i) {
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
printf (" %08lX%s",
|
||||
info->start[i],
|
||||
info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
printf ("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
static ulong flash_get_size (FPW *addr, flash_info_t *info)
|
||||
{
|
||||
volatile FPW value;
|
||||
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
addr[0x5555] = (FPW) 0x00AA00AA;
|
||||
addr[0x2AAA] = (FPW) 0x00550055;
|
||||
addr[0x5555] = (FPW) 0x00900090;
|
||||
|
||||
mb ();
|
||||
value = addr[0];
|
||||
|
||||
switch (value) {
|
||||
|
||||
case (FPW) INTEL_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_INTEL;
|
||||
break;
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
mb ();
|
||||
value = addr[1]; /* device ID */
|
||||
|
||||
switch (value) {
|
||||
|
||||
case (FPW) INTEL_ID_28F128J3A:
|
||||
info->flash_id += FLASH_28F128J3A;
|
||||
info->sector_count = 128;
|
||||
info->size = 0x02000000;
|
||||
break; /* => 32 MB */
|
||||
|
||||
case (FPW) INTEL_ID_28F640J3A:
|
||||
info->flash_id += FLASH_28F640J3A;
|
||||
info->sector_count = 64;
|
||||
info->size = 0x01000000;
|
||||
break; /* => 16 MB */
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
break;
|
||||
}
|
||||
|
||||
if (info->sector_count > CFG_MAX_FLASH_SECT) {
|
||||
printf ("** ERROR: sector count %d > max (%d) **\n",
|
||||
info->sector_count, CFG_MAX_FLASH_SECT);
|
||||
info->sector_count = CFG_MAX_FLASH_SECT;
|
||||
}
|
||||
|
||||
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
int flag, prot, sect;
|
||||
ulong type, start, last;
|
||||
int rcode = 0;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
type = (info->flash_id & FLASH_VENDMASK);
|
||||
if ((type != FLASH_MAN_INTEL)) {
|
||||
printf ("Can't erase unknown flash type %08lx - aborted\n",
|
||||
info->flash_id);
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
FPWV *addr = (FPWV *) (info->start[sect]);
|
||||
FPW status;
|
||||
|
||||
printf ("Erasing sector %2d ... ", sect);
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
reset_timer_masked ();
|
||||
|
||||
*addr = (FPW) 0x00500050; /* clear status register */
|
||||
*addr = (FPW) 0x00200020; /* erase setup */
|
||||
*addr = (FPW) 0x00D000D0; /* erase confirm */
|
||||
|
||||
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
|
||||
if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
*addr = (FPW) 0x00B000B0; /* suspend erase */
|
||||
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
|
||||
rcode = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
*addr = 0x00500050; /* clear status register cmd. */
|
||||
*addr = 0x00FF00FF; /* resest to read mode */
|
||||
|
||||
printf (" done\n");
|
||||
}
|
||||
}
|
||||
return rcode;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
* 4 - Flash not identified
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp;
|
||||
FPW data;
|
||||
int count, i, l, rc, port_width;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
return 4;
|
||||
}
|
||||
/* get lower word aligned address */
|
||||
#ifdef FLASH_PORT_WIDTH16
|
||||
wp = (addr & ~1);
|
||||
port_width = 2;
|
||||
#else
|
||||
wp = (addr & ~3);
|
||||
port_width = 4;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
}
|
||||
for (; i < port_width && cnt > 0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt == 0 && i < port_width; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
}
|
||||
|
||||
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += port_width;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
count = 0;
|
||||
while (cnt >= port_width) {
|
||||
data = 0;
|
||||
for (i = 0; i < port_width; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_data (info, wp, SWAP (data))) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += port_width;
|
||||
cnt -= port_width;
|
||||
if (count++ > 0x800) {
|
||||
spin_wheel ();
|
||||
count = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i < port_width; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
}
|
||||
|
||||
return (write_data (info, wp, SWAP (data)));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word or halfword to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_data (flash_info_t *info, ulong dest, FPW data)
|
||||
{
|
||||
FPWV *addr = (FPWV *) dest;
|
||||
ulong status;
|
||||
int flag;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*addr & data) != data) {
|
||||
printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
|
||||
return (2);
|
||||
}
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
|
||||
*addr = (FPW) 0x00400040; /* write setup */
|
||||
*addr = data;
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
reset_timer_masked ();
|
||||
|
||||
/* wait while polling the status register */
|
||||
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
|
||||
if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
|
||||
*addr = (FPW) 0x00FF00FF; /* restore read mode */
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
|
||||
*addr = (FPW) 0x00FF00FF; /* restore read mode */
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
void inline spin_wheel (void)
|
||||
{
|
||||
static int p = 0;
|
||||
static char w[] = "\\/-";
|
||||
|
||||
printf ("\010%c", w[p]);
|
||||
(++p == 3) ? (p = 0) : 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Set/Clear sector's lock bit, returns:
|
||||
* 0 - OK
|
||||
* 1 - Error (timeout, voltage problems, etc.)
|
||||
*/
|
||||
int flash_real_protect(flash_info_t *info, long sector, int prot)
|
||||
{
|
||||
int i;
|
||||
int rc = 0;
|
||||
vu_long *addr = (vu_long *)(info->start[sector]);
|
||||
int flag = disable_interrupts();
|
||||
|
||||
*addr = INTEL_CLEAR; /* Clear status register */
|
||||
if (prot) { /* Set sector lock bit */
|
||||
*addr = INTEL_LOCKBIT; /* Sector lock bit */
|
||||
*addr = INTEL_PROTECT; /* set */
|
||||
}
|
||||
else { /* Clear sector lock bit */
|
||||
*addr = INTEL_LOCKBIT; /* All sectors lock bits */
|
||||
*addr = INTEL_CONFIRM; /* clear */
|
||||
}
|
||||
|
||||
reset_timer_masked ();
|
||||
|
||||
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
|
||||
if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) {
|
||||
printf("Flash lock bit operation timed out\n");
|
||||
rc = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (*addr != INTEL_OK) {
|
||||
printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
|
||||
(uint)addr, (uint)*addr);
|
||||
rc = 1;
|
||||
}
|
||||
|
||||
if (!rc)
|
||||
info->protect[sector] = prot;
|
||||
|
||||
/*
|
||||
* Clear lock bit command clears all sectors lock bits, so
|
||||
* we have to restore lock bits of protected sectors.
|
||||
*/
|
||||
if (!prot)
|
||||
{
|
||||
for (i = 0; i < info->sector_count; i++)
|
||||
{
|
||||
if (info->protect[i])
|
||||
{
|
||||
reset_timer_masked ();
|
||||
addr = (vu_long *)(info->start[i]);
|
||||
*addr = INTEL_LOCKBIT; /* Sector lock bit */
|
||||
*addr = INTEL_PROTECT; /* set */
|
||||
while ((*addr & INTEL_FINISHED) != INTEL_FINISHED)
|
||||
{
|
||||
if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT)
|
||||
{
|
||||
printf("Flash lock bit operation timed out\n");
|
||||
rc = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
*addr = INTEL_RESET; /* Reset to read array mode */
|
||||
|
||||
return rc;
|
||||
}
|
519
board/xm250/memsetup.S
Normal file
519
board/xm250/memsetup.S
Normal file
|
@ -0,0 +1,519 @@
|
|||
/*
|
||||
* Most of this taken from Redboot hal_platform_setup.h with cleanup
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
|
||||
DRAM_SIZE: .long CFG_DRAM_SIZE
|
||||
|
||||
/* wait for coprocessor write complete */
|
||||
.macro CPWAIT reg
|
||||
mrc p15,0,\reg,c2,c0,0
|
||||
mov \reg,\reg
|
||||
sub pc,pc,#4
|
||||
.endm
|
||||
/*
|
||||
.macro SET_LED val
|
||||
ldr r6, =CRADLE_LED_CLR_REG
|
||||
ldr r7, =0
|
||||
str r7, [r6]
|
||||
ldr r6, =CRADLE_LED_SET_REG
|
||||
ldr r7, =\val
|
||||
str r7, [r6]
|
||||
.endm
|
||||
*/
|
||||
|
||||
.globl memsetup
|
||||
memsetup:
|
||||
|
||||
mov r10, lr
|
||||
|
||||
/* Set up GPIO pins first */
|
||||
|
||||
ldr r0, =GPSR0
|
||||
ldr r1, =CFG_GPSR0_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GPSR1
|
||||
ldr r1, =CFG_GPSR1_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GPSR2
|
||||
ldr r1, =CFG_GPSR2_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GPCR0
|
||||
ldr r1, =CFG_GPCR0_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GPCR1
|
||||
ldr r1, =CFG_GPCR1_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GPCR2
|
||||
ldr r1, =CFG_GPCR2_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GRER0
|
||||
ldr r1, =CFG_GRER0_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GRER1
|
||||
ldr r1, =CFG_GRER1_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GRER2
|
||||
ldr r1, =CFG_GRER2_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GFER0
|
||||
ldr r1, =CFG_GFER0_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GFER1
|
||||
ldr r1, =CFG_GFER1_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GFER2
|
||||
ldr r1, =CFG_GFER2_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GPDR0
|
||||
ldr r1, =CFG_GPDR0_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GPDR1
|
||||
ldr r1, =CFG_GPDR1_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GPDR2
|
||||
ldr r1, =CFG_GPDR2_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GAFR0_L
|
||||
ldr r1, =CFG_GAFR0_L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GAFR0_U
|
||||
ldr r1, =CFG_GAFR0_U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GAFR1_L
|
||||
ldr r1, =CFG_GAFR1_L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GAFR1_U
|
||||
ldr r1, =CFG_GAFR1_U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GAFR2_L
|
||||
ldr r1, =CFG_GAFR2_L_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =GAFR2_U
|
||||
ldr r1, =CFG_GAFR2_U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* enable GPIO pins */
|
||||
ldr r0, =PSSR
|
||||
ldr r1, =CFG_PSSR_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* SET_LED 1 */
|
||||
|
||||
ldr r3, =MSC1 /* low - bank 2 Lubbock Registers / SRAM */
|
||||
ldr r2, =CFG_MSC1_VAL /* high - bank 3 Ethernet Controller */
|
||||
str r2, [r3] /* need to set MSC1 before trying to write to the HEX LEDs */
|
||||
ldr r2, [r3] /* need to read it back to make sure the value latches (see MSC section of manual) */
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* Initlialize Memory Controller
|
||||
*
|
||||
* See PXA250 Operating System Developer's Guide
|
||||
*
|
||||
* pause for 200 uSecs- allow internal clocks to settle
|
||||
* *Note: only need this if hard reset... doing it anyway for now
|
||||
*/
|
||||
|
||||
@ Step 1
|
||||
@ ---- Wait 200 usec
|
||||
ldr r3, =OSCR @ reset the OS Timer Count to zero
|
||||
mov r2, #0
|
||||
str r2, [r3]
|
||||
ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
|
||||
1:
|
||||
ldr r2, [r3]
|
||||
cmp r4, r2
|
||||
bgt 1b
|
||||
|
||||
/* SET_LED 2 */
|
||||
|
||||
mem_init:
|
||||
@ get memory controller base address
|
||||
ldr r1, =MEMC_BASE
|
||||
|
||||
|
||||
@****************************************************************************
|
||||
@ Step 2
|
||||
@
|
||||
|
||||
@ Step 2a
|
||||
@ write msc0, read back to ensure data latches
|
||||
@
|
||||
ldr r2, =CFG_MSC0_VAL
|
||||
str r2, [r1, #MSC0_OFFSET]
|
||||
ldr r2, [r1, #MSC0_OFFSET]
|
||||
|
||||
@ write msc1
|
||||
ldr r2, =CFG_MSC1_VAL
|
||||
str r2, [r1, #MSC1_OFFSET]
|
||||
ldr r2, [r1, #MSC1_OFFSET]
|
||||
|
||||
@ write msc2
|
||||
ldr r2, =CFG_MSC2_VAL
|
||||
str r2, [r1, #MSC2_OFFSET]
|
||||
ldr r2, [r1, #MSC2_OFFSET]
|
||||
|
||||
@ Step 2b
|
||||
@ write mecr
|
||||
ldr r2, =CFG_MECR_VAL
|
||||
str r2, [r1, #MECR_OFFSET]
|
||||
|
||||
@ write mcmem0
|
||||
ldr r2, =CFG_MCMEM0_VAL
|
||||
str r2, [r1, #MCMEM0_OFFSET]
|
||||
|
||||
@ write mcmem1
|
||||
ldr r2, =CFG_MCMEM1_VAL
|
||||
str r2, [r1, #MCMEM1_OFFSET]
|
||||
|
||||
@ write mcatt0
|
||||
ldr r2, =CFG_MCATT0_VAL
|
||||
str r2, [r1, #MCATT0_OFFSET]
|
||||
|
||||
@ write mcatt1
|
||||
ldr r2, =CFG_MCATT1_VAL
|
||||
str r2, [r1, #MCATT1_OFFSET]
|
||||
|
||||
@ write mcio0
|
||||
ldr r2, =CFG_MCIO0_VAL
|
||||
str r2, [r1, #MCIO0_OFFSET]
|
||||
|
||||
@ write mcio1
|
||||
ldr r2, =CFG_MCIO1_VAL
|
||||
str r2, [r1, #MCIO1_OFFSET]
|
||||
|
||||
/*SET_LED 3 */
|
||||
|
||||
@ Step 2c
|
||||
@ fly-by-dma is defeatured on this part
|
||||
@ write flycnfg
|
||||
@ldr r2, =CFG_FLYCNFG_VAL
|
||||
@str r2, [r1, #FLYCNFG_OFFSET]
|
||||
|
||||
/* FIXME Does this sequence really make sense */
|
||||
#ifdef REDBOOT_WAY
|
||||
@ Step 2d
|
||||
@ get the mdrefr settings
|
||||
ldr r3, =CFG_MDREFR_VAL
|
||||
|
||||
@ extract DRI field (we need a valid DRI field)
|
||||
@
|
||||
ldr r2, =0xFFF
|
||||
|
||||
@ valid DRI field in r3
|
||||
@
|
||||
and r3, r3, r2
|
||||
|
||||
@ get the reset state of MDREFR
|
||||
@
|
||||
ldr r4, [r1, #MDREFR_OFFSET]
|
||||
|
||||
@ clear the DRI field
|
||||
@
|
||||
bic r4, r4, r2
|
||||
|
||||
@ insert the valid DRI field loaded above
|
||||
@
|
||||
orr r4, r4, r3
|
||||
|
||||
@ write back mdrefr
|
||||
@
|
||||
str r4, [r1, #MDREFR_OFFSET]
|
||||
|
||||
@ *Note: preserve the mdrefr value in r4 *
|
||||
|
||||
/*SET_LED 4 */
|
||||
|
||||
@****************************************************************************
|
||||
@ Step 3
|
||||
@
|
||||
@ NO SRAM
|
||||
|
||||
mov pc, r10
|
||||
|
||||
|
||||
@****************************************************************************
|
||||
@ Step 4
|
||||
@
|
||||
|
||||
@ Assumes previous mdrefr value in r4, if not then read current mdrefr
|
||||
|
||||
@ clear the free-running clock bits
|
||||
@ (clear K0Free, K1Free, K2Free
|
||||
@
|
||||
bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
|
||||
|
||||
@ set K0RUN for CPLD clock
|
||||
@
|
||||
orr r4, r4, #0x00002000
|
||||
|
||||
@ set K1RUN if bank 0 installed
|
||||
@
|
||||
orr r4, r4, #0x00010000
|
||||
|
||||
@ write back mdrefr
|
||||
@
|
||||
str r4, [r1, #MDREFR_OFFSET]
|
||||
ldr r4, [r1, #MDREFR_OFFSET]
|
||||
|
||||
@ deassert SLFRSH
|
||||
@
|
||||
bic r4, r4, #0x00400000
|
||||
|
||||
@ write back mdrefr
|
||||
@
|
||||
str r4, [r1, #MDREFR_OFFSET]
|
||||
|
||||
@ assert E1PIN
|
||||
@
|
||||
orr r4, r4, #0x00008000
|
||||
|
||||
@ write back mdrefr
|
||||
@
|
||||
str r4, [r1, #MDREFR_OFFSET]
|
||||
ldr r4, [r1, #MDREFR_OFFSET]
|
||||
nop
|
||||
nop
|
||||
#else
|
||||
@ Step 2d
|
||||
@ get the mdrefr settings
|
||||
ldr r4, =CFG_MDREFR_VAL
|
||||
|
||||
@ write back mdrefr
|
||||
@
|
||||
str r4, [r1, #MDREFR_OFFSET]
|
||||
|
||||
@ Step 4
|
||||
|
||||
@ set K0RUN for FLASH clock
|
||||
@
|
||||
orr r4, r4, #0x00002000
|
||||
|
||||
@ set K1RUN for bank DRAM 0
|
||||
@
|
||||
orr r4, r4, #0x00010000
|
||||
|
||||
@ set K2RUN for bank PLD
|
||||
@
|
||||
orr r4, r4, #0x00040000
|
||||
|
||||
@ write back mdrefr
|
||||
@
|
||||
str r4, [r1, #MDREFR_OFFSET]
|
||||
ldr r4, [r1, #MDREFR_OFFSET]
|
||||
|
||||
@ deassert SLFRSH
|
||||
@
|
||||
bic r4, r4, #0x00400000
|
||||
|
||||
@ write back mdrefr
|
||||
@
|
||||
str r4, [r1, #MDREFR_OFFSET]
|
||||
|
||||
@ assert E1PIN
|
||||
@
|
||||
orr r4, r4, #0x00008000
|
||||
|
||||
@ write back mdrefr
|
||||
@
|
||||
str r4, [r1, #MDREFR_OFFSET]
|
||||
ldr r4, [r1, #MDREFR_OFFSET]
|
||||
nop
|
||||
nop
|
||||
#endif
|
||||
|
||||
@ Step 4d
|
||||
@ fetch platform value of mdcnfg
|
||||
@
|
||||
ldr r2, =CFG_MDCNFG_VAL
|
||||
|
||||
@ disable all sdram banks
|
||||
@
|
||||
bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
|
||||
bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
|
||||
|
||||
@ program banks 0/1 for bus width
|
||||
@
|
||||
bic r2, r2, #MDCNFG_DWID0 @0=32-bit
|
||||
|
||||
@ write initial value of mdcnfg, w/o enabling sdram banks
|
||||
@
|
||||
str r2, [r1, #MDCNFG_OFFSET]
|
||||
|
||||
@ Step 4e
|
||||
@ pause for 200 uSecs
|
||||
@
|
||||
ldr r3, =OSCR @ reset the OS Timer Count to zero
|
||||
mov r2, #0
|
||||
str r2, [r3]
|
||||
ldr r4, =0x300 @ really 0x2E1 is about 200usec, so 0x300 should be plenty
|
||||
1:
|
||||
ldr r2, [r3]
|
||||
cmp r4, r2
|
||||
bgt 1b
|
||||
|
||||
/*SET_LED 5 */
|
||||
|
||||
/* Why is this here??? */
|
||||
mov r0, #0x78 @turn everything off
|
||||
mcr p15, 0, r0, c1, c0, 0 @(caches off, MMU off, etc.)
|
||||
|
||||
@ Step 4f
|
||||
@ Access memory *not yet enabled* for CBR refresh cycles (8)
|
||||
@ - CBR is generated for all banks
|
||||
|
||||
ldr r2, =CFG_DRAM_BASE
|
||||
str r2, [r2]
|
||||
str r2, [r2]
|
||||
str r2, [r2]
|
||||
str r2, [r2]
|
||||
str r2, [r2]
|
||||
str r2, [r2]
|
||||
str r2, [r2]
|
||||
str r2, [r2]
|
||||
|
||||
@ Step 4g
|
||||
@get memory controller base address
|
||||
@
|
||||
ldr r1, =MEMC_BASE
|
||||
|
||||
@fetch current mdcnfg value
|
||||
@
|
||||
ldr r3, [r1, #MDCNFG_OFFSET]
|
||||
|
||||
@enable sdram bank 0 if installed (must do for any populated bank)
|
||||
@
|
||||
orr r3, r3, #MDCNFG_DE0
|
||||
|
||||
@write back mdcnfg, enabling the sdram bank(s)
|
||||
@
|
||||
str r3, [r1, #MDCNFG_OFFSET]
|
||||
|
||||
@ Step 4h
|
||||
@ write mdmrs
|
||||
@
|
||||
ldr r2, =CFG_MDMRS_VAL
|
||||
str r2, [r1, #MDMRS_OFFSET]
|
||||
|
||||
@ Done Memory Init
|
||||
|
||||
/*SET_LED 6 */
|
||||
|
||||
@********************************************************************
|
||||
@ Disable (mask) all interrupts at the interrupt controller
|
||||
@
|
||||
|
||||
@ clear the interrupt level register (use IRQ, not FIQ)
|
||||
@
|
||||
mov r1, #0
|
||||
ldr r2, =ICLR
|
||||
str r1, [r2]
|
||||
|
||||
@ Set interrupt mask register
|
||||
@
|
||||
ldr r1, =CFG_ICMR_VAL
|
||||
ldr r2, =ICMR
|
||||
str r1, [r2]
|
||||
|
||||
@ ********************************************************************
|
||||
@ Disable the peripheral clocks, and set the core clock
|
||||
@
|
||||
|
||||
@ Turn Off ALL on-chip peripheral clocks for re-configuration
|
||||
@
|
||||
ldr r1, =CKEN
|
||||
mov r2, #0
|
||||
str r2, [r1]
|
||||
|
||||
@ set core clocks
|
||||
@
|
||||
ldr r2, =CFG_CCCR_VAL
|
||||
ldr r1, =CCCR
|
||||
str r2, [r1]
|
||||
|
||||
#ifdef ENABLE32KHZ
|
||||
@ enable the 32Khz oscillator for RTC and PowerManager
|
||||
@
|
||||
ldr r1, =OSCC
|
||||
mov r2, #OSCC_OON
|
||||
str r2, [r1]
|
||||
|
||||
@ NOTE: spin here until OSCC.OOK get set,
|
||||
@ meaning the PLL has settled.
|
||||
@
|
||||
60:
|
||||
ldr r2, [r1]
|
||||
ands r2, r2, #1
|
||||
beq 60b
|
||||
#endif
|
||||
|
||||
@ Turn on needed clocks
|
||||
@
|
||||
ldr r1, =CKEN
|
||||
ldr r2, =CFG_CKEN_VAL
|
||||
str r2, [r1]
|
||||
|
||||
/*SET_LED 7 */
|
||||
|
||||
/* Is this needed???? */
|
||||
#define NODEBUG
|
||||
#ifdef NODEBUG
|
||||
/*Disable software and data breakpoints */
|
||||
mov r0,#0
|
||||
mcr p15,0,r0,c14,c8,0 /* ibcr0 */
|
||||
mcr p15,0,r0,c14,c9,0 /* ibcr1 */
|
||||
mcr p15,0,r0,c14,c4,0 /* dbcon */
|
||||
|
||||
/*Enable all debug functionality */
|
||||
mov r0,#0x80000000
|
||||
mcr p14,0,r0,c10,c0,0 /* dcsr */
|
||||
|
||||
#endif
|
||||
|
||||
/*SET_LED 8 */
|
||||
|
||||
mov pc, r10
|
||||
|
||||
@ End memsetup
|
55
board/xm250/u-boot.lds
Normal file
55
board/xm250/u-boot.lds
Normal file
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/pxa/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
}
|
91
board/xm250/xm250.c
Normal file
91
board/xm250/xm250.c
Normal file
|
@ -0,0 +1,91 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
#include <common.h>
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/* local prototypes */
|
||||
|
||||
inline void sleep (int i);
|
||||
|
||||
inline void
|
||||
/**********************************************************/
|
||||
sleep (int i)
|
||||
/**********************************************************/
|
||||
{
|
||||
while (i--) {
|
||||
udelay (1000000);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations
|
||||
*/
|
||||
|
||||
int
|
||||
/**********************************************************/
|
||||
board_post_init (void)
|
||||
/**********************************************************/
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
int
|
||||
/**********************************************************/
|
||||
board_init (void)
|
||||
/**********************************************************/
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
/* arch number of MicroSys XM250 */
|
||||
gd->bd->bi_arch_number = 444;
|
||||
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = 0xa0000100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
/**********************************************************/
|
||||
dram_init (void)
|
||||
/**********************************************************/
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
|
||||
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
|
||||
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
|
||||
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
|
||||
gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
|
||||
gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
|
||||
|
||||
return (0);
|
||||
}
|
|
@ -1422,7 +1422,7 @@ static void ident_cpy (unsigned char *dst, unsigned char *src, unsigned int len)
|
|||
/* reserve space for '\0' */
|
||||
if (len < 2)
|
||||
goto OUT;
|
||||
|
||||
|
||||
/* skip leading white space */
|
||||
while ((*src) && (src<end) && (*src==' '))
|
||||
++src;
|
||||
|
|
|
@ -235,14 +235,13 @@ void set_timer (ulong t)
|
|||
void udelay (unsigned long usec)
|
||||
{
|
||||
ulong tmo;
|
||||
ulong start = get_timer(0);
|
||||
|
||||
tmo = usec / 1000;
|
||||
tmo *= (timer_load_val * 100);
|
||||
tmo /= 1000;
|
||||
|
||||
tmo += get_timer (0);
|
||||
|
||||
while (get_timer_masked () < tmo)
|
||||
while ((ulong)(get_timer_masked () - start) < tmo)
|
||||
/*NOP*/;
|
||||
}
|
||||
|
||||
|
|
|
@ -830,12 +830,14 @@ int mpc5xxx_fec_initialize(bd_t * bis)
|
|||
fec->eth = (ethernet_regs *)MPC5XXX_FEC;
|
||||
fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
|
||||
fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
|
||||
#if defined(CONFIG_ICECUBE) || defined(CONFIG_TOP5200)
|
||||
# ifndef CONFIG_FEC_10MBIT
|
||||
#if defined(CONFIG_ICECUBE) ||
|
||||
defined(CONFIG_PM520) ||
|
||||
defined(CONFIG_TOP5200)
|
||||
# ifndef CONFIG_FEC_10MBIT
|
||||
fec->xcv_type = MII100;
|
||||
# else
|
||||
# else
|
||||
fec->xcv_type = MII10;
|
||||
# endif
|
||||
# endif
|
||||
#else
|
||||
#error fec->xcv_type not initialized.
|
||||
#endif
|
||||
|
|
|
@ -448,13 +448,17 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
|||
|
||||
uchar i2c_reg_read (uchar chip, uchar reg)
|
||||
{
|
||||
char buf;
|
||||
|
||||
PRINTD(("i2c_reg_read(chip=0x%02x, reg=0x%02x)\n",chip,reg));
|
||||
return 0;
|
||||
i2c_read(chip, reg, 1, &buf, 1);
|
||||
return (buf);
|
||||
}
|
||||
|
||||
void i2c_reg_write(uchar chip, uchar reg, uchar val)
|
||||
{
|
||||
PRINTD(("i2c_reg_write(chip=0x%02x, reg=0x%02x, val=0x%02x)\n",chip,reg,val));
|
||||
i2c_write(chip, reg, 1, &val, 1);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_HARD_I2C */
|
||||
|
|
|
@ -40,6 +40,7 @@
|
|||
#include "usbdcore_ep0.h"
|
||||
|
||||
|
||||
#define UDC_INIT_MDELAY 80 /* Device settle delay */
|
||||
#define UDC_MAX_ENDPOINTS 31 /* Number of endpoints on this UDC */
|
||||
|
||||
/* Some kind of debugging output... */
|
||||
|
@ -1087,6 +1088,11 @@ int udc_init (void)
|
|||
{
|
||||
u16 udc_rev;
|
||||
uchar value;
|
||||
ulong gpio;
|
||||
int i;
|
||||
|
||||
/* Let the device settle down before we start */
|
||||
for (i = 0; i < UDC_INIT_MDELAY; i++) udelay(1000);
|
||||
|
||||
udc_device = NULL;
|
||||
|
||||
|
@ -1127,6 +1133,24 @@ int udc_init (void)
|
|||
i2c_read (0x32, 0x03, 1, &value, 1);
|
||||
value |= 0x01;
|
||||
i2c_write (0x32, 0x03, 1, &value, 1);
|
||||
|
||||
gpio = inl(GPIO_PIN_CONTROL_REG);
|
||||
gpio |= 0x0002; /* A_IRDA_OFF */
|
||||
gpio |= 0x0800; /* A_SWITCH */
|
||||
gpio |= 0x8000; /* A_USB_ON */
|
||||
outl (gpio, GPIO_PIN_CONTROL_REG);
|
||||
|
||||
gpio = inl(GPIO_DIR_CONTROL_REG);
|
||||
gpio &= ~0x0002; /* A_IRDA_OFF */
|
||||
gpio &= ~0x0800; /* A_SWITCH */
|
||||
gpio &= ~0x8000; /* A_USB_ON */
|
||||
outl (gpio, GPIO_DIR_CONTROL_REG);
|
||||
|
||||
gpio = inl(GPIO_DATA_OUTPUT_REG);
|
||||
gpio |= 0x0002; /* A_IRDA_OFF */
|
||||
gpio &= ~0x0800; /* A_SWITCH */
|
||||
gpio &= ~0x8000; /* A_USB_ON */
|
||||
outl (gpio, GPIO_DATA_OUTPUT_REG);
|
||||
#endif
|
||||
|
||||
/* The VBUS_MODE bit selects whether VBUS detection is done via
|
||||
|
|
239
include/configs/PM520.h
Normal file
239
include/configs/PM520.h
Normal file
|
@ -0,0 +1,239 @@
|
|||
/*
|
||||
* (C) Copyright 2003-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC5200
|
||||
#define CONFIG_MPC5XXX 1 /* This is an MPC5xxx CPU */
|
||||
#define CONFIG_PM520 1 /* ... on PM520 board */
|
||||
|
||||
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
|
||||
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Serial console configuration
|
||||
*/
|
||||
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
|
||||
#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||
|
||||
|
||||
#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
|
||||
/*
|
||||
* PCI Mapping:
|
||||
* 0x40000000 - 0x4fffffff - PCI Memory
|
||||
* 0x50000000 - 0x50ffffff - PCI IO Space
|
||||
*/
|
||||
#define CONFIG_PCI 1
|
||||
#define CONFIG_PCI_PNP 1
|
||||
#define CONFIG_PCI_SCAN_SHOW 1
|
||||
|
||||
#define CONFIG_PCI_MEM_BUS 0x40000000
|
||||
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
|
||||
#define CONFIG_PCI_MEM_SIZE 0x10000000
|
||||
|
||||
#define CONFIG_PCI_IO_BUS 0x50000000
|
||||
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
|
||||
#define CONFIG_PCI_IO_SIZE 0x01000000
|
||||
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_EEPRO100 1
|
||||
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
|
||||
#undef CONFIG_NS8382X
|
||||
|
||||
#define ADD_PCI_CMD CFG_CMD_PCI
|
||||
|
||||
#else /* MPC5100 */
|
||||
|
||||
#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Supported commands
|
||||
*/
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD | \
|
||||
CFG_CMD_I2C | CFG_CMD_EEPROM | CFG_CMD_DATE)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Autobooting
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
|
||||
#define CONFIG_BOOTARGS "root=/dev/ram rw"
|
||||
|
||||
#if defined(CONFIG_MPC5200)
|
||||
/*
|
||||
* IPB Bus clocking configuration.
|
||||
*/
|
||||
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
|
||||
#endif
|
||||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
|
||||
|
||||
#define CFG_I2C_SPEED 100000 /* 100 kHz */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
/*
|
||||
* EEPROM configuration
|
||||
*/
|
||||
#define CFG_I2C_EEPROM_ADDR 0x58
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
#define CONFIG_RTC_PCF8563
|
||||
#define CFG_I2C_RTC_ADDR 0x51
|
||||
|
||||
/*
|
||||
* Flash configuration
|
||||
*/
|
||||
#define CFG_FLASH_BASE 0xff800000
|
||||
#define CFG_FLASH_SIZE 0x00800000
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000)
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
|
||||
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
|
||||
#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
|
||||
#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
|
||||
#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
|
||||
|
||||
#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
|
||||
|
||||
#undef CONFIG_FLASH_16BIT /* Flash is 32-bit */
|
||||
|
||||
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_SIZE 0x10000
|
||||
#define CFG_ENV_SECT_SIZE 0x40000
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*/
|
||||
#define CFG_MBAR 0xf0000000
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_DEFAULT_MBAR 0x80000000
|
||||
|
||||
/* Use SRAM until RAM will be available */
|
||||
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
|
||||
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
|
||||
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||
# define CFG_RAMBOOT 1
|
||||
#endif
|
||||
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*
|
||||
* Ethernet configuration
|
||||
*/
|
||||
#define CONFIG_MPC5XXX_FEC 1
|
||||
#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
|
||||
#define CONFIG_PHY_ADDR 0x00
|
||||
|
||||
/*
|
||||
* GPIO configuration
|
||||
*/
|
||||
#define CFG_GPS_PORT_CONFIG 0x10000004
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
/*
|
||||
* Various low-level settings
|
||||
*/
|
||||
#if defined(CONFIG_MPC5200)
|
||||
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
|
||||
#define CFG_HID0_FINAL HID0_ICE
|
||||
#else
|
||||
#define CFG_HID0_INIT 0
|
||||
#define CFG_HID0_FINAL 0
|
||||
#endif
|
||||
|
||||
#define CFG_BOOTCS_START CFG_FLASH_BASE
|
||||
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
|
||||
#define CFG_BOOTCS_CFG 0x0004fb00
|
||||
#define CFG_CS0_START CFG_FLASH_BASE
|
||||
#define CFG_CS0_SIZE CFG_FLASH_SIZE
|
||||
|
||||
#define CFG_CS_BURST 0x00000000
|
||||
#define CFG_CS_DEADCYCLE 0x33333333
|
||||
|
||||
#define CFG_RESET_ADDRESS 0xff000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* (C) Copyright 2001-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
|
@ -220,15 +220,18 @@
|
|||
/*-----------------------------------------------------------------------
|
||||
* Flash and Boot ROM mapping
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_FLASH_32MB
|
||||
#define CFG_FLASH0_BASE 0x40000000
|
||||
#define CFG_FLASH0_SIZE 0x02000000
|
||||
#else
|
||||
#define CFG_FLASH0_BASE 0xFF000000
|
||||
#define CFG_FLASH0_SIZE 0x00800000
|
||||
#endif
|
||||
#define CFG_BOOTROM_BASE 0xFF800000
|
||||
#define CFG_BOOTROM_SIZE 0x00080000
|
||||
#define CFG_FLASH0_BASE 0xFF000000
|
||||
#define CFG_FLASH0_SIZE 0x02000000
|
||||
#define CFG_DOC_BASE 0xFF800000
|
||||
#define CFG_DOC_SIZE 0x00100000
|
||||
|
||||
|
||||
/* Flash bank size (for preliminary settings)
|
||||
*/
|
||||
#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
|
||||
|
@ -237,8 +240,11 @@
|
|||
* FLASH organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
|
||||
#ifdef CONFIG_FLASH_32MB
|
||||
#define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */
|
||||
#else
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
|
||||
|
||||
#endif
|
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
|
||||
|
||||
|
@ -426,7 +432,6 @@
|
|||
* ---- --- ------- ------ ------
|
||||
* 0 60x GPCM 64 bit FLASH
|
||||
* 1 60x SDRAM 64 bit SDRAM
|
||||
* 2 Local SDRAM 32 bit SDRAM
|
||||
*
|
||||
*/
|
||||
|
||||
|
@ -440,7 +445,12 @@
|
|||
*/
|
||||
#define CFG_MIN_AM_MASK 0xC0000000
|
||||
|
||||
#define CFG_MPTPR 0x1F00
|
||||
/*
|
||||
* we use the same values for 32 MB and 128 MB SDRAM
|
||||
* refresh rate = 7.73 uS (64 MHz Bus Clock)
|
||||
*/
|
||||
#define CFG_MPTPR 0x2000
|
||||
#define CFG_PSRT 0x0E
|
||||
|
||||
#define CFG_MRS_OFFS 0x00000000
|
||||
|
||||
|
@ -512,7 +522,7 @@
|
|||
|
||||
/* Bank 2 - SDRAM
|
||||
*/
|
||||
#define CFG_PSRT 0x0F
|
||||
|
||||
#ifndef CFG_RAMBOOT
|
||||
#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_64 |\
|
||||
|
|
565
include/configs/PM828.h
Normal file
565
include/configs/PM828.h
Normal file
|
@ -0,0 +1,565 @@
|
|||
/*
|
||||
* (C) Copyright 2001-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#undef CFG_RAMBOOT
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
|
||||
#define CONFIG_PM828 1 /* ...on a PM828 module */
|
||||
|
||||
#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
|
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"bootp;" \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
|
||||
"bootm"
|
||||
|
||||
/* enable I2C and select the hardware/software driver */
|
||||
#undef CONFIG_HARD_I2C
|
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
|
||||
# define CFG_I2C_SPEED 50000
|
||||
# define CFG_I2C_SLAVE 0xFE
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration
|
||||
*/
|
||||
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
|
||||
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
|
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
|
||||
#define I2C_READ ((iop->pdat & 0x00010000) != 0)
|
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
|
||||
else iop->pdat &= ~0x00010000
|
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
|
||||
else iop->pdat &= ~0x00020000
|
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
||||
|
||||
|
||||
#define CONFIG_RTC_PCF8563
|
||||
#define CFG_I2C_RTC_ADDR 0x51
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*
|
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
|
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
|
||||
* for SCC).
|
||||
*
|
||||
* if CONFIG_CONS_NONE is defined, then the serial console routines must
|
||||
* defined elsewhere (for example, on the cogent platform, there are serial
|
||||
* ports on the motherboard which are used for the serial console - see
|
||||
* cogent/cma101/serial.[ch]).
|
||||
*/
|
||||
#define CONFIG_CONS_ON_SMC /* define if console on SMC */
|
||||
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
|
||||
#undef CONFIG_CONS_NONE /* define if console on something else*/
|
||||
#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
|
||||
|
||||
/*
|
||||
* select ethernet configuration
|
||||
*
|
||||
* if CONFIG_ETHER_ON_SCC is selected, then
|
||||
* - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
|
||||
* - CONFIG_NET_MULTI must not be defined
|
||||
*
|
||||
* if CONFIG_ETHER_ON_FCC is selected, then
|
||||
* - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
|
||||
* - CONFIG_NET_MULTI must be defined
|
||||
*
|
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
|
||||
* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
|
||||
* from CONFIG_COMMANDS to remove support for networking.
|
||||
*/
|
||||
#define CONFIG_NET_MULTI
|
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */
|
||||
|
||||
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
|
||||
#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */
|
||||
|
||||
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
|
||||
/*
|
||||
* - Rx-CLK is CLK11
|
||||
* - Tx-CLK is CLK10
|
||||
*/
|
||||
#define CONFIG_ETHER_ON_FCC1
|
||||
# define CFG_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
|
||||
#ifndef CONFIG_DB_CR826_J30x_ON
|
||||
# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
|
||||
#else
|
||||
# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
|
||||
#endif
|
||||
/*
|
||||
* - Rx-CLK is CLK15
|
||||
* - Tx-CLK is CLK14
|
||||
*/
|
||||
#define CONFIG_ETHER_ON_FCC2
|
||||
# define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
|
||||
# define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
|
||||
/*
|
||||
* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
|
||||
* - Enable Full Duplex in FSMR
|
||||
*/
|
||||
# define CFG_CPMFCR_RAMTYPE 0
|
||||
# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
|
||||
|
||||
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
|
||||
#define CONFIG_8260_CLKIN 100000000 /* in Hz */
|
||||
|
||||
#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
|
||||
#define CONFIG_BAUDRATE 230400
|
||||
#else
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_BEDBUG | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DOC | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_PCI)
|
||||
#else /* ! PCI */
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_BEDBUG | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DOC | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_I2C )
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Disk-On-Chip configuration
|
||||
*/
|
||||
|
||||
#define CFG_DOC_SHORT_TIMEOUT
|
||||
#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
|
||||
|
||||
#define CFG_DOC_SUPPORT_2000
|
||||
#define CFG_DOC_SUPPORT_MILLENNIUM
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Flash and Boot ROM mapping
|
||||
*/
|
||||
|
||||
#define CFG_BOOTROM_BASE 0xFF800000
|
||||
#define CFG_BOOTROM_SIZE 0x00080000
|
||||
#define CFG_FLASH0_BASE 0x40000000
|
||||
#define CFG_FLASH0_SIZE 0x02000000
|
||||
#define CFG_DOC_BASE 0xFF800000
|
||||
#define CFG_DOC_SIZE 0x00100000
|
||||
|
||||
|
||||
/* Flash bank size (for preliminary settings)
|
||||
*/
|
||||
#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
|
||||
|
||||
#if 0
|
||||
/* Start port with environment in flash; switch to EEPROM later */
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000)
|
||||
#define CFG_ENV_SIZE 0x40000
|
||||
#define CFG_ENV_SECT_SIZE 0x40000
|
||||
#else
|
||||
/* Final version: environment in EEPROM */
|
||||
#define CFG_ENV_IS_IN_EEPROM 1
|
||||
#define CFG_I2C_EEPROM_ADDR 0x58
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
#define CFG_ENV_OFFSET 512
|
||||
#define CFG_ENV_SIZE (2048 - 512)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words
|
||||
*
|
||||
* if you change bits in the HRCW, you must also change the CFG_*
|
||||
* defines for the various registers affected by the HRCW e.g. changing
|
||||
* HRCW_DPPCxx requires you to also change CFG_SIUMCR.
|
||||
*/
|
||||
#if defined(CONFIG_BOOT_ROM)
|
||||
#define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
|
||||
#else
|
||||
#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
|
||||
#endif
|
||||
|
||||
/* no slaves so just fill with zeros */
|
||||
#define CFG_HRCW_SLAVE1 0
|
||||
#define CFG_HRCW_SLAVE2 0
|
||||
#define CFG_HRCW_SLAVE3 0
|
||||
#define CFG_HRCW_SLAVE4 0
|
||||
#define CFG_HRCW_SLAVE5 0
|
||||
#define CFG_HRCW_SLAVE6 0
|
||||
#define CFG_HRCW_SLAVE7 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CFG_IMMR 0xF0000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR
|
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*
|
||||
* 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
|
||||
* is mapped at SDRAM_BASE2_PRELIM.
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_FLASH_BASE CFG_FLASH0_BASE
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
|
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||
# define CFG_RAMBOOT
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_PCI_PNP
|
||||
#define CONFIG_EEPRO100
|
||||
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11
|
||||
*-----------------------------------------------------------------------
|
||||
* HID0 also contains cache control - initially enable both caches and
|
||||
* invalidate contents, then the final state leaves only the instruction
|
||||
* cache enabled. Note that Power-On and Hard reset invalidate the caches,
|
||||
* but Soft reset does not.
|
||||
*
|
||||
* HID1 has only read-only information - nothing to set.
|
||||
*/
|
||||
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
|
||||
HID0_IFEM|HID0_ABE)
|
||||
#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
|
||||
#define CFG_HID2 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register 5-5
|
||||
*-----------------------------------------------------------------------
|
||||
* turn on Checkstop Reset Enable
|
||||
*/
|
||||
#define CFG_RMR RMR_CSRE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define BCR_APD01 0x10000000
|
||||
#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#if 0
|
||||
#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
|
||||
#else
|
||||
#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
|
||||
#endif
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 4-35
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
|
||||
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
|
||||
#else
|
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
|
||||
SYPCR_SWRI|SYPCR_SWP)
|
||||
#endif /* CONFIG_WATCHDOG */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
|
||||
* and enable Time Counter
|
||||
*/
|
||||
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
|
||||
* Periodic timer
|
||||
*/
|
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_SCCR (SCCR_DFBRG00)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_RCCR 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* Bank Bus Machine PortSz Device
|
||||
* ---- --- ------- ------ ------
|
||||
* 0 60x GPCM 64 bit FLASH
|
||||
* 1 60x SDRAM 64 bit SDRAM
|
||||
*
|
||||
*/
|
||||
|
||||
/* Initialize SDRAM on local bus
|
||||
*/
|
||||
#define CFG_INIT_LOCAL_SDRAM
|
||||
|
||||
|
||||
/* Minimum mask to separate preliminary
|
||||
* address ranges for CS[0:2]
|
||||
*/
|
||||
#define CFG_MIN_AM_MASK 0xC0000000
|
||||
|
||||
/*
|
||||
* we use the same values for 32 MB and 128 MB SDRAM
|
||||
* refresh rate = 7.68 uS (100 MHz Bus Clock)
|
||||
*/
|
||||
#define CFG_MPTPR 0x2000
|
||||
#define CFG_PSRT 0x16
|
||||
|
||||
#define CFG_MRS_OFFS 0x00000000
|
||||
|
||||
|
||||
#if defined(CONFIG_BOOT_ROM)
|
||||
/*
|
||||
* Bank 0 - Boot ROM (8 bit wide)
|
||||
*/
|
||||
#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
|
||||
BRx_PS_8 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
|
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_5_CLK |\
|
||||
ORxG_EHTR |\
|
||||
ORxG_TRLX)
|
||||
|
||||
/*
|
||||
* Bank 1 - Flash (64 bit wide)
|
||||
*/
|
||||
#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_64 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
|
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_5_CLK |\
|
||||
ORxG_EHTR |\
|
||||
ORxG_TRLX)
|
||||
|
||||
#else /* ! CONFIG_BOOT_ROM */
|
||||
|
||||
/*
|
||||
* Bank 0 - Flash (64 bit wide)
|
||||
*/
|
||||
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_64 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
|
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_5_CLK |\
|
||||
ORxG_EHTR |\
|
||||
ORxG_TRLX)
|
||||
|
||||
/*
|
||||
* Bank 1 - Disk-On-Chip
|
||||
*/
|
||||
#define CFG_BR1_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_8 |\
|
||||
BRx_MS_GPCM_P |\
|
||||
BRx_V)
|
||||
|
||||
#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\
|
||||
ORxG_CSNT |\
|
||||
ORxG_ACS_DIV1 |\
|
||||
ORxG_SCY_5_CLK |\
|
||||
ORxG_EHTR |\
|
||||
ORxG_TRLX)
|
||||
|
||||
#endif /* CONFIG_BOOT_ROM */
|
||||
|
||||
/* Bank 2 - SDRAM
|
||||
*/
|
||||
|
||||
#ifndef CFG_RAMBOOT
|
||||
#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
|
||||
BRx_PS_64 |\
|
||||
BRx_MS_SDRAM_P |\
|
||||
BRx_V)
|
||||
|
||||
/* SDRAM initialization values for 8-column chips
|
||||
*/
|
||||
#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
|
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI0_A9 |\
|
||||
ORxS_NUMR_12)
|
||||
|
||||
#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
|
||||
PSDMR_BSMA_A14_A16 |\
|
||||
PSDMR_SDA10_PBI0_A10 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_1C |\
|
||||
PSDMR_CL_2)
|
||||
|
||||
/* SDRAM initialization values for 9-column chips
|
||||
*/
|
||||
#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
|
||||
ORxS_BPD_4 |\
|
||||
ORxS_ROWST_PBI0_A7 |\
|
||||
ORxS_NUMR_13)
|
||||
|
||||
#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
|
||||
PSDMR_BSMA_A13_A15 |\
|
||||
PSDMR_SDA10_PBI0_A9 |\
|
||||
PSDMR_RFRC_7_CLK |\
|
||||
PSDMR_PRETOACT_2W |\
|
||||
PSDMR_ACTTORW_2W |\
|
||||
PSDMR_LDOTOPRE_1C |\
|
||||
PSDMR_WRC_1C |\
|
||||
PSDMR_CL_2)
|
||||
|
||||
#define CFG_OR2_PRELIM CFG_OR2_9COL
|
||||
#define CFG_PSDMR CFG_PSDMR_9COL
|
||||
|
||||
#endif /* CFG_RAMBOOT */
|
||||
|
||||
#endif /* __CONFIG_H */
|
|
@ -250,7 +250,7 @@
|
|||
"add_net=setenv bootargs $bootargs ethaddr=$ethaddr " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
|
||||
"add_misc=setenv bootargs $bootargs console=ttyS0 panic=1\0" \
|
||||
"u-boot=/tftpboot/TRAB/u-boot.bin-old\0" \
|
||||
"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
|
||||
"load=tftp C100000 ${u-boot}\0" \
|
||||
"update=protect off 0 3FFFF;era 0 3FFFF;" \
|
||||
"cp.b C100000 0 $filesize;" \
|
||||
|
@ -273,7 +273,7 @@
|
|||
"add_net=setenv bootargs $(bootargs) ethaddr=$(ethaddr) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0" \
|
||||
"add_misc=setenv bootargs $(bootargs) console=ttyS0 panic=1\0" \
|
||||
"u-boot=/tftpboot/TRAB/u-boot.bin-old\0" \
|
||||
"u-boot=/tftpboot/TRAB/u-boot.bin\0" \
|
||||
"load=tftp C100000 $(u-boot)\0" \
|
||||
"update=protect off 0 3FFFF;era 0 3FFFF;" \
|
||||
"cp.b C100000 0 $(filesize);" \
|
||||
|
|
355
include/configs/xm250.h
Normal file
355
include/configs/xm250.h
Normal file
|
@ -0,0 +1,355 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* If we are developing, we might want to start armboot from ram
|
||||
* so we MUST NOT initialize critical regs like mem-timing ...
|
||||
*/
|
||||
#define CONFIG_INIT_CRITICAL /* undef for developing */
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
|
||||
#define CONFIG_XM250 1 /* on a MicroSys XM250 Board */
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
/*
|
||||
* Size of malloc() pool; this lives below the uppermost 128 KiB which are
|
||||
* used for the RAM copy of the uboot code
|
||||
*
|
||||
*/
|
||||
#define CFG_MALLOC_LEN (256*1024)
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
#define CONFIG_DRIVER_SMC91111
|
||||
#define CONFIG_SMC91111_BASE 0x04000300
|
||||
#undef CONFIG_SMC91111_EXT_PHY
|
||||
#define CONFIG_SMC_USE_32_BIT
|
||||
#undef CONFIG_SHOW_ACTIVITY
|
||||
#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
|
||||
|
||||
/*
|
||||
* I2C bus
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CFG_I2C_SPEED 50000
|
||||
#define CFG_I2C_SLAVE 0xfe
|
||||
|
||||
#define CONFIG_RTC_PCF8563 1
|
||||
#define CFG_I2C_RTC_ADDR 0x51
|
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0x58 /* A0 = 0 (hardwired) */
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 4 bits = 16 octets */
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* length of address */
|
||||
#define CFG_EEPROM_SIZE 2048 /* size in bytes */
|
||||
#undef CFG_I2C_INIT_BOARD /* board has no own init */
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_FFUART 1 /* we use FFUART */
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_I2C )
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
|
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
|
||||
|
||||
#define CFG_LOAD_ADDR 0xa3000000 /* default load address */
|
||||
|
||||
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
|
||||
#define CFG_CPUSPEED 0x161 /* set core clock to 400/400/100 MHz */
|
||||
|
||||
/* valid baudrates */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* Definitions related to passing arguments to kernel.
|
||||
*/
|
||||
#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
|
||||
#undef CONFIG_INITRD_TAG /* do not send initrd params */
|
||||
#undef CONFIG_VFD /* do not send framebuffer setup */
|
||||
|
||||
/*
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 4
|
||||
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
|
||||
#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
|
||||
#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
|
||||
#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
|
||||
#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
|
||||
#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
|
||||
#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
|
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
|
||||
#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
|
||||
#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
|
||||
#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
|
||||
#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
|
||||
|
||||
#define CFG_DRAM_BASE 0xa0000000
|
||||
#define CFG_DRAM_SIZE 0x04000000
|
||||
|
||||
#define CFG_FLASH_BASE PHYS_FLASH_1
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
|
||||
/* timeout values are in ticks */
|
||||
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
|
||||
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
|
||||
#define CFG_FLASH_LOCK_TOUT (2*CFG_HZ) /* Timeout for Flash Set Lock Bit */
|
||||
#define CFG_FLASH_UNLOCK_TOUT (2*CFG_HZ) /* Timeout for Flash Clear Lock Bits */
|
||||
#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x4000
|
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
|
||||
#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* CPU specific defines
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
* GPIO settings
|
||||
*
|
||||
* GPIO pin assignments
|
||||
* GPIO Name Dir Out AF
|
||||
* 0 NC
|
||||
* 1 NC
|
||||
* 2 SIRQ1 I
|
||||
* 3 SIRQ2 I
|
||||
* 4 SIRQ3 I
|
||||
* 5 DMAACK1 O 0
|
||||
* 6 DMAACK2 O 0
|
||||
* 7 DMAACK3 O 0
|
||||
* 8 TC1 O 0
|
||||
* 9 TC2 O 0
|
||||
* 10 TC3 O 0
|
||||
* 11 nDMAEN O 1
|
||||
* 12 AENCTRL O 0
|
||||
* 13 PLDTC O 0
|
||||
* 14 ETHIRQ I
|
||||
* 15 NC
|
||||
* 16 NC
|
||||
* 17 NC
|
||||
* 18 RDY I
|
||||
* 19 DMASIO I
|
||||
* 20 ETHIRQ NC
|
||||
* 21 NC
|
||||
* 22 PGMEN O 1 FIXME for debug only enable flash
|
||||
* 23 NC
|
||||
* 24 NC
|
||||
* 25 NC
|
||||
* 26 NC
|
||||
* 27 NC
|
||||
* 28 NC
|
||||
* 29 NC
|
||||
* 30 NC
|
||||
* 31 NC
|
||||
* 32 NC
|
||||
* 33 NC
|
||||
* 34 FFRXD I 01
|
||||
* 35 FFCTS I 01
|
||||
* 36 FFDCD I 01
|
||||
* 37 FFDSR I 01
|
||||
* 38 FFRI I 01
|
||||
* 39 FFTXD O 1 10
|
||||
* 40 FFDTR O 0 10
|
||||
* 41 FFRTS O 0 10
|
||||
* 42 RS232FOFF O 0 00
|
||||
* 43 NC
|
||||
* 44 NC
|
||||
* 45 IRSL0 O 0
|
||||
* 46 IRRX0 I 01
|
||||
* 47 IRTX0 O 0 10
|
||||
* 48 NC
|
||||
* 49 nIOWE O 0
|
||||
* 50 NC
|
||||
* 51 NC
|
||||
* 52 NC
|
||||
* 53 NC
|
||||
* 54 NC
|
||||
* 55 NC
|
||||
* 56 NC
|
||||
* 57 NC
|
||||
* 58 DKDIRQ I
|
||||
* 59 NC
|
||||
* 60 NC
|
||||
* 61 NC
|
||||
* 62 NC
|
||||
* 63 NC
|
||||
* 64 COMLED O 0
|
||||
* 65 COMLED O 0
|
||||
* 66 COMLED O 0
|
||||
* 67 COMLED O 0
|
||||
* 68 COMLED O 0
|
||||
* 69 COMLED O 0
|
||||
* 70 COMLED O 0
|
||||
* 71 COMLED O 0
|
||||
* 72 NC
|
||||
* 73 NC
|
||||
* 74 NC
|
||||
* 75 NC
|
||||
* 76 NC
|
||||
* 77 NC
|
||||
* 78 CSIO O 1
|
||||
* 79 NC
|
||||
* 80 CSETH O 1
|
||||
*
|
||||
* NOTE: All NC's are defined to be outputs
|
||||
*
|
||||
*/
|
||||
/* Pin direction control */
|
||||
#define CFG_GPDR0_VAL 0xd3808000
|
||||
#define CFG_GPDR1_VAL 0xfcffab83
|
||||
#define CFG_GPDR2_VAL 0x0001ffff
|
||||
/* Set and Clear registers */
|
||||
#define CFG_GPSR0_VAL 0x00008000
|
||||
#define CFG_GPSR1_VAL 0x00ff0002
|
||||
#define CFG_GPSR2_VAL 0x0001c000
|
||||
#define CFG_GPCR0_VAL 0x00000000
|
||||
#define CFG_GPCR1_VAL 0x00000000
|
||||
#define CFG_GPCR2_VAL 0x00000000
|
||||
/* Edge detect registers (these are set by the kernel) */
|
||||
#define CFG_GRER0_VAL 0x00002180
|
||||
#define CFG_GRER1_VAL 0x00000000
|
||||
#define CFG_GRER2_VAL 0x00000000
|
||||
#define CFG_GFER0_VAL 0x000043e0
|
||||
#define CFG_GFER1_VAL 0x00000000
|
||||
#define CFG_GFER2_VAL 0x00000000
|
||||
/* Alternate function registers */
|
||||
#define CFG_GAFR0_L_VAL 0x80000004
|
||||
#define CFG_GAFR0_U_VAL 0x595a8010
|
||||
#define CFG_GAFR1_L_VAL 0x699a9559
|
||||
#define CFG_GAFR1_U_VAL 0xaaa5aaaa
|
||||
#define CFG_GAFR2_L_VAL 0xaaaaaaaa
|
||||
#define CFG_GAFR2_U_VAL 0x00000002
|
||||
|
||||
/*
|
||||
* Clocks, power control and interrupts
|
||||
*/
|
||||
#define CFG_PSSR_VAL 0x00000030
|
||||
#define CFG_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */
|
||||
#define CFG_CKEN_VAL 0x000141ec /* FFUART and STUART enabled */
|
||||
#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */
|
||||
|
||||
/* FIXME
|
||||
*
|
||||
* RTC settings
|
||||
* Watchdog
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Memory settings
|
||||
*
|
||||
*/
|
||||
#define CFG_MSC0_VAL 0x122423f0 /* FLASH / LAN (cs0)/(cS1) */
|
||||
#define CFG_MSC1_VAL 0x35f4aa4c /* USB / ST3+ST5 (cs2)/(cS3) */
|
||||
#define CFG_MSC2_VAL 0x35f435fc /* IDE / BCR + WatchDog (cs4)/(cS5) */
|
||||
#define CFG_MDCNFG_VAL 0x000009c9
|
||||
#define CFG_MDMRS_VAL 0x00220022
|
||||
#define CFG_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in memsetup.S */
|
||||
|
||||
/*
|
||||
* PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
|
||||
*/
|
||||
#define CFG_MECR_VAL 0x00000000
|
||||
#define CFG_MCMEM0_VAL 0x00010504
|
||||
#define CFG_MCMEM1_VAL 0x00010504
|
||||
#define CFG_MCATT0_VAL 0x00010504
|
||||
#define CFG_MCATT1_VAL 0x00010504
|
||||
#define CFG_MCIO0_VAL 0x00004715
|
||||
#define CFG_MCIO1_VAL 0x00004715
|
||||
|
||||
/* Board specific defines */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* global prototypes */
|
||||
void led_code(int code, int color);
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
|
@ -168,7 +168,9 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
|||
#define AMD_ID_DL163B 0x222B222B /* 29DL163B ID (16 M, bottom boot sect) */
|
||||
|
||||
#define AMD_ID_LV320T 0x22F622F6 /* 29LV320T ID (32 M, top boot sector) */
|
||||
#define MX_ID_LV320T 0x22A722A7 /* 29LV320T by Macronix, AMD compatible */
|
||||
#define AMD_ID_LV320B 0x22F922F9 /* 29LV320B ID (32 M, bottom boot sect) */
|
||||
#define MX_ID_LV320B 0x22A822A8 /* 29LV320B by Macronix, AMD compatible */
|
||||
|
||||
#define AMD_ID_DL322T 0x22552255 /* 29DL322T ID (32 M, top boot sector) */
|
||||
#define AMD_ID_DL322B 0x22562256 /* 29DL322B ID (32 M, bottom boot sect) */
|
||||
|
@ -348,6 +350,8 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
|||
#define FLASH_AMLV320B 0x00A7 /* AMD 29LV320MB ( 32M = 2M x 16 ) */
|
||||
#define FLASH_AMLV320T 0x00A8 /* AMD 29LV320MT ( 32M = 2M x 16 ) */
|
||||
#define FLASH_AMLV256U 0x00AA /* AMD 29LV256M ( 256M = 16M x 16 ) */
|
||||
#define FLASH_MXLV320B 0x00AB /* MX 29LV320MB ( 32M = 2M x 16 ) */
|
||||
#define FLASH_MXLV320T 0x00AC /* MX 29LV320MT ( 32M = 2M x 16 ) */
|
||||
/* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */
|
||||
#define FLASH_28F256L18T 0x00B0
|
||||
#define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */
|
||||
|
|
Loading…
Reference in a new issue