mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 14:10:43 +00:00
arc: significant cache rework
[1] Align cache management functions to those in Linux kernel. I.e.:
a) Use the same functions for all cache ops (D$ Inv/Flush)
b) Split cache ops in 3 sub-functions: "before", "lineloop" and
"after". That way we may re-use "before" and "after" functions for
region and full cache ops.
[2] Implement full-functional L2 (SLC) management. Before SLC was
simply disabled early on boot. It's also possible to enable or disable
L2 cache from config utility.
[3] Disable/enable corresponding caches early on boot. So if U-Boot is
configured to use caches they will be used at all times (this is useful
in partucular for speed-up of relocation).
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit is contained in:
Alexey Brodkin
Alexey Brodkin
parent
8b2eb776b1
commit
ef639e6f70
6 changed files with 305 additions and 150 deletions
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@ -47,9 +47,12 @@
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#endif
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#define ARC_BCR_DC_BUILD 0x72
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#define ARC_BCR_SLC 0xce
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#define ARC_AUX_SLC_CONTROL 0x903
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#define ARC_AUX_SLC_CONFIG 0x901
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#define ARC_AUX_SLC_CTRL 0x903
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#define ARC_AUX_SLC_FLUSH 0x904
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#define ARC_AUX_SLC_INVALIDATE 0x905
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#define ARC_AUX_SLC_IVDL 0x910
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#define ARC_AUX_SLC_FLDL 0x912
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#ifndef __ASSEMBLY__
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/* Accessors for auxiliary registers */
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@ -29,12 +29,7 @@
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_ISA_ARCV2
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void slc_enable(void);
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void slc_disable(void);
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void slc_flush(void);
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void slc_invalidate(void);
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#endif
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void cache_init(void);
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#endif /* __ASSEMBLY__ */
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@ -5,9 +5,13 @@
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*/
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#include <config.h>
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#include <linux/compiler.h>
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#include <linux/kernel.h>
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#include <asm/arcregs.h>
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#include <asm/cache.h>
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#define CACHE_LINE_MASK (~(CONFIG_SYS_CACHELINE_SIZE - 1))
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/* Bit values in IC_CTRL */
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#define IC_CTRL_CACHE_DISABLE (1 << 0)
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@ -18,60 +22,186 @@
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#define CACHE_VER_NUM_MASK 0xF
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#define SLC_CTRL_SB (1 << 2)
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#define OP_INV 0x1
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#define OP_FLUSH 0x2
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#define OP_INV_IC 0x3
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#ifdef CONFIG_ISA_ARCV2
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/*
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* By default that variable will fall into .bss section.
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* But .bss section is not relocated and so it will be initilized before
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* relocation but will be used after being zeroed.
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*/
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int slc_line_sz __section(".data");
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int slc_exists __section(".data");
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static unsigned int __before_slc_op(const int op)
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{
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unsigned int reg = reg;
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if (op == OP_INV) {
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/*
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* IM is set by default and implies Flush-n-inv
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* Clear it here for vanilla inv
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*/
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reg = read_aux_reg(ARC_AUX_SLC_CTRL);
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write_aux_reg(ARC_AUX_SLC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
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}
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return reg;
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}
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static void __after_slc_op(const int op, unsigned int reg)
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{
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if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
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while (read_aux_reg(ARC_AUX_SLC_CTRL) &
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DC_CTRL_FLUSH_STATUS)
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;
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/* Switch back to default Invalidate mode */
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if (op == OP_INV)
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write_aux_reg(ARC_AUX_SLC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
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}
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static inline void __slc_line_loop(unsigned long paddr, unsigned long sz,
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const int op)
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{
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unsigned int aux_cmd;
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int num_lines;
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#define SLC_LINE_MASK (~(slc_line_sz - 1))
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aux_cmd = op & OP_INV ? ARC_AUX_SLC_IVDL : ARC_AUX_SLC_FLDL;
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sz += paddr & ~SLC_LINE_MASK;
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paddr &= SLC_LINE_MASK;
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num_lines = DIV_ROUND_UP(sz, slc_line_sz);
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while (num_lines-- > 0) {
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write_aux_reg(aux_cmd, paddr);
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paddr += slc_line_sz;
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}
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}
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static inline void __slc_entire_op(const int cacheop)
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{
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int aux;
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unsigned int ctrl_reg = __before_slc_op(cacheop);
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if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
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aux = ARC_AUX_SLC_INVALIDATE;
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else
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aux = ARC_AUX_SLC_FLUSH;
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write_aux_reg(aux, 0x1);
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__after_slc_op(cacheop, ctrl_reg);
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}
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static inline void __slc_line_op(unsigned long paddr, unsigned long sz,
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const int cacheop)
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{
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unsigned int ctrl_reg = __before_slc_op(cacheop);
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__slc_line_loop(paddr, sz, cacheop);
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__after_slc_op(cacheop, ctrl_reg);
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}
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#else
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#define __slc_entire_op(cacheop)
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#define __slc_line_op(paddr, sz, cacheop)
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#endif
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static inline int icache_exists(void)
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{
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/* Check if Instruction Cache is available */
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if (read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK)
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return 1;
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else
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return 0;
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}
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static inline int dcache_exists(void)
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{
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/* Check if Data Cache is available */
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if (read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK)
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return 1;
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else
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return 0;
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}
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void cache_init(void)
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{
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#ifdef CONFIG_ISA_ARCV2
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/* Check if System-Level Cache (SLC) is available */
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if (read_aux_reg(ARC_BCR_SLC) & CACHE_VER_NUM_MASK) {
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#define LSIZE_OFFSET 4
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#define LSIZE_MASK 3
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if (read_aux_reg(ARC_AUX_SLC_CONFIG) &
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(LSIZE_MASK << LSIZE_OFFSET))
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slc_line_sz = 64;
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else
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slc_line_sz = 128;
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slc_exists = 1;
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} else {
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slc_exists = 0;
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}
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#endif
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}
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int icache_status(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
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if (!icache_exists())
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return 0;
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return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
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IC_CTRL_CACHE_DISABLE;
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if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE)
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return 0;
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else
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return 1;
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}
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void icache_enable(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
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return;
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if (icache_exists())
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write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
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~IC_CTRL_CACHE_DISABLE);
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}
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void icache_disable(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
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return;
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if (icache_exists())
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write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
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IC_CTRL_CACHE_DISABLE);
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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void invalidate_icache_all(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
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return;
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/* Any write to IC_IVIC register triggers invalidation of entire I$ */
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if (icache_status()) {
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write_aux_reg(ARC_AUX_IC_IVIC, 1);
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read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
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}
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}
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#else
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void invalidate_icache_all(void)
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{
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}
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#endif
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int dcache_status(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
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if (!dcache_exists())
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return 0;
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return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
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DC_CTRL_CACHE_DISABLE;
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if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE)
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return 0;
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else
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return 1;
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}
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void dcache_enable(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
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if (!dcache_exists())
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return;
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write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
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@ -80,91 +210,123 @@ void dcache_enable(void)
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void dcache_disable(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
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if (!dcache_exists())
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return;
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write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
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DC_CTRL_CACHE_DISABLE);
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}
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void flush_dcache_all(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
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return;
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/* Do flush of entire cache */
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write_aux_reg(ARC_AUX_DC_FLSH, 1);
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/* Wait flush end */
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while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
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;
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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static void dcache_flush_line(unsigned addr)
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{
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#if (CONFIG_ARC_MMU_VER == 3)
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write_aux_reg(ARC_AUX_DC_PTAG, addr);
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#endif
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write_aux_reg(ARC_AUX_DC_FLDL, addr);
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/* Wait flush end */
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while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
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;
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#ifndef CONFIG_SYS_ICACHE_OFF
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/*
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* Invalidate I$ for addresses range just flushed from D$.
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* If we try to execute data flushed above it will be valid/correct
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/*
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* Common Helper for Line Operations on {I,D}-Cache
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*/
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#if (CONFIG_ARC_MMU_VER == 3)
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write_aux_reg(ARC_AUX_IC_PTAG, addr);
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#endif
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write_aux_reg(ARC_AUX_IC_IVIL, addr);
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#endif /* CONFIG_SYS_ICACHE_OFF */
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}
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#endif /* CONFIG_SYS_DCACHE_OFF */
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void flush_dcache_range(unsigned long start, unsigned long end)
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static inline void __cache_line_loop(unsigned long paddr, unsigned long sz,
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const int cacheop)
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{
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#ifndef CONFIG_SYS_DCACHE_OFF
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unsigned int addr;
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unsigned int aux_cmd;
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#if (CONFIG_ARC_MMU_VER == 3)
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unsigned int aux_tag;
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#endif
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int num_lines;
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start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
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end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
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if (cacheop == OP_INV_IC) {
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aux_cmd = ARC_AUX_IC_IVIL;
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#if (CONFIG_ARC_MMU_VER == 3)
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aux_tag = ARC_AUX_IC_PTAG;
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#endif
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} else {
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/* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
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aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
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#if (CONFIG_ARC_MMU_VER == 3)
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aux_tag = ARC_AUX_DC_PTAG;
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#endif
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}
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for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE)
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dcache_flush_line(addr);
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#endif /* CONFIG_SYS_DCACHE_OFF */
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sz += paddr & ~CACHE_LINE_MASK;
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paddr &= CACHE_LINE_MASK;
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num_lines = DIV_ROUND_UP(sz, CONFIG_SYS_CACHELINE_SIZE);
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while (num_lines-- > 0) {
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#if (CONFIG_ARC_MMU_VER == 3)
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write_aux_reg(aux_tag, paddr);
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#endif
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write_aux_reg(aux_cmd, paddr);
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paddr += CONFIG_SYS_CACHELINE_SIZE;
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}
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}
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static unsigned int __before_dc_op(const int op)
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{
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unsigned int reg;
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if (op == OP_INV) {
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/*
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* IM is set by default and implies Flush-n-inv
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* Clear it here for vanilla inv
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*/
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reg = read_aux_reg(ARC_AUX_DC_CTRL);
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write_aux_reg(ARC_AUX_DC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
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}
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return reg;
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}
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static void __after_dc_op(const int op, unsigned int reg)
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{
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if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
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while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
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;
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/* Switch back to default Invalidate mode */
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if (op == OP_INV)
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write_aux_reg(ARC_AUX_DC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
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}
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static inline void __dc_entire_op(const int cacheop)
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{
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int aux;
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unsigned int ctrl_reg = __before_dc_op(cacheop);
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if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
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aux = ARC_AUX_DC_IVDC;
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else
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aux = ARC_AUX_DC_FLSH;
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write_aux_reg(aux, 0x1);
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__after_dc_op(cacheop, ctrl_reg);
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}
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static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
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const int cacheop)
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{
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unsigned int ctrl_reg = __before_dc_op(cacheop);
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__cache_line_loop(paddr, sz, cacheop);
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__after_dc_op(cacheop, ctrl_reg);
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}
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#else
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#define __dc_entire_op(cacheop)
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#define __dc_line_op(paddr, sz, cacheop)
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#endif /* !CONFIG_SYS_DCACHE_OFF */
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void invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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#ifndef CONFIG_SYS_DCACHE_OFF
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unsigned int addr;
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start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
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end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
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for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
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#if (CONFIG_ARC_MMU_VER == 3)
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write_aux_reg(ARC_AUX_DC_PTAG, addr);
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__dc_line_op(start, end - start, OP_INV);
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#ifdef CONFIG_ISA_ARCV2
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if (slc_exists)
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__slc_line_op(start, end - start, OP_INV);
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#endif
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write_aux_reg(ARC_AUX_DC_IVDL, addr);
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}
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#endif /* CONFIG_SYS_DCACHE_OFF */
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}
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void invalidate_dcache_all(void)
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
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return;
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/* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
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write_aux_reg(ARC_AUX_DC_IVDC, 1);
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__dc_line_op(start, end - start, OP_FLUSH);
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#ifdef CONFIG_ISA_ARCV2
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if (slc_exists)
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__slc_line_op(start, end - start, OP_FLUSH);
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#endif
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}
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void flush_cache(unsigned long start, unsigned long size)
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@ -172,47 +334,20 @@ void flush_cache(unsigned long start, unsigned long size)
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flush_dcache_range(start, start + size);
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}
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void invalidate_dcache_all(void)
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{
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__dc_entire_op(OP_INV);
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#ifdef CONFIG_ISA_ARCV2
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void slc_enable(void)
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{
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/* If SLC ver = 0, no SLC present in CPU */
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if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
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return;
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write_aux_reg(ARC_AUX_SLC_CONTROL,
|
||||
read_aux_reg(ARC_AUX_SLC_CONTROL) & ~1);
|
||||
if (slc_exists)
|
||||
__slc_entire_op(OP_INV);
|
||||
#endif
|
||||
}
|
||||
|
||||
void slc_disable(void)
|
||||
void flush_dcache_all(void)
|
||||
{
|
||||
/* If SLC ver = 0, no SLC present in CPU */
|
||||
if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
|
||||
return;
|
||||
|
||||
write_aux_reg(ARC_AUX_SLC_CONTROL,
|
||||
read_aux_reg(ARC_AUX_SLC_CONTROL) | 1);
|
||||
__dc_entire_op(OP_FLUSH);
|
||||
#ifdef CONFIG_ISA_ARCV2
|
||||
if (slc_exists)
|
||||
__slc_entire_op(OP_FLUSH);
|
||||
#endif
|
||||
}
|
||||
|
||||
void slc_flush(void)
|
||||
{
|
||||
/* If SLC ver = 0, no SLC present in CPU */
|
||||
if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
|
||||
return;
|
||||
|
||||
write_aux_reg(ARC_AUX_SLC_FLUSH, 1);
|
||||
|
||||
/* Wait flush end */
|
||||
while (read_aux_reg(ARC_AUX_SLC_CONTROL) & SLC_CTRL_SB)
|
||||
;
|
||||
}
|
||||
|
||||
void slc_invalidate(void)
|
||||
{
|
||||
/* If SLC ver = 0, no SLC present in CPU */
|
||||
if (!(read_aux_reg(ARC_BCR_SLC) & 0xff))
|
||||
return;
|
||||
|
||||
write_aux_reg(ARC_AUX_SLC_INVALIDATE, 1);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ISA_ARCV2 */
|
||||
|
|
|
|||
|
|
@ -23,6 +23,8 @@ int arch_cpu_init(void)
|
|||
gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
|
||||
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
|
||||
|
||||
cache_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -10,16 +10,8 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
int init_cache_f_r(void)
|
||||
{
|
||||
#ifndef CONFIG_SYS_ICACHE_OFF
|
||||
icache_enable();
|
||||
/* Make sure no stale entries persist from before we disabled cache */
|
||||
invalidate_icache_all();
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
dcache_enable();
|
||||
/* Make sure no stale entries persist from before we disabled cache */
|
||||
invalidate_dcache_all();
|
||||
flush_dcache_all();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -13,19 +13,47 @@ ENTRY(_start)
|
|||
/* Setup interrupt vector base that matches "__text_start" */
|
||||
sr __ivt_start, [ARC_AUX_INTR_VEC_BASE]
|
||||
|
||||
; Disable/enable I-cache according to configuration
|
||||
lr r5, [ARC_BCR_IC_BUILD]
|
||||
breq r5, 0, 1f ; I$ doesn't exist
|
||||
lr r5, [ARC_AUX_IC_CTRL]
|
||||
#ifndef CONFIG_SYS_ICACHE_OFF
|
||||
bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
|
||||
#else
|
||||
bset r5, r5, 0 ; I$ exists, but is not used
|
||||
#endif
|
||||
sr r5, [ARC_AUX_IC_CTRL]
|
||||
|
||||
1:
|
||||
; Disable/enable D-cache according to configuration
|
||||
lr r5, [ARC_BCR_DC_BUILD]
|
||||
breq r5, 0, 1f ; D$ doesn't exist
|
||||
lr r5, [ARC_AUX_DC_CTRL]
|
||||
bclr r5, r5, 6 ; Invalidate (discard w/o wback)
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
bclr r5, r5, 0 ; Enable (+Inv)
|
||||
#else
|
||||
bset r5, r5, 0 ; Disable (+Inv)
|
||||
#endif
|
||||
sr r5, [ARC_AUX_DC_CTRL]
|
||||
|
||||
1:
|
||||
#ifdef CONFIG_ISA_ARCV2
|
||||
; Disable System-Level Cache (SLC)
|
||||
lr r5, [ARC_BCR_SLC]
|
||||
breq r5, 0, 1f ; SLC doesn't exist
|
||||
lr r5, [ARC_AUX_SLC_CTRL]
|
||||
bclr r5, r5, 6 ; Invalidate (discard w/o wback)
|
||||
bclr r5, r5, 0 ; Enable (+Inv)
|
||||
sr r5, [ARC_AUX_SLC_CTRL]
|
||||
|
||||
1:
|
||||
#endif
|
||||
|
||||
/* Setup stack- and frame-pointers */
|
||||
mov %sp, CONFIG_SYS_INIT_SP_ADDR
|
||||
mov %fp, %sp
|
||||
|
||||
/* Unconditionally disable caches */
|
||||
#ifdef CONFIG_ISA_ARCV2
|
||||
bl slc_flush
|
||||
bl slc_disable
|
||||
#endif
|
||||
bl flush_dcache_all
|
||||
bl dcache_disable
|
||||
bl icache_disable
|
||||
|
||||
/* Allocate and zero GD, update SP */
|
||||
mov %r0, %sp
|
||||
bl board_init_f_mem
|
||||
|
|
|
|||
Loading…
Reference in a new issue