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board/t2080rdb: some update for t2080rdb

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- update readme.
- add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315
  ucode from NOR/NAND/SPI/SD/REMOTE.
- update cpld vbank with SW3[5:7]=000 as default vbank0 instead of
  previous SW3[5:7]=111 as default vbank.
- fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Shengzhou Liu 2014-04-18 16:43:41 +08:00 committed by York Sun
parent 4d66668300
commit ef531c7357
4 changed files with 15 additions and 10 deletions
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6
board/freescale/t208xrdb/README
View file

@ -67,7 +67,7 @@ T2080PCIe-RDB board Overview
- One PCIe x2 end-point device (C293 Crypto co-processor) - One PCIe x2 end-point device (C293 Crypto co-processor)
- IFC/Local Bus - IFC/Local Bus
- NOR: 128MB 16-bit NOR Flash - NOR: 128MB 16-bit NOR Flash
- NAND: 512MB 8-bit NAND flash - NAND: 1GB 8-bit NAND flash
- CPLD: for system controlling with programable header on-board - CPLD: for system controlling with programable header on-board
- SATA - SATA
- Two SATA 2.0 onnectors on-board - Two SATA 2.0 onnectors on-board
@ -156,11 +156,11 @@ Software configurations and board settings
Switching between default bank and alternate bank on NOR flash Switching between default bank and alternate bank on NOR flash
To change boot source to vbank4: To change boot source to vbank4:
via software: run command 'cpld reset altbank' in u-boot. via software: run command 'cpld reset altbank' in u-boot.
via DIP-switch: set SW3[5:7] = '011' via DIP-switch: set SW3[5:7] = '100'
To change boot source to vbank0: To change boot source to vbank0:
via software: run command 'cpld reset' in u-boot. via software: run command 'cpld reset' in u-boot.
via DIP-Switch: set SW3[5:7] = '111' via DIP-Switch: set SW3[5:7] = '000'
2. NAND Boot: 2. NAND Boot:
a. build PBL image for NAND boot a. build PBL image for NAND boot

4
board/freescale/t208xrdb/cpld.h
View file

@ -35,8 +35,8 @@ void cpld_write(unsigned int reg, u8 value);
#define CPLD_LBMAP_MASK 0x3F #define CPLD_LBMAP_MASK 0x3F
#define CPLD_BANK_SEL_MASK 0x07 #define CPLD_BANK_SEL_MASK 0x07
#define CPLD_BANK_OVERRIDE 0x40 #define CPLD_BANK_OVERRIDE 0x40
#define CPLD_LBMAP_ALTBANK 0x43 /* BANK OR | BANK 4 */ #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
#define CPLD_LBMAP_DFLTBANK 0x47 /* BANK OR | BANK 0 */ #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
#define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03 #define CPLD_LBMAP_SHIFT 0x03
#define CPLD_BOOT_SEL 0x80 #define CPLD_BOOT_SEL 0x80

2
board/freescale/t208xrdb/t208xrdb.c
View file

@ -44,7 +44,7 @@ int checkboard(void)
puts("NAND\n"); puts("NAND\n");
} else { } else {
reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
printf("NOR vBank%d\n", ~reg & 0x7); printf("NOR vBank%d\n", reg);
} }
#endif #endif

13
include/configs/T208xRDB.h
View file

@ -208,7 +208,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0 #define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/* /*
* DDR Setup * DDR Setup
@ -584,7 +584,8 @@ unsigned long get_board_ddr_clk(void);
* env, so we got 0x110000. * env, so we got 0x110000.
*/ */
#define CONFIG_SYS_QE_FW_IN_SPIFLASH #define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
#define CONFIG_CORTINA_FW_ADDR 0x120000 #define CONFIG_CORTINA_FW_ADDR 0x120000
#elif defined(CONFIG_SDCARD) #elif defined(CONFIG_SDCARD)
@ -594,11 +595,13 @@ unsigned long get_board_ddr_clk(void);
* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
*/ */
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_CORTINA_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
#define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
#elif defined(CONFIG_NAND) #elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_CORTINA_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
@ -610,11 +613,13 @@ unsigned long get_board_ddr_clk(void);
* master LAW->the ucode address in master's memory space. * master LAW->the ucode address in master's memory space.
*/ */
#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
#define CONFIG_CORTINA_FW_ADDR 0xFFE10000 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000
#else #else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #define CONFIG_SYS_CORTINA_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#define CONFIG_CORTINA_FW_ADDR 0xEFE00000 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000
#endif #endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000