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https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
highbank: add custom ahci_link_up function
The Calxeda highbank SOC needs a custom sequence to bring up SATA links, so override ahci_link_up with custom function to handle combophy setup. Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com> Signed-off-by: Richard Gibbs Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Andre Przywara <osp@andrep.de>
This commit is contained in:
Mark Langsdorf
Tom Rini
parent
f8b009e8b7
commit
ef51c416bc
3 changed files with 231 additions and 1 deletions
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@ -5,4 +5,4 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := highbank.o
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obj-y := highbank.o ahci.o
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218
board/highbank/ahci.c
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218
board/highbank/ahci.c
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@ -0,0 +1,218 @@
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/*
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* Copyright 2012 Calxeda, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <ahci.h>
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#include <asm/io.h>
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#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
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#define CPHY_ADDR(base, dev, addr) ((base) | (((addr) & 0x1ff) << 2))
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#define CPHY_BASE 0xfff58000
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#define CPHY_WIDTH 0x1000
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#define CPHY_DTE_XS 5
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#define CPHY_MII 31
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#define SERDES_CR_CTL 0x80a0
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#define SERDES_CR_ADDR 0x80a1
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#define SERDES_CR_DATA 0x80a2
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#define CR_BUSY 0x0001
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#define CR_START 0x0001
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#define CR_WR_RDN 0x0002
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#define CPHY_TX_INPUT_STS 0x2001
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#define CPHY_RX_INPUT_STS 0x2002
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#define CPHY_SATA_TX_OVERRIDE_BIT 0x8000
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#define CPHY_SATA_RX_OVERRIDE_BIT 0x4000
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#define CPHY_TX_INPUT_OVERRIDE 0x2004
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#define CPHY_RX_INPUT_OVERRIDE 0x2005
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#define SPHY_LANE 0x100
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#define SPHY_HALF_RATE 0x0001
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#define CPHY_SATA_DPLL_MODE 0x0700
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#define CPHY_SATA_DPLL_SHIFT 8
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#define CPHY_SATA_TX_ATTEN 0x1c00
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#define CPHY_SATA_TX_ATTEN_SHIFT 10
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#define HB_SREG_SATA_ATTEN 0xfff3cf24
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#define SATA_PORT_BASE 0xffe08000
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#define SATA_VERSIONR 0xf8
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#define SATA_HB_VERSION 0x3332302a
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static u32 __combo_phy_reg_read(u8 phy, u8 dev, u32 addr)
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{
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u32 data;
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writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
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data = readl(CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
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return data;
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}
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static void __combo_phy_reg_write(u8 phy, u8 dev, u32 addr, u32 data)
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{
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writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);
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writel(data, CPHY_ADDR(CPHY_BASE + CPHY_WIDTH * phy, dev, addr));
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}
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static u32 combo_phy_read(u8 phy, u32 addr)
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{
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u8 dev = CPHY_DTE_XS;
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if (phy == 5)
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dev = CPHY_MII;
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while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
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udelay(5);
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__combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
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__combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_START);
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while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
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udelay(5);
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return __combo_phy_reg_read(phy, dev, SERDES_CR_DATA);
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}
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static void combo_phy_write(u8 phy, u32 addr, u32 data)
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{
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u8 dev = CPHY_DTE_XS;
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if (phy == 5)
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dev = CPHY_MII;
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while (__combo_phy_reg_read(phy, dev, SERDES_CR_CTL) & CR_BUSY)
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udelay(5);
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__combo_phy_reg_write(phy, dev, SERDES_CR_ADDR, addr);
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__combo_phy_reg_write(phy, dev, SERDES_CR_DATA, data);
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__combo_phy_reg_write(phy, dev, SERDES_CR_CTL, CR_WR_RDN | CR_START);
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}
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static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val)
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{
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u32 tmp;
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tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
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tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
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combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
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tmp |= CPHY_SATA_RX_OVERRIDE_BIT;
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combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
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tmp &= ~CPHY_SATA_DPLL_MODE;
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tmp |= (val << CPHY_SATA_DPLL_SHIFT) & CPHY_SATA_DPLL_MODE;
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combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
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}
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static void cphy_tx_attenuation_override(u8 phy, u8 lane)
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{
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u32 val;
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u32 tmp;
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u8 shift;
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shift = ((phy == 5) ? 4 : lane) * 4;
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val = (readl(HB_SREG_SATA_ATTEN) >> shift) & 0xf;
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if (val & 0x8)
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return;
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tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE);
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tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
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combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
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tmp |= CPHY_SATA_TX_OVERRIDE_BIT;
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combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
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tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN;
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combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
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}
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static void cphy_disable_port_overrides(u8 port)
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{
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u32 tmp;
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u8 lane = 0, phy = 0;
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if (port == 0)
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phy = 5;
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else if (port < 5)
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lane = port - 1;
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else
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return;
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tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
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tmp &= ~CPHY_SATA_RX_OVERRIDE_BIT;
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combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
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tmp = combo_phy_read(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE);
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tmp &= ~CPHY_SATA_TX_OVERRIDE_BIT;
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combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp);
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}
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void cphy_disable_overrides(void)
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{
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int i;
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u32 port_map;
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port_map = readl(0xffe08000 + HOST_PORTS_IMPL);
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for (i = 0; i < 5; i++) {
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if (port_map & (1 << i))
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cphy_disable_port_overrides(i);
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}
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}
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static void cphy_override_lane(u8 port)
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{
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u32 tmp, k = 0;
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u8 lane = 0, phy = 0;
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if (port == 0)
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phy = 5;
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else if (port < 5)
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lane = port - 1;
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else
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return;
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do {
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tmp = combo_phy_read(0, CPHY_RX_INPUT_STS +
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lane * SPHY_LANE);
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} while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
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cphy_spread_spectrum_override(phy, lane, 3);
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cphy_tx_attenuation_override(phy, lane);
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}
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#define WAIT_MS_LINKUP 4
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int ahci_link_up(struct ahci_probe_ent *probe_ent, int port)
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{
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u32 tmp;
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int j = 0;
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u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
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u32 is_highbank = readl(SATA_PORT_BASE + SATA_VERSIONR) ==
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SATA_HB_VERSION ? 1 : 0;
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/* Bring up SATA link.
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* SATA link bringup time is usually less than 1 ms; only very
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* rarely has it taken between 1-2 ms. Never seen it above 2 ms.
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*/
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while (j < WAIT_MS_LINKUP) {
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if (is_highbank && (j == 0)) {
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cphy_disable_port_overrides(port);
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writel(0x301, port_mmio + PORT_SCR_CTL);
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udelay(1000);
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writel(0x300, port_mmio + PORT_SCR_CTL);
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udelay(1000);
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cphy_override_lane(port);
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}
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tmp = readl(port_mmio + PORT_SCR_STAT);
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if ((tmp & 0xf) == 0x3)
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return 0;
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udelay(1000);
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j++;
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if ((j == WAIT_MS_LINKUP) && (tmp & 0xf))
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j = 0; /* retry phy reset */
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}
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return 1;
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}
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@ -35,6 +35,8 @@
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DECLARE_GLOBAL_DATA_PTR;
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void cphy_disable_overrides(void);
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/*
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* Miscellaneous platform dependent initialisations
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*/
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@ -62,6 +64,7 @@ void scsi_init(void)
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{
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u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
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cphy_disable_overrides();
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if (reg & PWRDOM_STAT_SATA) {
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ahci_init((void __iomem *)HB_AHCI_BASE);
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scsi_scan(1);
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@ -136,3 +139,12 @@ void reset_cpu(ulong addr)
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wfi();
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}
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/*
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* turn off the override before transferring control to Linux, since Linux
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* may not support spread spectrum.
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*/
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void arch_preboot_os(void)
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{
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cphy_disable_overrides();
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}
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