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Merge git://git.denx.de/u-boot into u-boot

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Ben Warren 2009-01-24 20:44:56 -08:00
commit ef29884b27
414 changed files with 15334 additions and 3911 deletions
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3544
CHANGELOG
View file

File diff suppressed because it is too large Load diff

12
MAINTAINERS
View file

@ -263,6 +263,10 @@ Jon Loeliger <jdl@freescale.com>
MPC8641HPCN MPC8641D
Ron Madrid <info@sheldoninst.com>
SIMPC8313 MPC8313
Dan Malek <dan@embeddedalley.com>
stxgp3 MPC85xx
@ -374,6 +378,7 @@ Heiko Schocher <hs@denx.de>
ids8247 MPC8247
jupiter MPC5200
kmeter1 MPC8360
mgcoge MPC8247
mgsuvd MPC852
mucmc52 MPC5200
@ -411,6 +416,10 @@ Rune Torgersen <runet@innovsys.com>
MPC8266ADS MPC8266
Peter Tyser <ptyser@xes-inc.com>
XPEDITE5200 MPC8548
XPEDITE5370 MPC8572
David Updegraff <dave@cray.com>
@ -703,8 +712,7 @@ Yasushi Shoji <yashi@atmark-techno.com>
Michal Simek <monstr@monstr.eu>
ML401 MicroBlaze
XUPV2P MicroBlaze
microblaze-generic MicroBlaze
#########################################################################
# Coldfire Systems: #

13
MAKEALL
View file

@ -335,6 +335,7 @@ LIST_8260=" \
#########################################################################
LIST_83xx=" \
kmeter1 \
MPC8313ERDB_33 \
MPC8313ERDB_NAND_66 \
MPC8315ERDB \
@ -352,6 +353,7 @@ LIST_83xx=" \
MPC837XERDB \
MVBLM7 \
sbc8349 \
SIMPC8313_LP \
TQM834x \
"
@ -372,6 +374,7 @@ LIST_85xx=" \
MPC8560ADS \
MPC8568MDS \
MPC8572DS \
MPC8572DS_36BIT \
PM854 \
PM856 \
sbc8540 \
@ -385,6 +388,8 @@ LIST_85xx=" \
TQM8548 \
TQM8555 \
TQM8560 \
XPEDITE5200 \
XPEDITE5370 \
"
#########################################################################
@ -656,6 +661,7 @@ LIST_mips_el=" \
LIST_I486=" \
sc520_cdp \
sc520_eNET \
sc520_spunk \
sc520_spunk_rel \
"
@ -695,10 +701,9 @@ LIST_nios2=" \
## MicroBlaze Systems
#########################################################################
LIST_microblaze=" \
ml401 \
suzaku \
xupv2p \
LIST_microblaze=" \
microblaze-generic \
suzaku \
"
#########################################################################

98
Makefile
View file

@ -21,8 +21,8 @@
# MA 02111-1307 USA
#
VERSION = 2008
PATCHLEVEL = 10
VERSION = 2009
PATCHLEVEL = 01
SUBLEVEL =
EXTRAVERSION =
ifneq "$(SUBLEVEL)" ""
@ -197,7 +197,7 @@ include $(TOPDIR)/config.mk
OBJS = cpu/$(CPU)/start.o
ifeq ($(CPU),i386)
OBJS += cpu/$(CPU)/start16.o
OBJS += cpu/$(CPU)/reset.o
OBJS += cpu/$(CPU)/resetvec.o
endif
ifeq ($(CPU),ppc4xx)
OBJS += cpu/$(CPU)/resetvec.o
@ -228,6 +228,7 @@ LIBS += drivers/bios_emulator/libatibiosemu.a
LIBS += drivers/block/libblock.a
LIBS += drivers/dma/libdma.a
LIBS += drivers/fpga/libfpga.a
LIBS += drivers/gpio/libgpio.a
LIBS += drivers/hwmon/libhwmon.a
LIBS += drivers/i2c/libi2c.a
LIBS += drivers/input/libinput.a
@ -347,7 +348,7 @@ $(obj)u-boot: depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT)
$(OBJS): depend $(obj)include/autoconf.mk
$(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@))
$(LIBS): depend $(obj)include/autoconf.mk
$(LIBS): depend $(obj)include/autoconf.mk $(SUBDIRS)
$(MAKE) -C $(dir $(subst $(obj),,$@))
$(LIBBOARD): depend $(LIBS) $(obj)include/autoconf.mk
@ -407,6 +408,7 @@ TAG_SUBDIRS += disk
TAG_SUBDIRS += common
TAG_SUBDIRS += drivers/bios_emulator
TAG_SUBDIRS += drivers/block
TAG_SUBDIRS += drivers/gpio
TAG_SUBDIRS += drivers/hwmon
TAG_SUBDIRS += drivers/i2c
TAG_SUBDIRS += drivers/input
@ -463,7 +465,8 @@ $(obj)include/autoconf.mk: $(obj)include/config.h
set -e ; \
: Extract the config macros ; \
$(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h | \
sed -n -f tools/scripts/define2mk.sed > $@
sed -n -f tools/scripts/define2mk.sed > $@.tmp && \
mv $@.tmp $@
sinclude $(obj)include/autoconf.mk.dep
@ -1261,14 +1264,11 @@ CMS700_config: unconfig
CPCI2DP_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd
CPCI405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
CPCI405_config \
CPCI4052_config \
CPCI405DT_config \
CPCI405AB_config: unconfig
@mkdir -p $(obj)board/esd/cpci405
@echo "TEXT_BASE = 0xFFFC0000" > $(obj)board/esd/cpci405/config.tmp
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
CPCIISER4_config: unconfig
@ -2186,6 +2186,9 @@ TASREG_config : unconfig
## MPC83xx Systems
#########################################################################
kmeter1_config: unconfig
@$(MKCONFIG) kmeter1 ppc mpc83xx kmeter1 keymile
MPC8313ERDB_33_config \
MPC8313ERDB_66_config \
MPC8313ERDB_NAND_33_config \
@ -2325,6 +2328,21 @@ MVBLM7_config: unconfig
sbc8349_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
SIMPC8313_LP_config \
SIMPC8313_SP_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/sheldon/simpc8313
@if [ "$(findstring _LP_,$@)" ] ; then \
$(XECHO) -n "...Large Page NAND..." ; \
echo "#define CONFIG_NAND_LP" >> $(obj)include/config.h ; \
fi ; \
if [ "$(findstring _SP_,$@)" ] ; then \
$(XECHO) -n "...Small Page NAND..." ; \
echo "#define CONFIG_NAND_SP" >> $(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a SIMPC8313 ppc mpc83xx simpc8313 sheldon
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
TQM834x_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc
@ -2398,8 +2416,14 @@ MPC8555CDS_config: unconfig
MPC8568MDS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale
MPC8572DS_36BIT_config \
MPC8572DS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8572ds freescale
@mkdir -p $(obj)include
@if [ "$(findstring _36BIT_,$@)" ] ; then \
echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
$(XECHO) "... enabling 36-bit physical addressing." ; \
fi
@$(MKCONFIG) -a MPC8572DS ppc mpc85xx mpc8572ds freescale
PM854_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
@ -2463,6 +2487,12 @@ TQM8560_config: unconfig
echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h;
@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc
XPEDITE5200_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5200 xes
XPEDITE5370_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5370 xes
#########################################################################
## MPC86xx Systems
#########################################################################
@ -2596,6 +2626,7 @@ at91sam9260ek_nandflash_config \
at91sam9260ek_dataflash_cs0_config \
at91sam9260ek_dataflash_cs1_config \
at91sam9260ek_config : unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _nandflash,$@)" ] ; then \
echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
$(XECHO) "... with environment variable in NAND FLASH" ; \
@ -2608,10 +2639,28 @@ at91sam9260ek_config : unconfig
fi;
@$(MKCONFIG) -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91
at91sam9xeek_nandflash_config \
at91sam9xeek_dataflash_cs0_config \
at91sam9xeek_dataflash_cs1_config \
at91sam9xeek_config : unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _nandflash,$@)" ] ; then \
echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
$(XECHO) "... with environment variable in NAND FLASH" ; \
elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1" >>$(obj)include/config.h ; \
$(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
else \
echo "#define CONFIG_SYS_USE_DATAFLASH_CS1 1" >>$(obj)include/config.h ; \
$(XECHO) "... with environment variable in SPI DATAFLASH CS1" ; \
fi;
@$(MKCONFIG) -n at91sam9xeek -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91sam9
at91sam9261ek_nandflash_config \
at91sam9261ek_dataflash_cs0_config \
at91sam9261ek_dataflash_cs3_config \
at91sam9261ek_config : unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _nandflash,$@)" ] ; then \
echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
$(XECHO) "... with environment variable in NAND FLASH" ; \
@ -2628,6 +2677,7 @@ at91sam9263ek_nandflash_config \
at91sam9263ek_dataflash_config \
at91sam9263ek_dataflash_cs0_config \
at91sam9263ek_config : unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _nandflash,$@)" ] ; then \
echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
$(XECHO) "... with environment variable in NAND FLASH" ; \
@ -2641,6 +2691,7 @@ at91sam9rlek_nandflash_config \
at91sam9rlek_dataflash_config \
at91sam9rlek_dataflash_cs0_config \
at91sam9rlek_config : unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _nandflash,$@)" ] ; then \
echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
$(XECHO) "... with environment variable in NAND FLASH" ; \
@ -2963,14 +3014,17 @@ smdk6400_config : unconfig
#########################################################################
## AMD SC520 CDP
#########################################################################
eNET_config : unconfig
@$(MKCONFIG) $(@:_config=) i386 i386 eNET NULL sc520
sc520_cdp_config : unconfig
@$(MKCONFIG) $(@:_config=) i386 i386 sc520_cdp
@$(MKCONFIG) $(@:_config=) i386 i386 sc520_cdp NULL sc520
sc520_spunk_config : unconfig
@$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk
@$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk NULL sc520
sc520_spunk_rel_config : unconfig
@$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk
@$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk NULL sc520
#========================================================================
# MIPS
@ -3143,21 +3197,15 @@ PCI5441_config : unconfig
## Microblaze
#========================================================================
ml401_config: unconfig
microblaze-generic_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_ML401 1" > $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) microblaze microblaze ml401 xilinx
@$(MKCONFIG) -a $(@:_config=) microblaze microblaze microblaze-generic xilinx
suzaku_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_SUZAKU 1" > $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno
xupv2p_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_XUPV2P 1" > $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) microblaze microblaze xupv2p xilinx
#========================================================================
# Blackfin
#========================================================================
@ -3208,9 +3256,9 @@ mimc200_config : unconfig
## sh2 (Renesas SuperH)
#########################################################################
rsk7203_config: unconfig
@ >include/config.h
@echo "#define CONFIG_RSK7203 1" >> include/config.h
@./mkconfig -a $(@:_config=) sh sh2 rsk7203 renesas
@mkdir -p $(obj)include
@echo "#define CONFIG_RSK7203 1" > $(obj)/include/config.h
@$(MKCONFIG) -a $(@:_config=) sh sh2 rsk7203 renesas
#########################################################################
## sh3 (Renesas SuperH)
@ -3233,7 +3281,7 @@ ms7720se_config: unconfig
MigoR_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_MIGO_R 1" > $(obj)include/config.h
@./mkconfig -a $(@:_config=) sh sh4 MigoR renesas
@$(MKCONFIG) -a $(@:_config=) sh sh4 MigoR renesas
ms7750se_config: unconfig
@mkdir -p $(obj)include

30
README
View file

@ -592,6 +592,10 @@ The following options need to be configured:
CONFIG_CMD_DHCP * DHCP support
CONFIG_CMD_DIAG * Diagnostics
CONFIG_CMD_DOC * Disk-On-Chip Support
CONFIG_CMD_DS4510 * ds4510 I2C gpio commands
CONFIG_CMD_DS4510_INFO * ds4510 I2C info command
CONFIG_CMD_DS4510_MEM * ds4510 I2C eeprom/sram commansd
CONFIG_CMD_DS4510_RST * ds4510 I2C rst command
CONFIG_CMD_DTT * Digital Therm and Thermostat
CONFIG_CMD_ECHO echo arguments
CONFIG_CMD_EEPROM * EEPROM read/write support
@ -621,6 +625,8 @@ The following options need to be configured:
CONFIG_CMD_MII * MII utility commands
CONFIG_CMD_NAND * NAND support
CONFIG_CMD_NET bootp, tftpboot, rarpboot
CONFIG_CMD_PCA953X * PCA953x I2C gpio commands
CONFIG_CMD_PCA953X_INFO * PCA953x I2C gpio info command
CONFIG_CMD_PCI * pciinfo
CONFIG_CMD_PCMCIA * PCMCIA support
CONFIG_CMD_PING * send ICMP ECHO_REQUEST to network
@ -698,6 +704,13 @@ The following options need to be configured:
Note that if the RTC uses I2C, then the I2C interface
must also be configured. See I2C Support, below.
- GPIO Support:
CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO
CONFIG_PCA953X_INFO - enable pca953x info command
Note that if the GPIO device uses I2C, then the I2C interface
must also be configured. See I2C Support, below.
- Timestamp Support:
When CONFIG_TIMESTAMP is selected, the timestamp
@ -3731,7 +3744,7 @@ MPC826x processors), on others (parts of) the data cache can be
locked as (mis-) used as memory, etc.
Chris Hallinan posted a good summary of these issues to the
u-boot-users mailing list:
U-Boot mailing list:
Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)?
From: "Chris Hallinan" <clh@net1plus.com>
@ -3941,7 +3954,7 @@ int main (int argc, char *argv[])
Download latest U-Boot source;
Subscribe to u-boot-users mailing list;
Subscribe to u-boot mailing list;
if (clueless) {
email ("Hi, I am new to U-Boot, how do I get started?");
@ -4018,10 +4031,11 @@ Since the number of patches for U-Boot is growing, we need to
establish some rules. Submissions which do not conform to these rules
may be rejected, even when they contain important and valuable stuff.
Patches shall be sent to the u-boot-users mailing list.
Please see http://www.denx.de/wiki/U-Boot/Patches for details.
Patches shall be sent to the u-boot mailing list <u-boot@lists.denx.de>;
see http://lists.denx.de/mailman/listinfo/u-boot
When you send a patch, please include the following information with
it:
@ -4084,7 +4098,7 @@ Notes:
disabled must not need more memory than the old code without your
modification.
* Remember that there is a size limit of 40 kB per message on the
u-boot-users mailing list. Bigger patches will be moderated. If
they are reasonable and not bigger than 100 kB, they will be
acknowledged. Even bigger patches should be avoided.
* Remember that there is a size limit of 100 kB per message on the
u-boot mailing list. Bigger patches will be moderated. If they are
reasonable and not too big, they will be acknowledged. But patches
bigger than the size limit should be avoided.

1
board/afeb9260/partition.c
View file

@ -34,4 +34,3 @@ dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
{0x00008400, 0x00041FFF, FLAG_PROTECT_CLEAR, 0, "U-Boot"},
};

7
board/bf533-ezkit/Makefile
View file

@ -35,12 +35,11 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
u-boot.lds: u-boot.lds.S
$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
mv -f $@.tmp $@
$(obj)u-boot.lds: u-boot.lds.S
$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
clean:
rm -f $(SOBJS) $(OBJS)

8
board/bf533-ezkit/config.mk
View file

@ -1,4 +1,6 @@
#
# Copyright (c) 2005-2008 Analog Device Inc.
#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
@ -23,3 +25,9 @@
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))

23
board/bf533-ezkit/u-boot.lds.S
View file

@ -28,6 +28,8 @@
#include <config.h>
#include <asm/blackfin.h>
#undef ALIGN
#undef ENTRY
#undef bfin
/* If we don't actually load anything into L1 data, this will avoid
* a syntax error. If we do actually load something into L1 data,
@ -50,11 +52,12 @@ MEMORY
l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
ENTRY(_start)
SECTIONS
{
.text :
{
cpu/blackfin/start.o (.text)
cpu/blackfin/start.o (.text .text.*)
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
@ -63,20 +66,20 @@ SECTIONS
* it linked after the configuration sector.
*/
cpu/blackfin/traps.o (.text)
cpu/blackfin/interrupt.o (.text)
cpu/blackfin/serial.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
board/bf533-ezkit/bf533-ezkit.o (.text)
cpu/blackfin/traps.o (.text .text.*)
cpu/blackfin/interrupt.o (.text .text.*)
cpu/blackfin/serial.o (.text .text.*)
common/dlmalloc.o (.text .text.*)
lib_generic/crc32.o (.text .text.*)
lib_generic/zlib.o (.text .text.*)
board/bf533-ezkit/bf533-ezkit.o (.text .text.*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
common/env_embedded.o (.text .text.*)
#endif
__initcode_start = .;
cpu/blackfin/initcode.o (.text)
cpu/blackfin/initcode.o (.text .text.*)
__initcode_end = .;
*(.text .text.*)

7
board/bf533-stamp/Makefile
View file

@ -35,12 +35,11 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
u-boot.lds: u-boot.lds.S
$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
mv -f $@.tmp $@
$(obj)u-boot.lds: u-boot.lds.S
$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
clean:
rm -f $(SOBJS) $(OBJS)

8
board/bf533-stamp/config.mk
View file

@ -1,4 +1,6 @@
#
# Copyright (c) 2005-2008 Analog Device Inc.
#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
@ -23,3 +25,9 @@
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))

19
board/bf533-stamp/u-boot.lds.S
View file

@ -28,6 +28,8 @@
#include <config.h>
#include <asm/blackfin.h>
#undef ALIGN
#undef ENTRY
#undef bfin
/* If we don't actually load anything into L1 data, this will avoid
* a syntax error. If we do actually load something into L1 data,
@ -50,11 +52,12 @@ MEMORY
l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
ENTRY(_start)
SECTIONS
{
.text :
{
cpu/blackfin/start.o (.text)
cpu/blackfin/start.o (.text .text.*)
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
@ -63,18 +66,18 @@ SECTIONS
* it linked after the configuration sector.
*/
cpu/blackfin/traps.o (.text)
cpu/blackfin/interrupt.o (.text)
cpu/blackfin/serial.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
cpu/blackfin/traps.o (.text .text.*)
cpu/blackfin/interrupt.o (.text .text.*)
cpu/blackfin/serial.o (.text .text.*)
common/dlmalloc.o (.text .text.*)
lib_generic/crc32.o (.text .text.*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
common/env_embedded.o (.text .text.*)
#endif
__initcode_start = .;
cpu/blackfin/initcode.o (.text)
cpu/blackfin/initcode.o (.text .text.*)
__initcode_end = .;
*(.text .text.*)

7
board/bf537-stamp/Makefile
View file

@ -35,12 +35,11 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
u-boot.lds: u-boot.lds.S
$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
mv -f $@.tmp $@
$(obj)u-boot.lds: u-boot.lds.S
$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
clean:
rm -f $(SOBJS) $(OBJS)

7
board/bf537-stamp/config.mk
View file

@ -1,4 +1,6 @@
#
# Copyright (c) 2005-2008 Analog Device Inc.
#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
@ -24,6 +26,9 @@
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))

4
board/bf537-stamp/nand.c
View file

@ -87,7 +87,7 @@ int bfin_device_ready(struct mtd_info *mtd)
* Members with a "?" were not set in the merged testing-NAND branch,
* so they are not set here either.
*/
void board_nand_init(struct nand_chip *nand)
int board_nand_init(struct nand_chip *nand)
{
*PORT(CONFIG_NAND_GPIO_PORT, _FER) &= ~BFIN_NAND_READY;
*PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) &= ~BFIN_NAND_READY;
@ -97,5 +97,7 @@ void board_nand_init(struct nand_chip *nand)
nand->ecc.mode = NAND_ECC_SOFT;
nand->dev_ready = bfin_device_ready;
nand->chip_delay = 30;
return 0;
}
#endif

19
board/bf537-stamp/u-boot.lds.S
View file

@ -28,6 +28,8 @@
#include <config.h>
#include <asm/blackfin.h>
#undef ALIGN
#undef ENTRY
#undef bfin
/* If we don't actually load anything into L1 data, this will avoid
* a syntax error. If we do actually load something into L1 data,
@ -50,11 +52,12 @@ MEMORY
l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
ENTRY(_start)
SECTIONS
{
.text :
{
cpu/blackfin/start.o (.text)
cpu/blackfin/start.o (.text .text.*)
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
@ -63,18 +66,18 @@ SECTIONS
* it linked after the configuration sector.
*/
cpu/blackfin/traps.o (.text)
cpu/blackfin/interrupt.o (.text)
cpu/blackfin/serial.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
cpu/blackfin/traps.o (.text .text.*)
cpu/blackfin/interrupt.o (.text .text.*)
cpu/blackfin/serial.o (.text .text.*)
common/dlmalloc.o (.text .text.*)
lib_generic/crc32.o (.text .text.*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
common/env_embedded.o (.text .text.*)
#endif
__initcode_start = .;
cpu/blackfin/initcode.o (.text)
cpu/blackfin/initcode.o (.text .text.*)
__initcode_end = .;
*(.text .text.*)

7
board/bf561-ezkit/Makefile
View file

@ -35,12 +35,11 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
u-boot.lds: u-boot.lds.S
$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
mv -f $@.tmp $@
$(obj)u-boot.lds: u-boot.lds.S
$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
clean:
rm -f $(SOBJS) $(OBJS)

8
board/bf561-ezkit/config.mk
View file

@ -1,4 +1,6 @@
#
# Copyright (c) 2005-2008 Analog Device Inc.
#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
@ -23,3 +25,9 @@
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
# Set some default LDR flags based on boot mode.
LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))

23
board/bf561-ezkit/u-boot.lds.S
View file

@ -28,6 +28,8 @@
#include <config.h>
#include <asm/blackfin.h>
#undef ALIGN
#undef ENTRY
#undef bfin
/* If we don't actually load anything into L1 data, this will avoid
* a syntax error. If we do actually load something into L1 data,
@ -50,11 +52,12 @@ MEMORY
l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
ENTRY(_start)
SECTIONS
{
.text :
{
cpu/blackfin/start.o (.text)
cpu/blackfin/start.o (.text .text.*)
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
@ -63,20 +66,20 @@ SECTIONS
* it linked after the configuration sector.
*/
cpu/blackfin/traps.o (.text)
cpu/blackfin/interrupt.o (.text)
cpu/blackfin/serial.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
board/bf561-ezkit/bf561-ezkit.o (.text)
cpu/blackfin/traps.o (.text .text.*)
cpu/blackfin/interrupt.o (.text .text.*)
cpu/blackfin/serial.o (.text .text.*)
common/dlmalloc.o (.text .text.*)
lib_generic/crc32.o (.text .text.*)
lib_generic/zlib.o (.text .text.*)
board/bf561-ezkit/bf561-ezkit.o (.text .text.*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
common/env_embedded.o (.text .text.*)
#endif
__initcode_start = .;
cpu/blackfin/initcode.o (.text)
cpu/blackfin/initcode.o (.text .text.*)
__initcode_end = .;
*(.text .text.*)

57
board/eNET/Makefile Normal file
View file

@ -0,0 +1,57 @@
#
# (C) Copyright 2008
# Graeme Russ, graeme.russ@gmail.com.
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2002
# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := eNET.o
SOBJS := eNET_start16.o eNET_start.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

16
board/xilinx/xupv2p/config.mk → board/eNET/config.mk
View file

@ -1,7 +1,6 @@
#
# (C) Copyright 2007 Michal Simek
#
# Michal SIMEK <monstr@monstr.eu>
# (C) Copyright 2002
# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
#
# See file CREDITS for list of people who contributed to this
# project.
@ -13,7 +12,7 @@
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
@ -21,12 +20,5 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# CAUTION: This file is automatically generated by libgen.
# Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
#
TEXT_BASE = 0x38000000
PLATFORM_CPPFLAGS += -mno-xl-soft-mul
PLATFORM_CPPFLAGS += -mno-xl-soft-div
PLATFORM_CPPFLAGS += -mxl-barrel-shift
TEXT_BASE = 0x38040000

167
board/eNET/eNET.c Normal file
View file

@ -0,0 +1,167 @@
/*
* (C) Copyright 2008
* Graeme Russ, graeme.russ@gmail.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/ic/sc520.h>
#ifdef CONFIG_HW_WATCHDOG
#include <watchdog.h>
#endif
#include "hardware.h"
DECLARE_GLOBAL_DATA_PTR;
#undef SC520_CDP_DEBUG
#ifdef SC520_CDP_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
void init_sc520_enet (void)
{
/* Set CPU Speed to 100MHz */
write_mmcr_byte(SC520_CPUCTL, 1);
gd->cpu_clk = 100000000;
/* wait at least one millisecond */
asm("movl $0x2000,%%ecx\n"
"wait_loop: pushl %%ecx\n"
"popl %%ecx\n"
"loop wait_loop\n": : : "ecx");
/* turn on the SDRAM write buffer */
write_mmcr_byte(SC520_DBCTL, 0x11);
/* turn on the cache and disable write through */
asm("movl %%cr0, %%eax\n"
"andl $0x9fffffff, %%eax\n"
"movl %%eax, %%cr0\n" : : : "eax");
}
/*
* Miscellaneous platform dependent initializations
*/
int board_init(void)
{
init_sc520_enet();
write_mmcr_byte(SC520_GPCSRT, 0x01); /* GP Chip Select Recovery Time */
write_mmcr_byte(SC520_GPCSPW, 0x07); /* GP Chip Select Pulse Width */
write_mmcr_byte(SC520_GPCSOFF, 0x00); /* GP Chip Select Offset */
write_mmcr_byte(SC520_GPRDW, 0x05); /* GP Read pulse width */
write_mmcr_byte(SC520_GPRDOFF, 0x01); /* GP Read offset */
write_mmcr_byte(SC520_GPWRW, 0x05); /* GP Write pulse width */
write_mmcr_byte(SC520_GPWROFF, 0x01); /* GP Write offset */
write_mmcr_word(SC520_PIODATA15_0, 0x0630); /* PIO15_PIO0 Data */
write_mmcr_word(SC520_PIODATA31_16, 0x2000); /* PIO31_PIO16 Data */
write_mmcr_word(SC520_PIODIR31_16, 0x2000); /* GPIO Direction */
write_mmcr_word(SC520_PIODIR15_0, 0x87b5); /* GPIO Direction */
write_mmcr_word(SC520_PIOPFS31_16, 0x0dfe); /* GPIO pin function 31-16 reg */
write_mmcr_word(SC520_PIOPFS15_0, 0x200a); /* GPIO pin function 15-0 reg */
write_mmcr_byte(SC520_CSPFS, 0x00f8); /* Chip Select Pin Function Select */
write_mmcr_long(SC520_PAR2, 0x200713f8); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
write_mmcr_long(SC520_PAR3, 0x2c0712f8); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
write_mmcr_long(SC520_PAR4, 0x300711f8); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
write_mmcr_long(SC520_PAR5, 0x340710f8); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
write_mmcr_long(SC520_PAR6, 0xe3ffc000); /* SDRAM (0x00000000, 128MB) */
write_mmcr_long(SC520_PAR7, 0xaa3fd000); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
write_mmcr_long(SC520_PAR8, 0xca3fd100); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
write_mmcr_long(SC520_PAR9, 0x4203d900); /* SRAM (GPCS0, 0x19000000, 1MB) */
write_mmcr_long(SC520_PAR10, 0x4e03d910); /* SRAM (GPCS3, 0x19100000, 1MB) */
write_mmcr_long(SC520_PAR11, 0x50018100); /* DP-RAM (GPCS4, 0x18100000, 4kB) */
write_mmcr_long(SC520_PAR12, 0x54020000); /* CFLASH1 (0x200000000, 4kB) */
write_mmcr_long(SC520_PAR13, 0x5c020001); /* CFLASH2 (0x200010000, 4kB) */
/* write_mmcr_long(SC520_PAR14, 0x8bfff800); */ /* BOOTCS at 0x18000000 */
/* write_mmcr_long(SC520_PAR15, 0x38201000); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
/* Disable Watchdog */
write_mmcr_word(0x0cb0, 0x3333);
write_mmcr_word(0x0cb0, 0xcccc);
write_mmcr_word(0x0cb0, 0x0000);
/* Chip Select Configuration */
write_mmcr_word(SC520_BOOTCSCTL, 0x0033);
write_mmcr_word(SC520_ROMCS1CTL, 0x0615);
write_mmcr_word(SC520_ROMCS2CTL, 0x0615);
write_mmcr_byte(SC520_ADDDECCTL, 0x02);
write_mmcr_byte(SC520_UART1CTL, 0x07);
write_mmcr_byte(SC520_SYSARBCTL,0x06);
write_mmcr_word(SC520_SYSARBMENB, 0x0003);
/* Crystal is 33.000MHz */
gd->bus_clk = 33000000;
return 0;
}
int dram_init(void)
{
init_sc520_dram();
return 0;
}
void show_boot_progress(int val)
{
uchar led_mask;
led_mask = 0x00;
if (val < 0)
led_mask |= LED_ERR_BITMASK;
led_mask |= (uchar)(val & 0x001f);
outb(led_mask, LED_LATCH_ADDRESS);
}
int last_stage_init(void)
{
int minor;
int major;
major = minor = 0;
printf("Serck Controls eNET\n");
return 0;
}
ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
{
if (banknum == 0) { /* non-CFI boot flash */
info->portwidth = FLASH_CFI_8BIT;
info->chipwidth = FLASH_CFI_BY8;
info->interface = FLASH_CFI_X8;
return 1;
} else
return 0;
}

50
board/eNET/eNET_start.S Normal file
View file

@ -0,0 +1,50 @@
/*
* (C) Copyright 2008
* Graeme Russ, graeme.russ@gmail.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include "hardware.h"
/* board early intialization */
.globl early_board_init
early_board_init:
/* No 32-bit board specific initialisation */
jmp *%ebp /* return to caller */
.globl show_boot_progress_asm
show_boot_progress_asm:
movb %al, %dl /* Create Working Copy */
andb $0x80, %dl /* Mask in only Error bit */
shrb $0x02, %dl /* Shift Error bit to Error LED */
andb $0x0f, %al /* Mask out 'Error' bit */
orb %dl, %al /* Mask in ERR LED */
movw $LED_LATCH_ADDRESS, %dx
outb %al, %dx
jmp *%ebp /* return to caller */
.globl cpu_halt_asm
cpu_halt_asm:
movb $0x0f, %al
movw $LED_LATCH_ADDRESS, %dx
outb %al, %dx
hlt
jmp cpu_halt_asm

90
board/eNET/eNET_start16.S Normal file
View file

@ -0,0 +1,90 @@
/*
* (C) Copyright 2008
* Graeme Russ, graeme.russ@gmail.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* 16bit initialization code.
* This code have to map the area of the boot flash
* that is used by U-boot to its final destination.
*/
/* #include <asm/ic/sc520_defs.h> */
#include "hardware.h"
.text
.section .start16, "ax"
.code16
.globl board_init16
board_init16:
/* Alias MMCR to 0xdf000 */
movw $0xfffc, %dx
movl $0x800df0cb, %eax
outl %eax, %dx
/* Set ds to point to MMCR alias */
movw $0xdf00, %ax
movw %ax, %ds
/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
movl $0x00c0, %edi /* SC520_PAR14 */
movl $0x8bfff800, %eax /* TODO: Check this */
movl %eax, (%di)
/* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
movl $0x00c4, %edi /* SC520_PAR15 */
movl $0x38201000, %eax
movl %eax, (%di)
/* Disable SDRAM write buffer */
movw $0x0040, %di /* SC520_DBCTL */
xorw %ax, %ax
movb %al, (%di)
/* Disabe MMCR alias */
movw $0xfffc, %dx
movl $0x000000cb, %eax
outl %eax, %dx
/* the return address is stored in bp */
jmp *%bp
.section .bios, "ax"
.code16
.globl realmode_reset
realmode_reset:
/* Alias MMCR to 0xdf000 */
movw $0xfffc, %dx
movl $0x800df0cb, %eax
outl %eax, %dx
/* Set ds to point to MMCR alias */
movw $0xdf00, %ax
movw %ax, %ds
/* issue software reset thorugh MMCR */
movl $0xd72, %edi
movb $0x01, %al
movb %al, (%di)
1: hlt
jmp 1

38
board/xilinx/xupv2p/xupv2p.c → board/eNET/hardware.h
View file

@ -1,7 +1,6 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
* (C) Copyright 2008
* Graeme Russ, graeme.russ@gmail.com.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -22,28 +21,15 @@
* MA 02111-1307 USA
*/
/* This is a board specific file. It's OK to include board specific
* header files */
#ifndef HARDWARE_H_
#define HARDWARE_H_
#include <common.h>
#include <config.h>
#define LED_LATCH_ADDRESS 0x1002
#define LED_RUN_BITMASK 0x01
#define LED_1_BITMASK 0x02
#define LED_2_BITMASK 0x04
#define LED_RX_BITMASK 0x08
#define LED_TX_BITMASK 0x10
#define LED_ERR_BITMASK 0x20
void do_reset (void)
{
#ifdef CONFIG_SYS_GPIO_0
*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) =
++(*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)));
#endif
#ifdef CONFIG_SYS_RESET_ADDRESS
puts ("Reseting board\n");
asm ("bra r0");
#endif
}
int gpio_init (void)
{
#ifdef CONFIG_SYS_GPIO_0
*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = 0x0;
#endif
return 0;
}
#endif /* HARDWARE_H_ */

90
board/eNET/u-boot.lds Normal file
View file

@ -0,0 +1,90 @@
/*
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
OUTPUT_ARCH(i386)
ENTRY(_start)
SECTIONS
{
. = 0x38040000; /* Location of bootcode in flash */
.text : { *(.text); }
. = ALIGN(4);
.rodata : { *(.rodata) *(.rodata.str1.1) *(.rodata.str1.32) }
_i386boot_text_size = SIZEOF(.text) + SIZEOF(.rodata);
. = 0x03FF0000; /* Ram data segment to use */
_i386boot_romdata_dest = ABSOLUTE(.);
.data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) }
_i386boot_romdata_start = LOADADDR(.data);
. = ALIGN(4);
.got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) }
. = ALIGN(4);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
_i386boot_cmd_start = LOADADDR(.u_boot_cmd);
_i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got) + SIZEOF(.u_boot_cmd);
. = ALIGN(4);
_i386boot_bss_start = ABSOLUTE(.);
.bss (NOLOAD) : { *(.bss) }
_i386boot_bss_size = SIZEOF(.bss);
/* 16bit realmode trampoline code */
.realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) + SIZEOF(.u_boot_cmd)) { *(.realmode) }
_i386boot_realmode = LOADADDR(.realmode);
_i386boot_realmode_size = SIZEOF(.realmode);
/* 16bit BIOS emulation code (just enough to boot Linux) */
.bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) }
_i386boot_bios = LOADADDR(.bios);
_i386boot_bios_size = SIZEOF(.bios);
/* The load addresses below assumes that the flash
* will be mapped so that 0x387f0000 == 0xffff0000
* at reset time
*
* The fe00 and ff00 offsets of the start32 and start16
* segments are arbitrary, the just have to be mapped
* at reset and the code have to fit.
* The fff0 offset of resetvec is important, however.
*/
. = 0xfffffe00;
.start32 : AT (0x3807fe00) { *(.start32); }
. = 0xf800;
.start16 : AT (0x3807f800) { *(.start16); }
. = 0xfff0;
.resetvec : AT (0x3807fff0) { *(.resetvec); }
_i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) );
}

1
board/esd/cpci405/Makefile
View file

@ -29,6 +29,7 @@ endif
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
COBJS += ../common/cmd_loadpci.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))

6
board/esd/cpci405/config.mk
View file

@ -21,8 +21,4 @@
# MA 02111-1307 USA
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
TEXT_BASE = 0xFFFD0000
endif
TEXT_BASE = 0xFFFC0000

331
board/esd/cpci405/cpci405.c
View file

@ -20,8 +20,9 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
@ -31,16 +32,16 @@
DECLARE_GLOBAL_DATA_PTR;
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/
#if 0
#define FPGA_DEBUG
#endif
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern void __ft_board_setup(void *blob, bd_t *bd);
#undef FPGA_DEBUG
/* fpga configuration data - generated by bin2cc */
const unsigned char fpgadata[] =
{
#ifdef CONFIG_CPCI405_VER2
# ifdef CONFIG_CPCI405AB
#if defined(CONFIG_CPCI405_VER2)
# if defined(CONFIG_CPCI405AB)
# include "fpgadata_cpci405ab.c"
# else
# include "fpgadata_cpci4052.c"
@ -56,7 +57,7 @@ const unsigned char fpgadata[] =
#include "../common/fpga.c"
#include "../common/auto_update.h"
#ifdef CONFIG_CPCI405AB
#if defined(CONFIG_CPCI405AB)
au_image_t au_image[] = {
{"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
{"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
@ -65,7 +66,7 @@ au_image_t au_image[] = {
{"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
};
#else
#ifdef CONFIG_CPCI405_VER2
#if defined(CONFIG_CPCI405_VER2)
au_image_t au_image[] = {
{"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
{"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
@ -91,7 +92,7 @@ int cpci405_version(void);
int gunzip(void *, int, unsigned char *, unsigned long *);
void lxt971_no_sleep(void);
int board_early_init_f (void)
int board_early_init_f(void)
{
#ifndef CONFIG_CPCI405_VER2
int index, len, i;
@ -100,18 +101,19 @@ int board_early_init_f (void)
#ifdef FPGA_DEBUG
/* set up serial port with default baudrate */
(void) get_clocks ();
(void)get_clocks();
gd->baudrate = CONFIG_BAUDRATE;
serial_init ();
serial_init();
console_init_f();
#endif
/*
* First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
* First pull fpga-prg pin low,
* to disable fpga logic (on version 2 board)
*/
out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
out32(GPIO0_OR, 0); /* pull prg low */
/*
@ -124,39 +126,42 @@ int board_early_init_f (void)
/* booting FPGA failed */
#ifndef FPGA_DEBUG
/* set up serial port with default baudrate */
(void) get_clocks ();
(void)get_clocks();
gd->baudrate = CONFIG_BAUDRATE;
serial_init ();
serial_init();
console_init_f();
#endif
printf("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
printf("(Timeout: INIT not low after "
"asserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
printf("(Timeout: INIT not high after "
"deasserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_DONE:
printf("(Timeout: DONE not high after programming FPGA)\n ");
printf("(Timeout: DONE not high after "
"programming FPGA)\n ");
break;
}
/* display infos on fpgaimage */
index = 15;
for (i=0; i<4; i++) {
for (i = 0; i < 4; i++) {
len = fpgadata[index];
printf("FPGA: %s\n", &(fpgadata[index+1]));
index += len+3;
printf("FPGA: %s\n", &(fpgadata[index + 1]));
index += len + 3;
}
putc ('\n');
putc('\n');
/* delayed reboot */
for (i=20; i>0; i--) {
for (i = 20; i > 0; i--) {
printf("Rebooting in %2d seconds \r",i);
for (index=0;index<1000;index++)
for (index = 0; index < 1000; index++)
udelay(1000);
}
putc ('\n');
putc('\n');
do_reset(NULL, 0, 0, NULL);
}
}
@ -167,7 +172,7 @@ int board_early_init_f (void)
* IRQ 16 405GP internally generated; active low; level sensitive
* IRQ 17-24 RESERVED
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
* IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive
* IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
@ -177,7 +182,7 @@ int board_early_init_f (void)
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
#ifdef CONFIG_CPCI405_6U
#if defined(CONFIG_CPCI405_6U)
if (cpci405_version() == 3) {
mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
} else {
@ -187,21 +192,20 @@ int board_early_init_f (void)
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
#endif
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicvcr, 0x00000001); /* set vect base=0,
* INT0 highest priority */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
return 0;
}
/* ------------------------------------------------------------------------- */
int ctermm2(void)
{
#ifdef CONFIG_CPCI405_VER2
#if defined(CONFIG_CPCI405_VER2)
return 0; /* no, board is cpci405 */
#else
if ((*(unsigned char *)0xf0000400 == 0x00) &&
(*(unsigned char *)0xf0000401 == 0x01))
if ((in_8((void*)0xf0000400) == 0x00) &&
(in_8((void*)0xf0000401) == 0x01))
return 0; /* no, board is cpci405 */
else
return -1; /* yes, board is cterm-m2 */
@ -228,8 +232,8 @@ int cpci405_version(void)
mtdcr(cntrl0, cntrl0Reg | 0x03000000);
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
udelay(1000); /* wait some time before reading input */
value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
udelay(1000); /* wait some time before reading input */
value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
/*
* Restore GPIO settings
@ -263,7 +267,7 @@ int misc_init_r (void)
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
#ifdef CONFIG_CPCI405_VER2
#if defined(CONFIG_CPCI405_VER2)
{
unsigned char *dst;
ulong len = sizeof(fpgadata);
@ -283,9 +287,10 @@ int misc_init_r (void)
mtdcr(cntrl0, cntrl0Reg | 0x00300000);
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
(uchar *)fpgadata, &len) != 0) {
printf("GUNZIP ERROR - must RESET board to recover\n");
do_reset(NULL, 0, 0, NULL);
}
status = fpga_boot(dst, len);
@ -293,31 +298,34 @@ int misc_init_r (void)
printf("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
printf("(Timeout: INIT not low after "
"asserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
printf("(Timeout: INIT not high after "
"deasserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_DONE:
printf("(Timeout: DONE not high after programming FPGA)\n ");
printf("(Timeout: DONE not high after "
"programming FPGA)\n ");
break;
}
/* display infos on fpgaimage */
index = 15;
for (i=0; i<4; i++) {
for (i = 0; i < 4; i++) {
len = dst[index];
printf("FPGA: %s\n", &(dst[index+1]));
index += len+3;
printf("FPGA: %s\n", &(dst[index + 1]));
index += len + 3;
}
putc ('\n');
putc('\n');
/* delayed reboot */
for (i=20; i>0; i--) {
printf("Rebooting in %2d seconds \r",i);
for (index=0;index<1000;index++)
for (i = 20; i > 0; i--) {
printf("Rebooting in %2d seconds \r", i);
for (index = 0; index < 1000; index++)
udelay(1000);
}
putc ('\n');
putc('\n');
do_reset(NULL, 0, 0, NULL);
}
@ -328,12 +336,12 @@ int misc_init_r (void)
/* display infos on fpgaimage */
index = 15;
for (i=0; i<4; i++) {
for (i = 0; i < 4; i++) {
len = dst[index];
printf("%s ", &(dst[index+1]));
index += len+3;
printf("%s ", &(dst[index + 1]));
index += len + 3;
}
putc ('\n');
putc('\n');
free(dst);
@ -345,68 +353,48 @@ int misc_init_r (void)
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
udelay(1000); /* wait 1ms */
#ifdef CONFIG_CPCI405_6U
#if defined(CONFIG_CPCI405_6U)
#error HIER GETH ES WEITER MIT IO ACCESSORS
if (cpci405_version() == 3) {
volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR;
volatile unsigned char *leds = (unsigned char *)CONFIG_SYS_LED_ADDR;
/*
* Enable outputs in fpga on version 3 board
*/
*fpga_mode |= CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT;
out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
/*
* Set outputs to 0
*/
*leds = 0x00;
out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
/*
* Reset external DUART
*/
*fpga_mode |= CONFIG_SYS_FPGA_MODE_DUART_RESET;
out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
CONFIG_SYS_FPGA_MODE_DUART_RESET);
udelay(100);
*fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_DUART_RESET);
out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
~CONFIG_SYS_FPGA_MODE_DUART_RESET);
}
#endif
}
else {
puts("\n*** U-Boot Version does not match Board Version!\n");
puts("*** CPCI-405 Version 1.x detected!\n");
puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
puts("*** Please use correct U-Boot version "
"(CPCI405 instead of CPCI4052)!\n\n");
}
}
#else /* CONFIG_CPCI405_VER2 */
#if 0 /* test-only: code-plug now not relavant for ip-address any more */
/*
* Generate last byte of ip-addr from code-plug @ 0xf0000400
*/
if (ctermm2()) {
char str[32];
unsigned char ipbyte = *(unsigned char *)0xf0000400;
/*
* Only overwrite ip-addr with allowed values
*/
if ((ipbyte != 0x00) && (ipbyte != 0xff)) {
bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte;
sprintf(str, "%ld.%ld.%ld.%ld",
(bd->bi_ip_addr & 0xff000000) >> 24,
(bd->bi_ip_addr & 0x00ff0000) >> 16,
(bd->bi_ip_addr & 0x0000ff00) >> 8,
(bd->bi_ip_addr & 0x000000ff));
setenv("ipaddr", str);
}
}
#endif
if (cpci405_version() >= 2) {
puts("\n*** U-Boot Version does not match Board Version!\n");
puts("*** CPCI-405 Board Version 2.x detected!\n");
puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n");
puts("*** Please use correct U-Boot version "
"(CPCI4052 instead of CPCI405)!\n\n");
}
#endif /* CONFIG_CPCI405_VER2 */
/*
@ -415,46 +403,33 @@ int misc_init_r (void)
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x00001000);
return (0);
return 0;
}
/*
* Check Board Identity:
*/
int checkboard (void)
int checkboard(void)
{
#ifndef CONFIG_CPCI405_VER2
int index;
int len;
#endif
char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
int i = getenv_r("serial#", str, sizeof(str));
unsigned short ver;
puts ("Board: ");
puts("Board: ");
if (i == -1) {
puts ("### No HW ID - assuming CPCI405");
} else {
if (i == -1)
puts("### No HW ID - assuming CPCI405");
else
puts(str);
}
ver = cpci405_version();
printf(" (Ver %d.x, ", ver);
#if 0 /* test-only */
if (ver >= 2) {
volatile u16 *fpga_status = (u16 *)CONFIG_SYS_FPGA_BASE_ADDR + 1;
if (*fpga_status & CONFIG_SYS_FPGA_STATUS_FLASH) {
puts ("FLASH Bank B, ");
} else {
puts ("FLASH Bank A, ");
}
}
#endif
if (ctermm2()) {
char str[4];
@ -465,32 +440,31 @@ int checkboard (void)
setenv("boardid", str);
printf("CTERM-M2 - Id=%s)", str);
} else {
if (cpci405_host()) {
puts ("PCI Host Version)");
} else {
puts ("PCI Adapter Version)");
}
if (cpci405_host())
puts("PCI Host Version)");
else
puts("PCI Adapter Version)");
}
#ifndef CONFIG_CPCI405_VER2
puts ("\nFPGA: ");
puts("\nFPGA: ");
/* display infos on fpgaimage */
index = 15;
for (i=0; i<4; i++) {
for (i = 0; i < 4; i++) {
len = fpgadata[index];
printf("%s ", &(fpgadata[index+1]));
index += len+3;
printf("%s ", &(fpgadata[index + 1]));
index += len + 3;
}
#endif
putc ('\n');
putc('\n');
return 0;
}
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
#if defined(CONFIG_LXT971_NO_SLEEP)
/*
* Disable sleep mode in LXT971
@ -499,25 +473,24 @@ void reset_phy(void)
#endif
}
#ifdef CONFIG_CPCI405_VER2
#ifdef CONFIG_IDE_RESET
#if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
void ide_set_reset(int on)
{
volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR;
/*
* Assert or deassert CompactFlash Reset Pin
*/
if (on) { /* assert RESET */
*fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_CF_RESET);
} else { /* release RESET */
*fpga_mode |= CONFIG_SYS_FPGA_MODE_CF_RESET;
if (on) { /* assert RESET */
out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
~CONFIG_SYS_FPGA_MODE_CF_RESET);
} else { /* release RESET */
out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
CONFIG_SYS_FPGA_MODE_CF_RESET);
}
}
#endif /* CONFIG_IDE_RESET */
#endif /* CONFIG_CPCI405_VER2 */
#endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
#if defined(CONFIG_PCI)
void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
@ -552,15 +525,44 @@ int pci_pre_init(struct pci_controller *hose)
}
#endif /* defined(CONFIG_PCI) */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
int rc;
#ifdef CONFIG_CPCI405AB
__ft_board_setup(blob, bd);
#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \
|= CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
#define ONE_WIRE_SET (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \
&= ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
#define ONE_WIRE_GET (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_STATUS) \
& CONFIG_SYS_FPGA_MODE_1WIRE)
/*
* Disable PCI in adapter mode.
*/
if (!cpci405_host()) {
rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
"disabled", sizeof("disabled"), 1);
if (rc) {
printf("Unable to update property status in PCI node, "
"err=%s\n",
fdt_strerror(rc));
}
}
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
#if defined(CONFIG_CPCI405AB)
#define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
CONFIG_SYS_FPGA_MODE), \
in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
CONFIG_SYS_FPGA_MODE)) | \
CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
#define ONE_WIRE_SET out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
CONFIG_SYS_FPGA_MODE), \
in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
CONFIG_SYS_FPGA_MODE)) & \
~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
#define ONE_WIRE_GET (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
CONFIG_SYS_FPGA_STATUS)) & \
CONFIG_SYS_FPGA_MODE_1WIRE)
/*
* Generate a 1-wire reset, return 1 if no presence detect was found,
@ -630,7 +632,7 @@ void OWWriteByte(int data)
{
int loop;
for (loop=0; loop<8; loop++) {
for (loop = 0; loop < 8; loop++) {
OWWriteBit(data & 0x01);
data >>= 1;
}
@ -640,11 +642,10 @@ int OWReadByte(void)
{
int loop, result = 0;
for (loop=0; loop<8; loop++) {
for (loop = 0; loop < 8; loop++) {
result >>= 1;
if (OWReadBit()) {
if (OWReadBit())
result |= 0x80;
}
}
return result;
@ -652,7 +653,7 @@ int OWReadByte(void)
int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
volatile unsigned short val;
unsigned short val;
int result;
int i;
unsigned char ow_id[6];
@ -662,23 +663,25 @@ int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/*
* Clear 1-wire bit (open drain with pull-up)
*/
val = *(volatile unsigned short *)0xf0400000;
val &= ~0x1000; /* clear 1-wire bit */
*(volatile unsigned short *)0xf0400000 = val;
val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
CONFIG_SYS_FPGA_MODE));
val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
CONFIG_SYS_FPGA_MODE), val);
result = OWTouchReset();
if (result != 0) {
if (result != 0)
puts("No 1-wire device detected!\n");
}
OWWriteByte(0x33); /* send read rom command */
OWReadByte(); /* skip family code ( == 0x01) */
for (i=0; i<6; i++) {
for (i = 0; i < 6; i++)
ow_id[i] = OWReadByte();
}
ow_crc = OWReadByte(); /* read crc */
sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]);
sprintf(str, "%08X%04X",
*(unsigned int *)&ow_id[0],
*(unsigned short *)&ow_id[4]);
printf("Setting environment variable 'ow_id' to %s\n", str);
setenv("ow_id", str);
@ -690,8 +693,8 @@ U_BOOT_CMD(
NULL
);
#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */
#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
/*
* Write backplane ip-address...
@ -706,12 +709,14 @@ int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
IPaddr_t ipaddr;
buf = malloc(CONFIG_ENV_SIZE_2);
if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) {
if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
(uchar *)buf, CONFIG_ENV_SIZE_2))
puts("\nError reading backplane EEPROM!\n");
} else {
crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4);
else {
crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
if (crc != *(ulong *)buf) {
printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf);
printf("ERROR: crc mismatch %08lx %08lx\n",
crc, *(ulong *)buf);
return -1;
}
@ -768,12 +773,12 @@ int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
memset(buf, 0, CONFIG_ENV_SIZE_2);
sprintf(str, "bp_ip=%s", argv[1]);
strcpy(buf+4, str);
crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4);
crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
*(ulong *)buf = crc;
if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) {
if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
0, (uchar *)buf, CONFIG_ENV_SIZE_2))
puts("\nError writing backplane EEPROM!\n");
}
free(buf);

10
board/esd/plu405/plu405.c
View file

@ -104,6 +104,7 @@ int misc_init_r (void)
unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
unsigned char *dst;
unsigned char fctr;
ulong len = sizeof(fpgadata);
int status;
int index;
@ -203,6 +204,15 @@ int misc_init_r (void)
out_8(duart0_mcr, 0x08);
out_8(duart1_mcr, 0x08);
/*
* Enable auto RS485 mode in 2nd external uart
*/
out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
fctr |= 0x08; /* enable RS485 mode */
out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
out_8((void *)DUART1_BA + 3, 0); /* write LCR */
return (0);
}

2
board/esd/pmc440/cmd_pmc440.c
View file

@ -364,7 +364,7 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
#endif
/*
* gd->bd->bi_memsize == physical ram size - CFG_MEM_TOP_HIDE
* gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
*/
param = base - (pram << 10);
printf("PARAM: @%08x\n", param);

24
board/esd/pmc440/pmc440.c
View file

@ -107,7 +107,7 @@ int board_early_init_f(void)
* Setup the GPIO pins
* TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
*/
out32(GPIO0_OR, 0x40000002);
out32(GPIO0_OR, 0x40000102);
out32(GPIO0_TCR, 0x4c90011f);
out32(GPIO0_OSRL, 0x28051400);
out32(GPIO0_OSRH, 0x55005000);
@ -755,17 +755,31 @@ int post_hotkeys_pressed(void)
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
char *s;
unsigned short val_method, val_behavior;
/* special LED setup for NGCC/CANDES */
if ((s = getenv("bd_type")) &&
((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
val_method = 0x0e0a;
val_behavior = 0x0cf2;
} else {
/* PMC440 standard type */
val_method = 0x0e10;
val_behavior = 0x0cf0;
}
if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0df0);
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, 0x0e10);
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior);
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method);
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
}
if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0df0);
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, 0x0e10);
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior);
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method);
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
}
}

52
board/freescale/mpc8315erdb/mpc8315erdb.c
View file

@ -30,6 +30,7 @@
#include <pci.h>
#include <mpc83xx.h>
#include <netdev.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@ -95,12 +96,45 @@ static struct pci_region pci_regions[] = {
}
};
static struct pci_region pcie_regions_0[] = {
{
.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
.size = CONFIG_SYS_PCIE1_MEM_SIZE,
.flags = PCI_REGION_MEM,
},
{
.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
.size = CONFIG_SYS_PCIE1_IO_SIZE,
.flags = PCI_REGION_IO,
},
};
static struct pci_region pcie_regions_1[] = {
{
.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
.size = CONFIG_SYS_PCIE2_MEM_SIZE,
.flags = PCI_REGION_MEM,
},
{
.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
.size = CONFIG_SYS_PCIE2_IO_SIZE,
.flags = PCI_REGION_IO,
},
};
void pci_init_board(void)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile sysconf83xx_t *sysconf = &immr->sysconf;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
volatile law83xx_t *pcie_law = sysconf->pcielaw;
struct pci_region *reg[] = { pci_regions };
struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
int warmboot;
/* Enable all 3 PCI_CLK_OUTPUTs. */
@ -119,6 +153,24 @@ void pci_init_board(void)
warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF;
mpc83xx_pci_init(1, reg, warmboot);
/* Configure the clock for PCIE controller */
clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
/* Deassert the resets in the control register */
out_be32(&sysconf->pecr1, 0xE0008000);
out_be32(&sysconf->pecr2, 0xE0008000);
udelay(2000);
/* Configure PCI Express Local Access Windows */
out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
mpc83xx_pcie_init(2, pcie_reg, warmboot);
}
#if defined(CONFIG_OF_BOARD_SETUP)

7
board/freescale/mpc8349emds/pci.c
View file

@ -171,15 +171,10 @@ void pci_init_board(void)
void pci_init_board(void)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
struct pci_region *reg[] = { pci1_regions };
/* Enable all 8 PCI_CLK_OUTPUTS */
clk->occr = 0xff000000;
udelay(2000);
/* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
@ -187,8 +182,6 @@ void pci_init_board(void)
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
udelay(2000);
mpc83xx_pci_init(1, reg, 0);
/* Configure PCI Inbound Translation Windows (3 1MB windows) */

6
board/freescale/mpc837xemds/mpc837xemds.c
View file

@ -18,6 +18,7 @@
#include <tsec.h>
#include <libfdt.h>
#include <fdt_support.h>
#include "pci.h"
#include "../common/pq-mds-pib.h"
int board_early_init_f(void)
@ -38,14 +39,10 @@ int board_early_init_f(void)
case SPR_8377:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
break;
case SPR_8378:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
break;
case SPR_8379:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
@ -316,6 +313,7 @@ void ft_board_setup(void *blob, bd_t *bd)
ft_pci_setup(blob, bd);
if (board_pci_host_broken())
ft_pci_fixup(blob, bd);
ft_pcie_fixup(blob, bd);
#endif
}
#endif /* CONFIG_OF_BOARD_SETUP */

89
board/freescale/mpc837xemds/pci.c
View file

@ -16,7 +16,9 @@
#include <mpc83xx.h>
#include <pci.h>
#include <i2c.h>
#include <fdt_support.h>
#include <asm/fsl_i2c.h>
#include <asm/fsl_serdes.h>
#if defined(CONFIG_PCI)
static struct pci_region pci_regions[] = {
@ -40,15 +42,59 @@ static struct pci_region pci_regions[] = {
}
};
static struct pci_region pcie_regions_0[] = {
{
.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
.size = CONFIG_SYS_PCIE1_MEM_SIZE,
.flags = PCI_REGION_MEM,
},
{
.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
.size = CONFIG_SYS_PCIE1_IO_SIZE,
.flags = PCI_REGION_IO,
},
};
static struct pci_region pcie_regions_1[] = {
{
.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
.size = CONFIG_SYS_PCIE2_MEM_SIZE,
.flags = PCI_REGION_MEM,
},
{
.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
.size = CONFIG_SYS_PCIE2_IO_SIZE,
.flags = PCI_REGION_IO,
},
};
static int is_pex_x2(void)
{
const char *pex_x2 = getenv("pex_x2");
if (pex_x2 && !strcmp(pex_x2, "yes"))
return 1;
return 0;
}
void pci_init_board(void)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile sysconf83xx_t *sysconf = &immr->sysconf;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
volatile law83xx_t *pcie_law = sysconf->pcielaw;
struct pci_region *reg[] = { pci_regions };
struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
u32 spridr = in_be32(&immr->sysconf.spridr);
int pex2 = is_pex_x2();
if (board_pci_host_broken())
return;
goto skip_pci;
/* Enable all 5 PCI_CLK_OUTPUTS */
clk->occr |= 0xf8000000;
@ -64,5 +110,46 @@ void pci_init_board(void)
udelay(2000);
mpc83xx_pci_init(1, reg, 0);
skip_pci:
/* There is no PEX in MPC8379 parts. */
if (PARTID_NO_E(spridr) == SPR_8379)
return;
/* Configure the clock for PCIE controller */
clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
/* Deassert the resets in the control register */
out_be32(&sysconf->pecr1, 0xE0008000);
if (!pex2)
out_be32(&sysconf->pecr2, 0xE0008000);
udelay(2000);
/* Configure PCI Express Local Access Windows */
out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
if (pex2)
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
else
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg, 0);
}
void ft_pcie_fixup(void *blob, bd_t *bd)
{
const char *status = "disabled (PCIE1 is x2)";
if (!is_pex_x2())
return;
do_fixup_by_path(blob, "pci2", "status", status,
strlen(status) + 1, 1);
}
#endif /* CONFIG_PCI */

6
board/freescale/mpc837xemds/pci.h Normal file
View file

@ -0,0 +1,6 @@
#ifndef __BOARD_MPC837XEMDS_PCI_H
#define __BOARD_MPC837XEMDS_PCI_H
extern void ft_pcie_fixup(void *blob, bd_t *bd);
#endif /* __BOARD_MPC837XEMDS_PCI_H */

6
board/freescale/mpc8536ds/ddr.c
View file

@ -79,4 +79,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
/*
* For wake up arp feature, we need enable auto self refresh
*/
popts->auto_self_refresh_en = 1;
popts->sr_it = 0x6;
}

4
board/freescale/mpc8536ds/law.c
View file

@ -30,14 +30,14 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
};

30
board/freescale/mpc8536ds/mpc8536ds.c
View file

@ -192,14 +192,14 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE,
CONFIG_SYS_PCIE3_MEM_BUS,
CONFIG_SYS_PCIE3_MEM_PHYS,
CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE3_IO_BASE,
CONFIG_SYS_PCIE3_IO_BUS,
CONFIG_SYS_PCIE3_IO_PHYS,
CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
@ -247,22 +247,22 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE2,
CONFIG_SYS_PCIE1_MEM_BUS2,
CONFIG_SYS_PCIE1_MEM_PHYS2,
CONFIG_SYS_PCIE1_MEM_SIZE2,
PCI_REGION_MEM);
@ -310,22 +310,22 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE,
CONFIG_SYS_PCIE2_MEM_BUS,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BASE,
CONFIG_SYS_PCIE2_IO_BUS,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE2,
CONFIG_SYS_PCIE2_MEM_BUS2,
CONFIG_SYS_PCIE2_MEM_PHYS2,
CONFIG_SYS_PCIE2_MEM_SIZE2,
PCI_REGION_MEM);
@ -378,22 +378,22 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
#ifdef CONFIG_SYS_PCI1_MEM_BASE2
#ifdef CONFIG_SYS_PCI1_MEM_BUS2
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE2,
CONFIG_SYS_PCI1_MEM_BUS2,
CONFIG_SYS_PCI1_MEM_PHYS2,
CONFIG_SYS_PCI1_MEM_SIZE2,
PCI_REGION_MEM);
@ -433,7 +433,7 @@ int board_early_init_r(void)
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */

8
board/freescale/mpc8536ds/tlb.c
View file

@ -41,7 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE,
SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 0),
@ -53,17 +53,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI I/O */
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256K, 1),

3
board/freescale/mpc8540ads/ddr.c
View file

@ -65,6 +65,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
*/
popts->write_data_delay = 3;
/* 2T timing enable */
popts->twoT_en = 1;
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed

2
board/freescale/mpc8540ads/law.c
View file

@ -52,7 +52,7 @@ struct law_entry law_table[] = {
/* This is not so much the SDRAM map as it is the whole localbus map. */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);

2
board/freescale/mpc8540ads/mpc8540ads.c
View file

@ -133,7 +133,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {

8
board/freescale/mpc8540ads/tlb.c
View file

@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 3: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 4: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),

2
board/freescale/mpc8541cds/mpc8541cds.c
View file

@ -308,7 +308,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {

8
board/freescale/mpc8541cds/tlb.c
View file

@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 3: 256M Non-cacheable, guarded
* 0xa0000000 256M PCI2 MEM First half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 4: 256M Non-cacheable, guarded
* 0xb0000000 256M PCI2 MEM Second half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),

3
board/freescale/mpc8544ds/ddr.c
View file

@ -75,6 +75,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
*/
popts->write_data_delay = 3;
/* 2T timing enable */
popts->twoT_en = 1;
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed

40
board/freescale/mpc8544ds/mpc8544ds.c
View file

@ -121,7 +121,7 @@ pci_init_board(void)
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
struct pci_controller *hose = &pcie3_hose;
int pcie_ep = (host_agent == 1);
int pcie_configured = io_sel >= 1;
int pcie_configured = io_sel >= 6;
struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
@ -139,22 +139,22 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE,
CONFIG_SYS_PCIE3_MEM_BUS,
CONFIG_SYS_PCIE3_MEM_PHYS,
CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE3_IO_BASE,
CONFIG_SYS_PCIE3_IO_BUS,
CONFIG_SYS_PCIE3_IO_PHYS,
CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE2,
CONFIG_SYS_PCIE3_MEM_BUS2,
CONFIG_SYS_PCIE3_MEM_PHYS2,
CONFIG_SYS_PCIE3_MEM_SIZE2,
PCI_REGION_MEM);
@ -173,7 +173,7 @@ pci_init_board(void)
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
*/
in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BASE);
in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
} else {
printf (" PCIE3: disabled\n");
}
@ -188,7 +188,7 @@ pci_init_board(void)
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 5);
int pcie_configured = io_sel & 6;
int pcie_configured = io_sel >= 2;
struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
@ -206,22 +206,22 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
#ifdef CONFIG_SYS_PCIE1_MEM_BUS2
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE2,
CONFIG_SYS_PCIE1_MEM_BUS2,
CONFIG_SYS_PCIE1_MEM_PHYS2,
CONFIG_SYS_PCIE1_MEM_SIZE2,
PCI_REGION_MEM);
@ -251,7 +251,7 @@ pci_init_board(void)
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
struct pci_controller *hose = &pcie2_hose;
int pcie_ep = (host_agent == 3);
int pcie_configured = io_sel & 4;
int pcie_configured = io_sel >= 4;
struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
@ -269,22 +269,22 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE,
CONFIG_SYS_PCIE2_MEM_BUS,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BASE,
CONFIG_SYS_PCIE2_IO_BUS,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
#ifdef CONFIG_SYS_PCIE2_MEM_BUS2
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE2,
CONFIG_SYS_PCIE2_MEM_BUS2,
CONFIG_SYS_PCIE2_MEM_PHYS2,
CONFIG_SYS_PCIE2_MEM_SIZE2,
PCI_REGION_MEM);
@ -337,22 +337,22 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
#ifdef CONFIG_SYS_PCIE3_MEM_BUS2
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE2,
CONFIG_SYS_PCIE3_MEM_BUS2,
CONFIG_SYS_PCIE3_MEM_PHYS2,
CONFIG_SYS_PCIE3_MEM_SIZE2,
PCI_REGION_MEM);

6
board/freescale/mpc8544ds/tlb.c
View file

@ -52,21 +52,21 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 1: 1G Non-cacheable, guarded
* 0x80000000 1G PCIE 8,9,a,b
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_PHYS, CONFIG_SYS_PCIE_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1G, 1),
/*
* TLB 2: 256M Non-cacheable, guarded
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/*
* TLB 3: 256M Non-cacheable, guarded
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),

10
board/freescale/mpc8548cds/mpc8548cds.c
View file

@ -125,7 +125,7 @@ local_bus_init(void)
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & 0x0f) * 2;
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;
@ -306,14 +306,14 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
@ -390,14 +390,14 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);

6
board/freescale/mpc8548cds/tlb.c
View file

@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 1: 1G Non-cacheable, guarded
* 0x80000000 1G PCI1/PCIE 8,9,a,b
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1G, 1),
@ -62,14 +62,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
/*
* TLB 2: 256M Non-cacheable, guarded
*/
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/*
* TLB 3: 256M Non-cacheable, guarded
*/
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
#endif

2
board/freescale/mpc8555cds/mpc8555cds.c
View file

@ -308,7 +308,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {

8
board/freescale/mpc8555cds/tlb.c
View file

@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 3: 256M Non-cacheable, guarded
* 0xa0000000 256M PCI2 MEM First half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 4: 256M Non-cacheable, guarded
* 0xb0000000 256M PCI2 MEM Second half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),

3
board/freescale/mpc8560ads/ddr.c
View file

@ -65,6 +65,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
*/
popts->write_data_delay = 3;
/* 2T timing enable */
popts->twoT_en = 1;
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed

2
board/freescale/mpc8560ads/law.c
View file

@ -52,7 +52,7 @@ struct law_entry law_table[] = {
/* This is not so much the SDRAM map as it is the whole localbus map. */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);

2
board/freescale/mpc8560ads/mpc8560ads.c
View file

@ -337,7 +337,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {

8
board/freescale/mpc8560ads/tlb.c
View file

@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 1: 256M Non-cacheable, guarded
* 0x80000000 256M PCI1 MEM First half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 2: 256M Non-cacheable, guarded
* 0x90000000 256M PCI1 MEM Second half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 3: 256M Non-cacheable, guarded
* 0xc0000000 256M Rapid IO MEM First half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* TLB 4: 256M Non-cacheable, guarded
* 0xd0000000 256M Rapid IO MEM Second half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),

2
board/freescale/mpc8568mds/law.c
View file

@ -54,7 +54,7 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};

10
board/freescale/mpc8568mds/mpc8568mds.c
View file

@ -188,7 +188,7 @@ local_bus_init(void)
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & 0x0f) * 2;
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;
@ -397,14 +397,14 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
@ -450,14 +450,14 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);

2
board/freescale/mpc8568mds/tlb.c
View file

@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
* 0x80000000 512M PCI1 MEM
* 0xa0000000 512M PCIe MEM
*/
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_1G, 1),

4
board/freescale/mpc8572ds/law.c
View file

@ -28,14 +28,14 @@
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
};

28
board/freescale/mpc8572ds/mpc8572ds.c
View file

@ -166,11 +166,11 @@ void pci_init_board(void)
struct pci_controller *hose = &pcie3_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
(host_agent == 5) || (host_agent == 6);
int pcie_configured = io_sel >= 1;
int pcie_configured = (io_sel == 0x7);
struct pci_region *r = hose->regions;
u32 temp32;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
printf ("\n PCIE3 connected to ULI as %s (base address %x)",
pcie_ep ? "End Point" : "Root Complex",
(uint)pci);
@ -185,14 +185,14 @@ void pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE,
CONFIG_SYS_PCIE3_MEM_BUS,
CONFIG_SYS_PCIE3_MEM_PHYS,
CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE3_IO_BASE,
CONFIG_SYS_PCIE3_IO_BUS,
CONFIG_SYS_PCIE3_IO_PHYS,
CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
@ -215,7 +215,7 @@ void pci_init_board(void)
pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
PCI_BASE_ADDRESS_1, &temp32);
if (temp32 >= CONFIG_SYS_PCIE3_MEM_PHYS) {
if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
debug(" uli1572 read to %x\n", temp32);
in_be32((unsigned *)temp32);
}
@ -234,10 +234,10 @@ void pci_init_board(void)
struct pci_controller *hose = &pcie2_hose;
int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
(host_agent == 6) || (host_agent == 0);
int pcie_configured = io_sel & 4;
int pcie_configured = (io_sel == 0x3) || (io_sel == 0x7);
struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
pcie_ep ? "End Point" : "Root Complex",
(uint)pci);
@ -252,14 +252,14 @@ void pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE,
CONFIG_SYS_PCIE2_MEM_BUS,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BASE,
CONFIG_SYS_PCIE2_IO_BUS,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
@ -287,7 +287,9 @@ void pci_init_board(void)
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
(host_agent == 5);
int pcie_configured = io_sel & 6;
int pcie_configured = (io_sel == 0x2) || (io_sel == 0x3) ||
(io_sel == 0x7) || (io_sel == 0xb) ||
(io_sel == 0xc) || (io_sel == 0xf);
struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
@ -305,14 +307,14 @@ void pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
@ -356,7 +358,7 @@ int board_early_init_r(void)
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */

17
board/freescale/mpc8572ds/tlb.c
View file

@ -41,10 +41,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
@ -58,26 +54,26 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI I/O */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_PHYS, CONFIG_SYS_PCIE3_IO_PHYS,
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
@ -86,6 +82,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_4K, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

3
board/freescale/mpc8610hpcd/ddr.c
View file

@ -74,6 +74,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
*/
popts->write_data_delay = 3;
/* 2T timing enable */
popts->twoT_en = 1;
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed

4
board/freescale/mpc8610hpcd/law.c
View file

@ -31,8 +31,8 @@ struct law_entry law_table[] = {
#if !defined(CONFIG_SPD_EEPROM)
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
#endif
SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),

12
board/freescale/mpc8610hpcd/mpc8610hpcd.c
View file

@ -266,14 +266,14 @@ void pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
@ -321,14 +321,14 @@ void pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE,
CONFIG_SYS_PCIE2_MEM_BUS,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BASE,
CONFIG_SYS_PCIE2_IO_BUS,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
@ -370,14 +370,14 @@ void pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);

2
board/freescale/mpc8641hpcn/ddr.c
View file

@ -162,4 +162,6 @@ void fsl_ddr_board_options(memctl_options_t *popts,
}
}
/* 2T timing enable */
popts->twoT_en = 1;
}

23
board/keymile/common/common.c
View file

@ -22,10 +22,14 @@
*/
#include <common.h>
#if defined(CONFIG_MGCOGE)
#include <mpc8260.h>
#endif
#include <ioports.h>
#include <malloc.h>
#include <hush.h>
#include <net.h>
#include <asm/io.h>
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
@ -33,8 +37,6 @@
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
#include <i2c.h>
#endif
#include <asm/io.h>
extern int i2c_soft_read_pin (void);
@ -495,6 +497,7 @@ void i2c_init_board(void)
#endif
}
#endif
#endif
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
int fdt_set_node_and_value (void *blob,
@ -521,3 +524,19 @@ int fdt_set_node_and_value (void *blob,
return ret;
}
#endif
int ethernet_present (void)
{
return (in_8((u8 *)CONFIG_SYS_PIGGY_BASE + CONFIG_SYS_SLOT_ID_OFF) & 0x80);
}
int board_eth_init (bd_t *bis)
{
#ifdef CONFIG_KEYMILE_HDLC_ENET
(void)keymile_hdlc_enet_initialize (bis);
#endif
if (ethernet_present ()) {
return -1;
}
return 0;
}

20
board/keymile/common/common.h Normal file
View file

@ -0,0 +1,20 @@
/*
* (C) Copyright 2008
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#ifndef __KEYMILE_COMMON_H
#define __KEYMILE_COMMON_H
int ethernet_present (void);
int ivm_read_eeprom (void);
#ifdef CONFIG_KEYMILE_HDLC_ENET
int keymile_hdlc_enet_initialize (bd_t *bis);
#endif
#endif /* __KEYMILE_COMMON_H */

53
board/keymile/kmeter1/Makefile Normal file
View file

@ -0,0 +1,53 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
endif
LIB = $(obj)lib$(BOARD).a
COBJS += $(BOARD).o ../common/common.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

24
board/keymile/kmeter1/config.mk Normal file
View file

@ -0,0 +1,24 @@
#
# (C) Copyright 2008
# Heiko Schocher, DENX Software Engineering, hs@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0xF0000000

158
board/keymile/kmeter1/kmeter1.c Normal file
View file

@ -0,0 +1,158 @@
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* Copyright (C) 2007 Logic Product Development, Inc.
* Peter Barada <peterb@logicpd.com>
*
* Copyright (C) 2007 MontaVista Software, Inc.
* Anton Vorontsov <avorontsov@ru.mvista.com>
*
* (C) Copyright 2008
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <i2c.h>
#include <miiphy.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <pci.h>
#include <libfdt.h>
#include "../common/common.h"
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* port pin dir open_drain assign */
/* MDIO */
{0, 1, 3, 0, 2}, /* MDIO */
{0, 2, 1, 0, 1}, /* MDC */
/* UCC4 - UEC */
{1, 14, 1, 0, 1}, /* TxD0 */
{1, 15, 1, 0, 1}, /* TxD1 */
{1, 20, 2, 0, 1}, /* RxD0 */
{1, 21, 2, 0, 1}, /* RxD1 */
{1, 18, 1, 0, 1}, /* TX_EN */
{1, 26, 2, 0, 1}, /* RX_DV */
{1, 27, 2, 0, 1}, /* RX_ER */
{1, 24, 2, 0, 1}, /* COL */
{1, 25, 2, 0, 1}, /* CRS */
{2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
{2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
/* DUART - UART2 */
{5, 0, 1, 0, 2}, /* UART2_SOUT */
{5, 2, 1, 0, 1}, /* UART2_RTS */
{5, 3, 2, 0, 2}, /* UART2_SIN */
{5, 1, 2, 0, 3}, /* UART2_CTS */
/* END of table */
{0, 0, 0, 0, QE_IOP_TAB_END},
};
int board_early_init_r (void)
{
void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8);
u32 val;
/*
* Because of errata in the UCCs, we have to write to the reserved
* registers to slow the clocks down.
*/
val = in_be32 (reg);
/* UCC1 */
val |= 0x00003000;
/* UCC2 */
val |= 0x0c000000;
out_be32 (reg, val);
/* enable the PHY on the PIGGY */
setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01);
return 0;
}
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
u32 ddr_size;
u32 ddr_size_log2;
msize = CONFIG_SYS_DDR_SIZE;
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
if (ddr_size & 1)
return -1;
}
im->sysconf.ddrlaw[0].ar =
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
udelay (200);
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
return msize;
}
phys_size_t initdram (int board_type)
{
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
extern void ddr_enable_ecc (unsigned int dram_size);
#endif
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
msize = fixed_sdram ();
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
/*
* Initialize DDR ECC byte
*/
ddr_enable_ecc (msize * 1024 * 1024);
#endif
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
int checkboard (void)
{
puts ("Board: Keymile kmeter1");
if (ethernet_present ())
puts (" with PIGGY.");
puts ("\n");
return 0;
}
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup (void *blob, bd_t *bd)
{
ft_cpu_setup (blob, bd);
}
#endif

10
board/keymile/mgcoge/mgcoge.c
View file

@ -25,6 +25,7 @@
#include <mpc8260.h>
#include <ioports.h>
#include <malloc.h>
#include <net.h>
#include <asm/io.h>
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
@ -35,7 +36,8 @@
#include <i2c.h>
#endif
extern int ivm_read_eeprom (void);
#include "../common/common.h"
/*
* I/O Port configuration table
*
@ -285,8 +287,10 @@ phys_size_t initdram (int board_type)
int checkboard(void)
{
puts ("Board: mgcoge\n");
puts ("Board: Keymile mgcoge");
if (ethernet_present ())
puts (" with PIGGY.");
puts ("\n");
return 0;
}

8
board/keymile/mgsuvd/mgsuvd.c
View file

@ -22,13 +22,14 @@
*/
#include <common.h>
#include <mpc8xx.h>
#include <net.h>
#include <asm/io.h>
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
extern int ivm_read_eeprom (void);
#include "../common/common.h"
DECLARE_GLOBAL_DATA_PTR;
@ -60,7 +61,10 @@ const uint sdram_table[] =
int checkboard (void)
{
puts ("Board: Keymile mgsuvd\n");
puts ("Board: Keymile mgsuvd");
if (ethernet_present ())
puts (" with PIGGY.");
puts ("\n");
return (0);
}

2
board/m501sk/Makefile
View file

@ -27,8 +27,6 @@ LIB = $(obj)lib$(BOARD).a
COBJS := m501sk.o eeprom.o
SOBJS := memsetup.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))

200
board/m501sk/memsetup.S
View file

@ -1,200 +0,0 @@
/*
* Memory Setup stuff - taken from blob memsetup.S
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
*
* Modified for the at91rm9200dk board by
* (C) Copyright 2004
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#ifdef CONFIG_BOOTBINFUNC
/*
* some parameters for the board
*
* This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
* turn is based on the boot.bin code from ATMEL
*
*/
/* flash */
#define MC_PUIA 0xFFFFFF10
#define MC_PUIA_VAL 0x00000000
#define MC_PUP 0xFFFFFF50
#define MC_PUP_VAL 0x00000000
#define MC_PUER 0xFFFFFF54
#define MC_PUER_VAL 0x00000000
#define MC_ASR 0xFFFFFF04
#define MC_ASR_VAL 0x00000000
#define MC_AASR 0xFFFFFF08
#define MC_AASR_VAL 0x00000000
#define EBI_CFGR 0xFFFFFF64
#define EBI_CFGR_VAL 0x00000000
#define SMC_CSR0 0xFFFFFF70
#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
/* clocks */
#define PLLAR 0xFFFFFC28
#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
#define PLLBR 0xFFFFFC2C
#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
#define MCKR 0xFFFFFC30
/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
#define MCKR_VAL 0x00000202
/* sdram */
#define PIOC_ASR 0xFFFFF870
#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */
#define PIOC_BSR 0xFFFFF874
#define PIOC_BSR_VAL 0x00000000
#define PIOC_PDR 0xFFFFF804
#define PIOC_PDR_VAL 0xFFFF0000
#define EBI_CSA 0xFFFFFF60
#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
#define SDRC_CR 0xFFFFFF98
#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
#define SDRAM 0x20000000 /* address of the SDRAM */
#define SDRAM1 0x20000080 /* address of the SDRAM */
#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
#define SDRC_MR 0xFFFFFF90
#define SDRC_MR_VAL 0x00000002 /* Precharge All */
#define SDRC_MR_VAL1 0x00000004 /* refresh */
#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
#define SDRC_TR 0xFFFFFF94
#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
_TEXT_BASE:
.word TEXT_BASE
.globl lowlevelinit
lowlevelinit:
/* memory control configuration */
/* this isn't very elegant, but what the heck */
ldr r0, =SMRDATA
ldr r1, _TEXT_BASE
sub r0, r0, r1
add r2, r0, #80
0:
/* the address */
ldr r1, [r0], #4
/* the value */
ldr r3, [r0], #4
str r3, [r1]
cmp r2, r0
bne 0b
/* delay - this is all done by guess */
ldr r0, =0x00010000
1:
subs r0, r0, #1
bhi 1b
ldr r0, =SMRDATA1
ldr r1, _TEXT_BASE
sub r0, r0, r1
add r2, r0, #176
2:
/* the address */
ldr r1, [r0], #4
/* the value */
ldr r3, [r0], #4
str r3, [r1]
cmp r2, r0
bne 2b
/* everything is fine now */
mov pc, lr
.ltorg
SMRDATA:
.word MC_PUIA
.word MC_PUIA_VAL
.word MC_PUP
.word MC_PUP_VAL
.word MC_PUER
.word MC_PUER_VAL
.word MC_ASR
.word MC_ASR_VAL
.word MC_AASR
.word MC_AASR_VAL
.word EBI_CFGR
.word EBI_CFGR_VAL
.word SMC_CSR0
.word SMC_CSR0_VAL
.word PLLAR
.word PLLAR_VAL
.word PLLBR
.word PLLBR_VAL
.word MCKR
.word MCKR_VAL
/* SMRDATA is 80 bytes long */
/* here there's a delay of 100 */
SMRDATA1:
.word PIOC_ASR
.word PIOC_ASR_VAL
.word PIOC_BSR
.word PIOC_BSR_VAL
.word PIOC_PDR
.word PIOC_PDR_VAL
.word EBI_CSA
.word EBI_CSA_VAL
.word SDRC_CR
.word SDRC_CR_VAL
.word SDRC_MR
.word SDRC_MR_VAL
.word SDRAM
.word SDRAM_VAL
.word SDRC_MR
.word SDRC_MR_VAL1
.word SDRAM
.word SDRAM_VAL
.word SDRAM
.word SDRAM_VAL
.word SDRAM
.word SDRAM_VAL
.word SDRAM
.word SDRAM_VAL
.word SDRAM
.word SDRAM_VAL
.word SDRAM
.word SDRAM_VAL
.word SDRAM
.word SDRAM_VAL
.word SDRAM
.word SDRAM_VAL
.word SDRC_MR
.word SDRC_MR_VAL2
.word SDRAM1
.word SDRAM_VAL
.word SDRC_TR
.word SDRC_TR_VAL
.word SDRAM
.word SDRAM_VAL
.word SDRC_MR
.word SDRC_MR_VAL3
.word SDRAM
.word SDRAM_VAL
/* SMRDATA1 is 176 bytes long */
#endif /* CONFIG_BOOTBINFUNC */

2
board/mpc8540eval/mpc8540eval.c
View file

@ -101,7 +101,7 @@ phys_size_t initdram (int board_type)
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
get_sys_info(&sysinfo);
/* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) {
lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
} else {
lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;

75
board/mpr2/lowlevel_init.S
View file

@ -22,6 +22,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm/macro.h>
.global lowlevel_init
@ -33,59 +34,35 @@ lowlevel_init:
/*
* Set frequency multipliers and dividers in FRQCR.
*/
mov.l WTCSR_A,r1
mov.l WTCSR_D,r0
mov.w r0,@r1
write16 WTCSR_A, WTCSR_D
mov.l WTCNT_A,r1
mov.l WTCNT_D,r0
mov.w r0,@r1
write16 WTCNT_A, WTCNT_D
mov.l FRQCR_A,r1
mov.l FRQCR_D,r0
mov.w r0,@r1
write16 FRQCR_A, FRQCR_D
/*
* Setup CS0 (Flash).
*/
mov.l CS0BCR_A, r1
mov.l CS0BCR_D, r0
mov.l r0, @r1
write32 CS0BCR_A, CS0BCR_D
mov.l CS0WCR_A, r1
mov.l CS0WCR_D, r0
mov.l r0, @r1
write32 CS0WCR_A, CS0WCR_D
/*
* Setup CS3 (SDRAM).
*/
mov.l CS3BCR_A, r1
mov.l CS3BCR_D, r0
mov.l r0, @r1
write32 CS3BCR_A, CS3BCR_D
mov.l CS3WCR_A, r1
mov.l CS3WCR_D, r0
mov.l r0, @r1
write32 CS3WCR_A, CS3WCR_D
mov.l SDCR_A, r1
mov.l SDCR_D1, r0
mov.l r0, @r1
write32 SDCR_A, SDCR_D1
mov.l RTCSR_A, r1
mov.l RTCSR_D, r0
mov.l r0, @r1
write32 RTCSR_A, RTCSR_D
mov.l RTCNT_A, r1
mov.l RTCNT_D, r0
mov.l r0, @r1
write32 RTCNT_A, RTCNT_D
mov.l RTCOR_A, r1
mov.l RTCOR_D, r0
mov.l r0, @r1
write32 RTCOR_A, RTCOR_D
mov.l SDCR_A, r1
mov.l SDCR_D2, r0
mov.l r0, @r1
write32 SDCR_A, SDCR_D2
mov.l SDMR3_A, r1
mov.l SDMR3_D, r0
@ -112,21 +89,27 @@ WTCSR_D: .long 0xA507 /* divide by 4096 */
/*
* Spansion S29GL256N11 @ 48 MHz
*/
CS0BCR_D: .long 0x12490400 /* 1 idle cycle inserted, normal space, 16 bit */
CS0WCR_D: .long 0x00000340 /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
/* 1 idle cycle inserted, normal space, 16 bit */
CS0BCR_D: .long 0x12490400
/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
CS0WCR_D: .long 0x00000340
/*
* Samsung K4S511632B-UL75 @ 48 MHz
* Micron MT48LC32M16A2-75 @ 48 MHz
*/
CS3BCR_D: .long 0x10004400 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
CS3WCR_D: .long 0x00000091 /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
SDCR_D1: .long 0x00000012 /* no refresh, 13 rows, 10 cols, NO bank active mode */
SDCR_D2: .long 0x00000812 /* refresh */
RTCSR_D: .long 0xA55A0008 /* 1/4, once */
RTCNT_D: .long 0xA55A005D /* count 93 */
RTCOR_D: .long 0xa55a005d /* count 93 */
SDMR3_D: .long 0x440 /* mode register CL2, burst read and SINGLE WRITE */
/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
CS3BCR_D: .long 0x10004400
/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
CS3WCR_D: .long 0x00000091
/* no refresh, 13 rows, 10 cols, NO bank active mode */
SDCR_D1: .long 0x00000012
SDCR_D2: .long 0x00000812 /* refresh */
RTCSR_D: .long 0xA55A0008 /* 1/4, once */
RTCNT_D: .long 0xA55A005D /* count 93 */
RTCOR_D: .long 0xa55a005d /* count 93 */
/* mode register CL2, burst read and SINGLE WRITE */
SDMR3_D: .long 0x440
/*
* Registers

195
board/ms7722se/lowlevel_init.S
View file

@ -27,13 +27,14 @@
#include <version.h>
#include <asm/processor.h>
#include <asm/macro.h>
/*
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
*
* (Note: As no stack is available, no subroutines can be called...).
* (Note: As no stack is available, no subroutines can be called...).
*/
.global lowlevel_init
@ -43,167 +44,96 @@
lowlevel_init:
/* Address of Cache Control Register */
mov.l CCR_A, r1
/*Instruction Cache Invalidate */
mov.l CCR_D, r0
mov.l r0, @r1
/*
* Cache Control Register
* Instruction Cache Invalidate
*/
write32 CCR_A, CCR_D
/* Address of MMU Control Register */
mov.l MMUCR_A, r1
/* TI == TLB Invalidate bit */
mov.l MMUCR_D, r0
mov.l r0, @r1
/*
* Address of MMU Control Register
* TI == TLB Invalidate bit
*/
write32 MMUCR_A, MMUCR_D
/* Address of Power Control Register 0 */
mov.l MSTPCR0_A, r1
mov.l MSTPCR0_D, r0
mov.l r0, @r1
write32 MSTPCR0_A, MSTPCR0_D
/* Address of Power Control Register 2 */
mov.l MSTPCR2_A, r1
mov.l MSTPCR2_D, r0
mov.l r0, @r1
write32 MSTPCR2_A, MSTPCR2_D
mov.l SBSCR_A, r1
mov.w SBSCR_D, r0
mov.w r0, @r1
write16 SBSCR_A, SBSCR_D
mov.l PSCR_A, r1
mov.w PSCR_D, r0
mov.w r0, @r1
write16 PSCR_A, PSCR_D
/* 0xA4520004 (Watchdog Control / Status Register) */
! mov.l RWTCSR_A, r1
/* 0xA507 -> timer_STOP/WDT_CLK=max */
! mov.w RWTCSR_D_1, r0
! mov.w r0, @r1
! write16 RWTCSR_A, RWTCSR_D_1 /* 0xA507 -> timer_STOP/WDT_CLK=max */
/* 0xA4520000 (Watchdog Count Register) */
mov.l RWTCNT_A, r1
/*0x5A00 -> Clear */
mov.w RWTCNT_D, r0
mov.w r0, @r1
write16 RWTCNT_A, RWTCNT_D /*0x5A00 -> Clear */
/* 0xA4520004 (Watchdog Control / Status Register) */
mov.l RWTCSR_A, r1
/* 0xA504 -> timer_STOP/CLK=500ms */
mov.w RWTCSR_D_2, r0
mov.w r0, @r1
write16 RWTCSR_A, RWTCSR_D_2 /* 0xA504 -> timer_STOP/CLK=500ms */
/* 0xA4150000 Frequency control register */
mov.l FRQCR_A, r1
mov.l FRQCR_D, r0 !
mov.l r0, @r1
write32 FRQCR_A, FRQCR_D
mov.l CCR_A, r1
mov.l CCR_D_2, r0
mov.l r0, @r1
write32 CCR_A, CCR_D_2
bsc_init:
mov.l PSELA_A, r1
mov.w PSELA_D, r0
mov.w r0, @r1
write16 PSELA_A, PSELA_D
mov.l DRVCR_A, r1
mov.w DRVCR_D, r0
mov.w r0, @r1
write16 DRVCR_A, DRVCR_D
mov.l PCCR_A, r1
mov.w PCCR_D, r0
mov.w r0, @r1
write16 PCCR_A, PCCR_D
mov.l PECR_A, r1
mov.w PECR_D, r0
mov.w r0, @r1
write16 PECR_A, PECR_D
mov.l PJCR_A, r1
mov.w PJCR_D, r0
mov.w r0, @r1
write16 PJCR_A, PJCR_D
mov.l PXCR_A, r1
mov.w PXCR_D, r0
mov.w r0, @r1
write16 PXCR_A, PXCR_D
mov.l CMNCR_A, r1 ! CMNCR address -> R1
mov.l CMNCR_D, r0 ! CMNCR data -> R0
mov.l r0, @r1 ! CMNCR set
write32 CMNCR_A, CMNCR_D
mov.l CS0BCR_A, r1 ! CS0BCR address -> R1
mov.l CS0BCR_D, r0 ! CS0BCR data -> R0
mov.l r0, @r1 ! CS0BCR set
write32 CS0BCR_A, CS0BCR_D
mov.l CS2BCR_A, r1 ! CS2BCR address -> R1
mov.l CS2BCR_D, r0 ! CS2BCR data -> R0
mov.l r0, @r1 ! CS2BCR set
write32 CS2BCR_A, CS2BCR_D
mov.l CS4BCR_A, r1 ! CS4BCR address -> R1
mov.l CS4BCR_D, r0 ! CS4BCR data -> R0
mov.l r0, @r1 ! CS4BCR set
write32 CS4BCR_A, CS4BCR_D
mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1
mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0
mov.l r0, @r1 ! CS5ABCR set
write32 CS5ABCR_A, CS5ABCR_D
mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1
mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0
mov.l r0, @r1 ! CS5BBCR set
write32 CS5BBCR_A, CS5BBCR_D
mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1
mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0
mov.l r0, @r1 ! CS6ABCR set
write32 CS6ABCR_A, CS6ABCR_D
mov.l CS0WCR_A, r1 ! CS0WCR address -> R1
mov.l CS0WCR_D, r0 ! CS0WCR data -> R0
mov.l r0, @r1 ! CS0WCR set
write32 CS0WCR_A, CS0WCR_D
mov.l CS2WCR_A, r1 ! CS2WCR address -> R1
mov.l CS2WCR_D, r0 ! CS2WCR data -> R0
mov.l r0, @r1 ! CS2WCR set
write32 CS2WCR_A, CS2WCR_D
mov.l CS4WCR_A, r1 ! CS4WCR address -> R1
mov.l CS4WCR_D, r0 ! CS4WCR data -> R0
mov.l r0, @r1 ! CS4WCR set
write32 CS4WCR_A, CS4WCR_D
mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1
mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0
mov.l r0, @r1 ! CS5AWCR set
write32 CS5AWCR_A, CS5AWCR_D
mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1
mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0
mov.l r0, @r1 ! CS5BWCR set
write32 CS5BWCR_A, CS5BWCR_D
mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1
mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0
mov.l r0, @r1 ! CS6AWCR set
write32 CS6AWCR_A, CS6AWCR_D
! SDRAM initialization
mov.l SDCR_A, r1 ! SB_SDCR address -> R1
mov.l SDCR_D, r0 ! SB_SDCR data -> R0
mov.l r0, @r1 ! SB_SDCR set
write32 SDCR_A, SDCR_D
mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1
mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0
mov.l r0, @r1 ! SB_SDWCR set
write32 SDWCR_A, SDWCR_D
mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1
mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0
mov.l r0, @r1 ! SB_SDPCR set
write32 SDPCR_A, SDPCR_D
mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1
mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0
mov.l r0, @r1 ! SB_RTCOR set
write32 RTCOR_A, RTCOR_D
mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1
mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0
mov.l r0, @r1 ! SB_RTCSR set
write32 RTCSR_A, RTCSR_D
mov.l SDMR3_A, r1 ! SDMR3 address -> R1
mov #0x00, r0 ! SDMR3 data -> R0
mov.b r0, @r1 ! SDMR3 set
write8 SDMR3_A, SDMR3_D
! BL bit off (init = ON) (?!?)
! BL bit off (init = ON) (?!?)
stc sr, r0 ! BL bit off(init=ON)
mov.l SR_MASK_D, r1
@ -232,28 +162,28 @@ MSTPCR0_D: .long 0x00001001
MSTPCR2_D: .long 0xffffffff
FRQCR_D: .long 0x07022538
PSELA_A: .long 0xa405014E
PSELA_D: .word 0x0A10
PSELA_A: .long 0xa405014E
PSELA_D: .word 0x0A10
.align 2
DRVCR_A: .long 0xa405018A
DRVCR_D: .word 0x0554
DRVCR_A: .long 0xa405018A
DRVCR_D: .word 0x0554
.align 2
PCCR_A: .long 0xa4050104
PCCR_D: .word 0x8800
PCCR_A: .long 0xa4050104
PCCR_D: .word 0x8800
.align 2
PECR_A: .long 0xa4050108
PECR_D: .word 0x0000
PECR_A: .long 0xa4050108
PECR_D: .word 0x0000
.align 2
PJCR_A: .long 0xa4050110
PJCR_D: .word 0x1000
PJCR_A: .long 0xa4050110
PJCR_D: .word 0x1000
.align 2
PXCR_A: .long 0xa4050148
PXCR_D: .word 0x0AAA
PXCR_A: .long 0xa4050148
PXCR_D: .word 0x0AAA
.align 2
CMNCR_A: .long CMNCR
@ -295,6 +225,7 @@ RTCOR_D: .long 0xA55A0034
RTCSR_A: .long SBSC_RTCSR
RTCSR_D: .long 0xA55A0010
SDMR3_A: .long 0xFE500180
SDMR3_D: .long 0x0
.align 1

125
board/ms7750se/lowlevel_init.S
View file

@ -29,120 +29,94 @@
#include <version.h>
#include <asm/processor.h>
#include <asm/macro.h>
#ifdef CONFIG_CPU_SH7751
#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
#ifdef CONFIG_MARUBUN_PCCARD
#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:6 A0B:7 */
#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:6 A0B:7 */
#else /* CONFIG_MARUBUN_PCCARD */
#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:6 A0B:7 */
#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:6 A0B:7 */
#endif /* CONFIG_MARUBUN_PCCARD */
#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
A2: 1-3 A1: 1-3 A0: 0-1 */
#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
A2: 1-3 A1: 1-3 A0: 0-1 */
#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */
#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
#else /* CONFIG_CPU_SH7751 */
#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:15 A0B:7 */
#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
A2: 1-3 A1: 1-3 A0: 0-1 */
#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:15 A0B:7 */
#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
A2: 1-3 A1: 1-3 A0: 0-1 */
#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */
#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
#endif /* CONFIG_CPU_SH7751 */
.global lowlevel_init
.text
.align 2
.align 2
lowlevel_init:
mov.l CCR_A, r1 ! CCR Address
mov.l CCR_D_DISABLE, r0 ! CCR Data
mov.l r0, @r1
write32 CCR_A, CCR_D_DISABLE
init_bsc:
mov.l FRQCR_A,r1 /* FRQCR Address */
mov.l FRQCR_D,r0 /* FRQCR Data */
mov.w r0,@r1
write16 FRQCR_A, FRQCR_D
mov.l BCR1_A,r1 /* BCR1 Address */
mov.l BCR1_D,r0 /* BCR1 Data */
mov.l r0,@r1
write32 BCR1_A, BCR1_D
mov.l BCR2_A,r1 /* BCR2 Address */
mov.l BCR2_D,r0 /* BCR2 Data */
mov.w r0,@r1
write16 BCR2_A, BCR2_D
mov.l WCR1_A,r1 /* WCR1 Address */
mov.l WCR1_D,r0 /* WCR1 Data */
mov.l r0,@r1
write32 WCR1_A, WCR1_D
mov.l WCR2_A,r1 /* WCR2 Address */
mov.l WCR2_D,r0 /* WCR2 Data */
mov.l r0,@r1
write32 WCR2_A, WCR2_D
mov.l WCR3_A,r1 /* WCR3 Address */
mov.l WCR3_D,r0 /* WCR3 Data */
mov.l r0,@r1
write32 WCR3_A, WCR3_D
mov.l MCR_A,r1 /* MCR Address */
mov.l MCR_D1,r0 /* MCR Data1 */
mov.l r0,@r1
write32 MCR_A, MCR_D1
mov.l SDMR3_A,r1 /* Set SDRAM mode */
mov #0,r0
mov.b r0,@r1
/* Set SDRAM mode */
write8 SDMR3_A, SDMR3_D
! Do you need PCMCIA setting?
! If so, please add the lines here...
mov.l RTCNT_A,r1 /* RTCNT Address */
mov.l RTCNT_D,r0 /* RTCNT Data */
mov.w r0,@r1
write16 RTCNT_A, RTCNT_D
mov.l RTCOR_A,r1 /* RTCOR Address */
mov.l RTCOR_D,r0 /* RTCOR Data */
mov.w r0,@r1
write16 RTCOR_A, RTCOR_D
mov.l RTCSR_A,r1 /* RTCSR Address */
mov.l RTCSR_D,r0 /* RTCSR Data */
mov.w r0,@r1
write16 RTCSR_A, RTCSR_D
write16 RFCR_A, RFCR_D
mov.l RFCR_A,r1 /* RFCR Address */
mov.l RFCR_D,r0 /* RFCR Data */
mov.w r0,@r1 /* Clear reflesh counter */
/* Wait DRAM refresh 30 times */
mov #30,r3
mov #30, r3
1:
mov.w @r1,r0
extu.w r0,r2
cmp/hi r3,r2
mov.w @r1, r0
extu.w r0, r2
cmp/hi r3, r2
bf 1b
mov.l MCR_A,r1 /* MCR Address */
mov.l MCR_D2,r0 /* MCR Data2 */
mov.l r0,@r1
write32 MCR_A, MCR_D2
mov.l SDMR3_A,r1 /* Set SDRAM mode */
mov #0,r0
mov.b r0,@r1
/* Set SDRAM mode */
write8 SDMR3_A, SDMR3_D
rts
nop
nop
.align 2
CCR_A: .long CCR
CCR_D_DISABLE: .long 0x0808
CCR_A: .long CCR
CCR_D_DISABLE: .long 0x0808
FRQCR_A: .long FRQCR
FRQCR_D:
#ifdef CONFIG_CPU_TYPE_R
@ -172,6 +146,7 @@ RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */
RTCOR_A: .long RTCOR
RTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */
SDMR3_A: .long SDMR3_ADDRESS
SDMR3_D: .long 0x00
MCR_A: .long MCR
MCR_D1: .long MCR_D1_VALUE
MCR_D2: .long MCR_D2_VALUE

2
board/pm854/pm854.c
View file

@ -150,7 +150,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {

2
board/pm856/pm856.c
View file

@ -306,7 +306,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
clkdiv = lbc->lcrr & 0x0f;
clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {

184
board/renesas/MigoR/lowlevel_init.S
View file

@ -1,5 +1,5 @@
/*
* Copyright (C) 2007
* Copyright (C) 2007-2008
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* Copyright (C) 2007
@ -27,13 +27,14 @@
#include <version.h>
#include <asm/processor.h>
#include <asm/macro.h>
/*
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
*
* (Note: As no stack is available, no subroutines can be called...).
* (Note: As no stack is available, no subroutines can be called...).
*/
.global lowlevel_init
@ -42,141 +43,83 @@
.align 2
lowlevel_init:
mov.l CCR_A, r1 ! Address of Cache Control Register
mov.l CCR_D, r0 ! Instruction Cache Invalidate
mov.l r0, @r1
write32 CCR_A, CCR_D ! Address of Cache Control Register
! Instruction Cache Invalidate
mov.l MMUCR_A, r1 ! Address of MMU Control Register
mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit
mov.l r0, @r1
write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register
! TI == TLB Invalidate bit
mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0
mov.l MSTPCR0_D, r0 !
mov.l r0, @r1
write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0
mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2
mov.l MSTPCR2_D, r0 !
mov.l r0, @r1
write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2
mov.l PFC_PULCR_A, r1
mov.w PFC_PULCR_D, r0
mov.w r0,@r1
write16 PFC_PULCR_A, PFC_PULCR_D
mov.l PFC_DRVCR_A, r1
mov.w PFC_DRVCR_D, r0
mov.w r0, @r1
write16 PFC_DRVCR_A, PFC_DRVCR_D
mov.l SBSCR_A, r1 !
mov.w SBSCR_D, r0 !
mov.w r0, @r1
write16 SBSCR_A, SBSCR_D
mov.l PSCR_A, r1 !
mov.w PSCR_D, r0 !
mov.w r0, @r1
write16 PSCR_A, PSCR_D
mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max
mov.w r0, @r1
write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register)
! 0xA507 -> timer_STOP / WDT_CLK = max
mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register)
mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear
mov.w r0, @r1
write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register)
! 0x5A00 -> Clear
mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms
mov.w r0, @r1
write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register)
! 0xA504 -> timer_STOP / CLK = 500ms
mov.l DLLFRQ_A, r1 ! 20080115
mov.l DLLFRQ_D, r0 ! 20080115
mov.l r0, @r1
write32 DLLFRQ_A, DLLFRQ_D ! 20080115
! 20080115
mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register
mov.l FRQCR_D, r0 ! 20080115
mov.l r0, @r1
write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register
! 20080115
mov.l CCR_A, r1 ! Address of Cache Control Register
mov.l CCR_D_2, r0 ! ??
mov.l r0, @r1
write32 CCR_A, CCR_D_2 ! Address of Cache Control Register
! ??
bsc_init:
mov.l CMNCR_A, r1 ! CMNCR address -> R1
mov.l CMNCR_D, r0 ! CMNCR data -> R0
mov.l r0, @r1 ! CMNCR set
write32 CMNCR_A, CMNCR_D
mov.l CS0BCR_A, r1 ! CS0BCR address -> R1
mov.l CS0BCR_D, r0 ! CS0BCR data -> R0
mov.l r0, @r1 ! CS0BCR set
write32 CS0BCR_A, CS0BCR_D
mov.l CS4BCR_A, r1 ! CS4BCR address -> R1
mov.l CS4BCR_D, r0 ! CS4BCR data -> R0
mov.l r0, @r1 ! CS4BCR set
write32 CS4BCR_A, CS4BCR_D
mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1
mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0
mov.l r0, @r1 ! CS5ABCR set
write32 CS5ABCR_A, CS5ABCR_D
mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1
mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0
mov.l r0, @r1 ! CS5BBCR set
write32 CS5BBCR_A, CS5BBCR_D
mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1
mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0
mov.l r0, @r1 ! CS6ABCR set
write32 CS6ABCR_A, CS6ABCR_D
mov.l CS0WCR_A, r1 ! CS0WCR address -> R1
mov.l CS0WCR_D, r0 ! CS0WCR data -> R0
mov.l r0, @r1 ! CS0WCR set
write32 CS0WCR_A, CS0WCR_D
mov.l CS4WCR_A, r1 ! CS4WCR address -> R1
mov.l CS4WCR_D, r0 ! CS4WCR data -> R0
mov.l r0, @r1 ! CS4WCR set
write32 CS4WCR_A, CS4WCR_D
mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1
mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0
mov.l r0, @r1 ! CS5AWCR set
write32 CS5AWCR_A, CS5AWCR_D
mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1
mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0
mov.l r0, @r1 ! CS5BWCR set
write32 CS5BWCR_A, CS5BWCR_D
mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1
mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0
mov.l r0, @r1 ! CS6AWCR set
write32 CS6AWCR_A, CS6AWCR_D
! SDRAM initialization
mov.l SDCR_A, r1 ! SB_SDCR address -> R1
mov.l SDCR_D, r0 ! SB_SDCR data -> R0
mov.l r0, @r1 ! SB_SDCR set
write32 SDCR_A, SDCR_D
mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1
mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0
mov.l r0, @r1 ! SB_SDWCR set
write32 SDWCR_A, SDWCR_D
mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1
mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0
mov.l r0, @r1 ! SB_SDPCR set
write32 SDPCR_A, SDPCR_D
mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1
mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0
mov.l r0, @r1 ! SB_RTCOR set
write32 RTCOR_A, RTCOR_D
mov.l RTCNT_A, r1 ! SB_RTCNT address -> R1
mov.l RTCNT_D, r0 ! SB_RTCNT data -> R0
mov.l r0, @r1
write32 RTCNT_A, RTCNT_D
mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1
mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0
mov.l r0, @r1 ! SB_RTCSR set
write32 RTCSR_A, RTCSR_D
mov.l RFCR_A, r1 ! SB_RFCR address -> R1
mov.l RFCR_D, r0 ! SB_RFCR data -> R0
mov.l r0, @r1
write32 RFCR_A, RFCR_D
mov.l SDMR3_A, r1 ! SDMR3 address -> R1
mov #0x00, r0 ! SDMR3 data -> R0
mov.b r0, @r1 ! SDMR3 set
write8 SDMR3_A, SDMR3_D
! BL bit off (init = ON) (?!?)
! BL bit off (init = ON) (?!?)
stc sr, r0 ! BL bit off(init=ON)
mov.l SR_MASK_D, r1
@ -211,25 +154,25 @@ PFC_PULCR_D: .long 0x6000
PFC_DRVCR_D: .long 0x0464
FRQCR_D: .long 0x07033639
PLLCR_D: .long 0x00005000
DLLFRQ_D: .long 0x000004F6 ! 20080115
DLLFRQ_D: .long 0x000004F6
CMNCR_A: .long CMNCR
CMNCR_D: .long 0x0000001B ! 20080115
CS0BCR_A: .long CS0BCR ! Flash bank 1
CMNCR_D: .long 0x0000001B
CS0BCR_A: .long CS0BCR
CS0BCR_D: .long 0x24920400
CS4BCR_A: .long CS4BCR !
CS4BCR_D: .long 0x10003400 ! 20080115
CS5ABCR_A: .long CS5ABCR !
CS4BCR_A: .long CS4BCR
CS4BCR_D: .long 0x00003400
CS5ABCR_A: .long CS5ABCR
CS5ABCR_D: .long 0x24920400
CS5BBCR_A: .long CS5BBCR !
CS5BBCR_A: .long CS5BBCR
CS5BBCR_D: .long 0x24920400
CS6ABCR_A: .long CS6ABCR !
CS6ABCR_A: .long CS6ABCR
CS6ABCR_D: .long 0x24920400
CS0WCR_A: .long CS0WCR
CS0WCR_D: .long 0x00000380
CS4WCR_A: .long CS4WCR
CS4WCR_D: .long 0x00100A81 ! 20080115
CS4WCR_D: .long 0x00110080
CS5AWCR_A: .long CS5AWCR
CS5AWCR_D: .long 0x00000300
CS5BWCR_A: .long CS5BWCR
@ -238,20 +181,21 @@ CS6AWCR_A: .long CS6AWCR
CS6AWCR_D: .long 0x00000300
SDCR_A: .long SBSC_SDCR
SDCR_D: .long 0x80160809 ! 20080115
SDCR_D: .long 0x80160809
SDWCR_A: .long SBSC_SDWCR
SDWCR_D: .long 0x0014450C ! 20080115
SDWCR_D: .long 0x0014450C
SDPCR_A: .long SBSC_SDPCR
SDPCR_D: .long 0x00000087
RTCOR_A: .long SBSC_RTCOR
RTCNT_A: .long SBSC_RTCNT
RTCNT_D: .long 0xA55A0012
RTCOR_D: .long 0xA55A001C ! 20080115
RTCOR_D: .long 0xA55A001C
RTCSR_A: .long SBSC_RTCSR
RFCR_A: .long SBSC_RFCR
RFCR_D: .long 0xA55A0221
RTCSR_D: .long 0xA55A009a ! 20080115
SDMR3_A: .long 0xFE581180 ! 20080115
RTCSR_D: .long 0xA55A009a
SDMR3_A: .long 0xFE581180
SDMR3_D: .long 0x0
SR_MASK_D: .long 0xEFFFFF0F
@ -260,5 +204,5 @@ SR_MASK_D: .long 0xEFFFFF0F
SBSCR_D: .word 0x0044
PSCR_D: .word 0x0000
RWTCSR_D_1: .word 0xA507
RWTCSR_D_2: .word 0xA504 ! 20080115
RWTCSR_D_2: .word 0xA504
RWTCNT_D: .word 0x5A00

125
board/renesas/ap325rxa/lowlevel_init.S
View file

@ -23,6 +23,7 @@
#include <config.h>
#include <version.h>
#include <asm/processor.h>
#include <asm/macro.h>
/*
* Board specific low level init code, called _very_ early in the
@ -38,113 +39,59 @@
.align 2
lowlevel_init:
mov.l DRVCRA_A, r1
mov.l DRVCRA_D, r0
mov.w r0, @r1
write16 DRVCRA_A, DRVCRA_D
mov.l DRVCRB_A, r1
mov.l DRVCRB_D, r0
mov.w r0, @r1
write16 DRVCRB_A, DRVCRB_D
mov.l RWTCSR_A, r1
mov.l RWTCSR_D1, r0
mov.w r0, @r1
write16 RWTCSR_A, RWTCSR_D1
mov.l RWTCNT_A, r1
mov.l RWTCNT_D, r0
mov.w r0, @r1
write16 RWTCNT_A, RWTCNT_D
mov.l RWTCSR_A, r1
mov.l RWTCSR_D2, r0
mov.w r0, @r1
write16 RWTCSR_A, RWTCSR_D2
mov.l FRQCR_A, r1
mov.l FRQCR_D, r0
mov.l r0, @r1
write32 FRQCR_A, FRQCR_D
mov.l CMNCR_A, r1
mov.l CMNCR_D, r0
mov.l r0, @r1
write32 CMNCR_A, CMNCR_D
mov.l CS0BCR_A ,r1
mov.l CS0BCR_D ,r0
mov.l r0, @r1
write32 CS0BCR_A, CS0BCR_D
mov.l CS4BCR_A ,r1
mov.l CS4BCR_D ,r0
mov.l r0, @r1
write32 CS4BCR_A, CS4BCR_D
mov.l CS5ABCR_A ,r1
mov.l CS5ABCR_D ,r0
mov.l r0, @r1
write32 CS5ABCR_A, CS5ABCR_D
mov.l CS5BBCR_A ,r1
mov.l CS5BBCR_D ,r0
mov.l r0, @r1
write32 CS5BBCR_A, CS5BBCR_D
mov.l CS6ABCR_A ,r1
mov.l CS6ABCR_D ,r0
mov.l r0, @r1
write32 CS6ABCR_A, CS6ABCR_D
mov.l CS6BBCR_A ,r1
mov.l CS6BBCR_D ,r0
mov.l r0, @r1
write32 CS6BBCR_A, CS6BBCR_D
mov.l CS0WCR_A ,r1
mov.l CS0WCR_D ,r0
mov.l r0, @r1
write32 CS0WCR_A, CS0WCR_D
mov.l CS4WCR_A ,r1
mov.l CS4WCR_D ,r0
mov.l r0, @r1
write32 CS4WCR_A, CS4WCR_D
mov.l CS5AWCR_A ,r1
mov.l CS5AWCR_D ,r0
mov.l r0, @r1
write32 CS5AWCR_A, CS5AWCR_D
mov.l CS5BWCR_A ,r1
mov.l CS5BWCR_D ,r0
mov.l r0, @r1
write32 CS5BWCR_A, CS5BWCR_D
mov.l CS6AWCR_A ,r1
mov.l CS6AWCR_D ,r0
mov.l r0, @r1
write32 CS6AWCR_A, CS6AWCR_D
mov.l CS6BWCR_A ,r1
mov.l CS6BWCR_D ,r0
mov.l r0, @r1
write32 CS6BWCR_A, CS6BWCR_D
mov.l SBSC_SDCR_A, r1
mov.l SBSC_SDCR_D1, r0
mov.l r0, @r1
write32 SBSC_SDCR_A, SBSC_SDCR_D1
mov.l SBSC_SDWCR_A, r1
mov.l SBSC_SDWCR_D, r0
mov.l r0, @r1
write32 SBSC_SDWCR_A, SBSC_SDWCR_D
mov.l SBSC_SDPCR_A, r1
mov.l SBSC_SDPCR_D, r0
mov.l r0, @r1
write32 SBSC_SDPCR_A, SBSC_SDPCR_D
mov.l SBSC_RTCSR_A, r1
mov.l SBSC_RTCSR_D, r0
mov.l r0, @r1
write32 SBSC_RTCSR_A, SBSC_RTCSR_D
mov.l SBSC_RTCNT_A, r1
mov.l SBSC_RTCNT_D, r0
mov.l r0, @r1
write32 SBSC_RTCNT_A, SBSC_RTCNT_D
mov.l SBSC_RTCOR_A, r1
mov.l SBSC_RTCOR_D, r0
mov.l r0, @r1
write32 SBSC_RTCOR_A, SBSC_RTCOR_D
mov.l SBSC_SDMR3_A1, r1
mov.l SBSC_SDMR3_D, r0
mov.b r0, @r1
write8 SBSC_SDMR3_A1, SBSC_SDMR3_D
mov.l SBSC_SDMR3_A2, r1
mov.l SBSC_SDMR3_D, r0
mov.b r0, @r1
write8 SBSC_SDMR3_A2, SBSC_SDMR3_D
mov.l SLEEP_CNT, r1
2: tst r1, r1
@ -152,19 +99,13 @@ lowlevel_init:
bf/s 2b
dt r1
mov.l SBSC_SDMR3_A3, r1
mov.l SBSC_SDMR3_D, r0
mov.b r0, @r1
write8 SBSC_SDMR3_A3, SBSC_SDMR3_D
mov.l SBSC_SDCR_A, r1
mov.l SBSC_SDCR_D2, r0
mov.l r0, @r1
write32 SBSC_SDCR_A, SBSC_SDCR_D2
mov.l CCR_A, r1
mov.l CCR_D, r0
mov.l r0, @r1
write32 CCR_A, CCR_D
! BL bit off (init = ON) (?!?)
! BL bit off (init = ON) (?!?)
stc sr, r0 ! BL bit off(init=ON)
mov.l SR_MASK_D, r1
@ -211,7 +152,7 @@ SBSC_SDMR3_D: .long 0x00
CMNCR_A: .long CMNCR
CS0BCR_A: .long CS0BCR
CS4BCR_A: .long CS4BCR
CS5ABCR_A: .long CS5ABCR
CS5ABCR_A: .long CS5ABCR
CS5BBCR_A: .long CS5BBCR
CS6ABCR_A: .long CS6ABCR
CS6BBCR_A: .long CS6BBCR

141
board/renesas/r2dplus/lowlevel_init.S
View file

@ -8,105 +8,64 @@
#include <version.h>
#include <asm/processor.h>
#include <asm/macro.h>
.global lowlevel_init
.text
.align 2
.align 2
lowlevel_init:
mov.l CCR_A, r1
mov.l CCR_D_D, r0
mov.l r0,@r1
write32 CCR_A, CCR_D_D
mov.l MMUCR_A,r1
mov.l MMUCR_D,r0
mov.w r0,@r1
write32 MMUCR_A, MMUCR_D
mov.l BCR1_A,r1
mov.l BCR1_D,r0
mov.l r0,@r1
write32 BCR1_A, BCR1_D
mov.l BCR2_A,r1
mov.l BCR2_D,r0
mov.w r0,@r1
write16 BCR2_A, BCR2_D
mov.l BCR3_A,r1
mov.l BCR3_D,r0
mov.w r0,@r1
write16 BCR3_A, BCR3_D
mov.l BCR4_A,r1
mov.l BCR4_D,r0
mov.l r0,@r1
write32 BCR4_A, BCR4_D
mov.l WCR1_A,r1
mov.l WCR1_D,r0
mov.l r0,@r1
write32 WCR1_A, WCR1_D
mov.l WCR2_A,r1
mov.l WCR2_D,r0
mov.l r0,@r1
write32 WCR2_A, WCR2_D
mov.l WCR3_A,r1
mov.l WCR3_D,r0
mov.l r0,@r1
write32 WCR3_A, WCR3_D
mov.l PCR_A,r1
mov.l PCR_D,r0
mov.w r0,@r1
write16 PCR_A, PCR_D
mov.l LED_A,r1
mov #0xff,r0
mov.w r0,@r1
write16 LED_A, LED_D
mov.l MCR_A,r1
mov.l MCR_D1,r0
mov.l r0,@r1
write32 MCR_A, MCR_D1
mov.l RTCNT_A,r1
mov.l RTCNT_D,r0
mov.w r0,@r1
write16 RTCNT_A, RTCNT_D
mov.l RTCOR_A,r1
mov.l RTCOR_D,r0
mov.w r0,@r1
write16 RTCOR_A, RTCOR_D
mov.l RFCR_A,r1
mov.l RFCR_D,r0
mov.w r0,@r1
write16 RFCR_A, RFCR_D
mov.l RTCSR_A,r1
mov.l RTCSR_D,r0
mov.w r0,@r1
write16 RTCSR_A, RTCSR_D
mov.l SDMR3_A,r1
mov #0x55,r0
mov.b r0,@r1
write8 SDMR3_A, SDMR3_D0
/* Wait DRAM refresh 30 times */
mov.l RFCR_A,r1
mov #30,r3
mov.l RFCR_A, r1
mov #30, r3
1:
mov.w @r1,r0
extu.w r0,r2
cmp/hi r3,r2
mov.w @r1, r0
extu.w r0, r2
cmp/hi r3, r2
bf 1b
mov.l MCR_A,r1
mov.l MCR_D2,r0
mov.l r0,@r1
write32 MCR_A, MCR_D2
mov.l SDMR3_A,r1
mov #0,r0
mov.b r0,@r1
write8 SDMR3_A, SDMR3_D1
mov.l IRLMASK_A,r1
mov.l IRLMASK_D,r0
mov.l r0,@r1
write32 IRLMASK_A, IRLMASK_D
mov.l CCR_A, r1
mov.l CCR_D_E, r0
mov.l r0, @r1
write32 CCR_A, CCR_D_E
rts
nop
@ -118,34 +77,36 @@ CCR_D_E: .long 0x8000090B
FRQCR_A: .long FRQCR /* FRQCR Address */
FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */
BCR1_A: .long BCR1 /* BCR1 Address */
BCR1_D: .long 0x00180008
BCR2_A: .long BCR2 /* BCR2 Address */
BCR2_D: .long 0xabe8
BCR3_A: .long BCR3 /* BCR3 Address */
BCR3_D: .long 0x0000
BCR4_A: .long BCR4 /* BCR4 Address */
BCR4_D: .long 0x00000010
WCR1_A: .long WCR1 /* WCR1 Address */
WCR1_D: .long 0x33343333
WCR2_A: .long WCR2 /* WCR2 Address */
WCR2_D: .long 0xcff86fbf
WCR3_A: .long WCR3 /* WCR3 Address */
WCR3_D: .long 0x07777707
BCR1_A: .long BCR1 /* BCR1 Address */
BCR1_D: .long 0x00180008
BCR2_A: .long BCR2 /* BCR2 Address */
BCR2_D: .long 0xabe8
BCR3_A: .long BCR3 /* BCR3 Address */
BCR3_D: .long 0x0000
BCR4_A: .long BCR4 /* BCR4 Address */
BCR4_D: .long 0x00000010
WCR1_A: .long WCR1 /* WCR1 Address */
WCR1_D: .long 0x33343333
WCR2_A: .long WCR2 /* WCR2 Address */
WCR2_D: .long 0xcff86fbf
WCR3_A: .long WCR3 /* WCR3 Address */
WCR3_D: .long 0x07777707
LED_A: .long 0x04000036 /* LED Address */
LED_D: .long 0xFF /* LED Data */
RTCNT_A: .long RTCNT /* RTCNT Address */
RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */
RTCOR_A: .long RTCOR /* RTCOR Address */
RTCOR_D: .long 0xA534 /* RTCOR Write Code */
RTCOR_D: .long 0xA534 /* RTCOR Write Code */
RTCSR_A: .long RTCSR /* RTCSR Address */
RTCSR_D: .long 0xA510 /* RTCSR Write Code */
SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */
SDMR3_D: .long 0x55
SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */
SDMR3_D0: .long 0x55
SDMR3_D1: .long 0x00
MCR_A: .long MCR /* MCR Address */
MCR_D1: .long 0x081901F4 /* MRSET:'0' */
MCR_D2: .long 0x481901F4 /* MRSET:'1' */
RFCR_A: .long RFCR /* RFCR Address */
RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */
MCR_D1: .long 0x081901F4 /* MRSET:'0' */
MCR_D2: .long 0x481901F4 /* MRSET:'1' */
RFCR_A: .long RFCR /* RFCR Address */
RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */
PCR_A: .long PCR /* PCR Address */
PCR_D: .long 0x0000
MMUCR_A: .long MMUCR /* MMUCCR Address */

392
board/renesas/r7780mp/lowlevel_init.S
View file

@ -22,13 +22,14 @@
#include <config.h>
#include <version.h>
#include <asm/processor.h>
#include <asm/macro.h>
/*
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
*
* (Note: As no stack is available, no subroutines can be called...).
* (Note: As no stack is available, no subroutines can be called...).
*/
.global lowlevel_init
@ -38,63 +39,36 @@
lowlevel_init:
mov.l CCR_A, r1 /* Address of Cache Control Register */
mov.l CCR_D, r0 /* Instruction Cache Invalidate */
mov.l r0, @r1
write32 CCR_A, CCR_D /* Address of Cache Control Register */
/* Instruction Cache Invalidate */
mov.l FRQCR_A, r1 /* Frequency control register */
mov.l FRQCR_D, r0
mov.l r0, @r1
write32 FRQCR_A, FRQCR_D /* Frequency control register */
/* pin_multi_setting */
mov.l BBG_PMMR_A,r1
mov.l BBG_PMMR_D_PMSR1,r0
mov.l r0,@r1
write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1
mov.l BBG_PMSR1_A,r1
mov.l BBG_PMSR1_D,r0
mov.l r0,@r1
write32 BBG_PMSR1_A, BBG_PMSR1_D
mov.l BBG_PMMR_A,r1
mov.l BBG_PMMR_D_PMSR2,r0
mov.l r0,@r1
write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2
mov.l BBG_PMSR2_A,r1
mov.l BBG_PMSR2_D,r0
mov.l r0,@r1
write32 BBG_PMSR2_A, BBG_PMSR2_D
mov.l BBG_PMMR_A,r1
mov.l BBG_PMMR_D_PMSR3,r0
mov.l r0,@r1
write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3
mov.l BBG_PMSR3_A,r1
mov.l BBG_PMSR3_D,r0
mov.l r0,@r1
write32 BBG_PMSR3_A, BBG_PMSR3_D
mov.l BBG_PMMR_A,r1
mov.l BBG_PMMR_D_PMSR4,r0
mov.l r0,@r1
write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4
mov.l BBG_PMSR4_A,r1
mov.l BBG_PMSR4_D,r0
mov.l r0,@r1
write32 BBG_PMSR4_A, BBG_PMSR4_D
mov.l BBG_PMMR_A,r1
mov.l BBG_PMMR_D_PMSRG,r0
mov.l r0,@r1
write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG
mov.l BBG_PMSRG_A,r1
mov.l BBG_PMSRG_D,r0
mov.l r0,@r1
write32 BBG_PMSRG_A, BBG_PMSRG_D
/* cpg_setting */
mov.l FRQCR_A,r1
mov.l FRQCR_D,r0
mov.l r0,@r1
write32 FRQCR_A, FRQCR_D
mov.l DLLCSR_A,r1
mov.l DLLCSR_D,r0
mov.l r0,@r1
write32 DLLCSR_A, DLLCSR_D
nop
nop
@ -108,111 +82,79 @@ lowlevel_init:
nop
/* wait 200us */
mov.l REPEAT0_R3,r3
mov #0,r2
mov.l REPEAT0_R3, r3
mov #0, r2
repeat0:
add #1,r2
cmp/hs r3,r2
bf repeat0
add #1, r2
cmp/hs r3, r2
bf repeat0
nop
/* bsc_setting */
mov.l MMSELR_A,r1
mov.l MMSELR_D,r0
mov.l r0,@r1
write32 MMSELR_A, MMSELR_D
mov.l BCR_A,r1
mov.l BCR_D,r0
mov.l r0,@r1
write32 BCR_A, BCR_D
mov.l CS0BCR_A,r1
mov.l CS0BCR_D,r0
mov.l r0,@r1
write32 CS0BCR_A, CS0BCR_D
mov.l CS1BCR_A,r1
mov.l CS1BCR_D,r0
mov.l r0,@r1
write32 CS1BCR_A, CS1BCR_D
mov.l CS2BCR_A,r1
mov.l CS2BCR_D,r0
mov.l r0,@r1
write32 CS2BCR_A, CS2BCR_D
mov.l CS4BCR_A,r1
mov.l CS4BCR_D,r0
mov.l r0,@r1
write32 CS4BCR_A, CS4BCR_D
mov.l CS5BCR_A,r1
mov.l CS5BCR_D,r0
mov.l r0,@r1
write32 CS5BCR_A, CS5BCR_D
mov.l CS6BCR_A,r1
mov.l CS6BCR_D,r0
mov.l r0,@r1
write32 CS6BCR_A, CS6BCR_D
mov.l CS0WCR_A,r1
mov.l CS0WCR_D,r0
mov.l r0,@r1
write32 CS0WCR_A, CS0WCR_D
mov.l CS1WCR_A,r1
mov.l CS1WCR_D,r0
mov.l r0,@r1
write32 CS1WCR_A, CS1WCR_D
mov.l CS2WCR_A,r1
mov.l CS2WCR_D,r0
mov.l r0,@r1
write32 CS2WCR_A, CS2WCR_D
mov.l CS4WCR_A,r1
mov.l CS4WCR_D,r0
mov.l r0,@r1
write32 CS4WCR_A, CS4WCR_D
mov.l CS5WCR_A,r1
mov.l CS5WCR_D,r0
mov.l r0,@r1
write32 CS5WCR_A, CS5WCR_D
mov.l CS6WCR_A,r1
mov.l CS6WCR_D,r0
mov.l r0,@r1
write32 CS6WCR_A, CS6WCR_D
mov.l CS5PCR_A,r1
mov.l CS5PCR_D,r0
mov.l r0,@r1
write32 CS5PCR_A, CS5PCR_D
mov.l CS6PCR_A,r1
mov.l CS6PCR_D,r0
mov.l r0,@r1
write32 CS6PCR_A, CS6PCR_D
/* ddr_setting */
/* wait 200us */
mov.l REPEAT0_R3,r3
mov #0,r2
mov.l REPEAT0_R3, r3
mov #0, r2
repeat1:
add #1,r2
cmp/hs r3,r2
bf repeat1
add #1, r2
cmp/hs r3, r2
bf repeat1
nop
mov.l MIM_U_A,r0
mov.l MIM_U_D,r1
mov.l MIM_U_A, r0
mov.l MIM_U_D, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
mov.l MIM_L_A,r0
mov.l MIM_L_D0,r1
mov.l MIM_L_A, r0
mov.l MIM_L_D0, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
mov.l STR_L_A,r0
mov.l STR_L_D,r1
mov.l STR_L_A, r0
mov.l STR_L_D, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
mov.l SDR_L_A,r0
mov.l SDR_L_D,r1
mov.l SDR_L_A, r0
mov.l SDR_L_D, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
nop
@ -220,193 +162,193 @@ repeat1:
nop
nop
mov.l SCR_L_A,r0
mov.l SCR_L_D0,r1
mov.l SCR_L_A, r0
mov.l SCR_L_D0, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
mov.l SCR_L_A,r0
mov.l SCR_L_D1,r1
mov.l SCR_L_A, r0
mov.l SCR_L_D1, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
nop
nop
nop
mov.l EMRS_A,r0
mov.l EMRS_D,r1
mov.l EMRS_A, r0
mov.l EMRS_D, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
nop
nop
nop
mov.l MRS1_A,r0
mov.l MRS1_D,r1
mov.l MRS1_A, r0
mov.l MRS1_D, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
nop
nop
nop
mov.l SCR_L_A,r0
mov.l SCR_L_D2,r1
mov.l SCR_L_A, r0
mov.l SCR_L_D2, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
nop
nop
nop
mov.l SCR_L_A,r0
mov.l SCR_L_D3,r1
mov.l SCR_L_A, r0
mov.l SCR_L_D3, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
nop
nop
nop
mov.l SCR_L_A,r0
mov.l SCR_L_D4,r1
mov.l SCR_L_A, r0
mov.l SCR_L_D4, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
nop
nop
nop
mov.l MRS2_A,r0
mov.l MRS2_D,r1
mov.l MRS2_A, r0
mov.l MRS2_D, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
nop
nop
nop
mov.l SCR_L_A,r0
mov.l SCR_L_D5,r1
mov.l SCR_L_A, r0
mov.l SCR_L_D5, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
/* wait 200us */
mov.l REPEAT0_R1,r3
mov #0,r2
mov.l REPEAT0_R1, r3
mov #0, r2
repeat2:
add #1,r2
cmp/hs r3,r2
bf repeat2
add #1, r2
cmp/hs r3, r2
bf repeat2
synco
mov.l MIM_L_A,r0
mov.l MIM_L_D1,r1
mov.l MIM_L_A, r0
mov.l MIM_L_D1, r1
synco
mov.l r1,@r0
mov.l r1, @r0
synco
rts
nop
.align 4
RWTCSR_D_1: .word 0xA507
RWTCSR_D_2: .word 0xA507
RWTCNT_D: .word 0x5A00
RWTCSR_D_1: .word 0xA507
RWTCSR_D_2: .word 0xA507
RWTCNT_D: .word 0x5A00
.align 2
BBG_PMMR_A: .long 0xFF800010
BBG_PMSR1_A: .long 0xFF800014
BBG_PMSR2_A: .long 0xFF800018
BBG_PMSR3_A: .long 0xFF80001C
BBG_PMSR4_A: .long 0xFF800020
BBG_PMSRG_A: .long 0xFF800024
BBG_PMMR_A: .long 0xFF800010
BBG_PMSR1_A: .long 0xFF800014
BBG_PMSR2_A: .long 0xFF800018
BBG_PMSR3_A: .long 0xFF80001C
BBG_PMSR4_A: .long 0xFF800020
BBG_PMSRG_A: .long 0xFF800024
BBG_PMMR_D_PMSR1: .long 0xffffbffd
BBG_PMSR1_D: .long 0x00004002
BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
BBG_PMSR2_D: .long 0x03de5800
BBG_PMMR_D_PMSR3: .long 0xfffffff8
BBG_PMSR3_D: .long 0x00000007
BBG_PMMR_D_PMSR4: .long 0xdffdfff9
BBG_PMSR4_D: .long 0x20020006
BBG_PMMR_D_PMSRG: .long 0xffffffff
BBG_PMSRG_D: .long 0x00000000
BBG_PMMR_D_PMSR1: .long 0xffffbffd
BBG_PMSR1_D: .long 0x00004002
BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
BBG_PMSR2_D: .long 0x03de5800
BBG_PMMR_D_PMSR3: .long 0xfffffff8
BBG_PMSR3_D: .long 0x00000007
BBG_PMMR_D_PMSR4: .long 0xdffdfff9
BBG_PMSR4_D: .long 0x20020006
BBG_PMMR_D_PMSRG: .long 0xffffffff
BBG_PMSRG_D: .long 0x00000000
FRQCR_A: .long FRQCR
DLLCSR_A: .long 0xffc40010
FRQCR_D: .long 0x40233035
DLLCSR_D: .long 0x00000000
FRQCR_A: .long FRQCR
DLLCSR_A: .long 0xffc40010
FRQCR_D: .long 0x40233035
DLLCSR_D: .long 0x00000000
/* for DDR-SDRAM */
MIM_U_A: .long MIM_1
MIM_L_A: .long MIM_2
SCR_U_A: .long SCR_1
SCR_L_A: .long SCR_2
STR_U_A: .long STR_1
STR_L_A: .long STR_2
SDR_U_A: .long SDR_1
SDR_L_A: .long SDR_2
MIM_U_A: .long MIM_1
MIM_L_A: .long MIM_2
SCR_U_A: .long SCR_1
SCR_L_A: .long SCR_2
STR_U_A: .long STR_1
STR_L_A: .long STR_2
SDR_U_A: .long SDR_1
SDR_L_A: .long SDR_2
EMRS_A: .long 0xFEC02000
MRS1_A: .long 0xFEC00B08
MRS2_A: .long 0xFEC00308
EMRS_A: .long 0xFEC02000
MRS1_A: .long 0xFEC00B08
MRS2_A: .long 0xFEC00308
MIM_U_D: .long 0x00004000
MIM_L_D0: .long 0x03e80009
MIM_L_D1: .long 0x03e80209
SCR_L_D0: .long 0x3
SCR_L_D1: .long 0x2
SCR_L_D2: .long 0x2
SCR_L_D3: .long 0x4
SCR_L_D4: .long 0x4
SCR_L_D5: .long 0x0
STR_L_D: .long 0x000f0000
SDR_L_D: .long 0x00000400
EMRS_D: .long 0x0
MRS1_D: .long 0x0
MRS2_D: .long 0x0
MIM_U_D: .long 0x00004000
MIM_L_D0: .long 0x03e80009
MIM_L_D1: .long 0x03e80209
SCR_L_D0: .long 0x3
SCR_L_D1: .long 0x2
SCR_L_D2: .long 0x2
SCR_L_D3: .long 0x4
SCR_L_D4: .long 0x4
SCR_L_D5: .long 0x0
STR_L_D: .long 0x000f0000
SDR_L_D: .long 0x00000400
EMRS_D: .long 0x0
MRS1_D: .long 0x0
MRS2_D: .long 0x0
/* Cache Controller */
CCR_A: .long CCR
MMUCR_A: .long MMUCR
RWTCNT_A: .long WTCNT
CCR_A: .long CCR
MMUCR_A: .long MMUCR
RWTCNT_A: .long WTCNT
CCR_D: .long 0x0000090b
CCR_D_2: .long 0x00000103
MMUCR_D: .long 0x00000004
MSTPCR0_D: .long 0x00001001
MSTPCR2_D: .long 0xffffffff
CCR_D: .long 0x0000090b
CCR_D_2: .long 0x00000103
MMUCR_D: .long 0x00000004
MSTPCR0_D: .long 0x00001001
MSTPCR2_D: .long 0xffffffff
/* local Bus State Controller */
MMSELR_A: .long MMSELR
BCR_A: .long BCR
CS0BCR_A: .long CS0BCR
CS1BCR_A: .long CS1BCR
CS2BCR_A: .long CS2BCR
CS4BCR_A: .long CS4BCR
CS5BCR_A: .long CS5BCR
CS6BCR_A: .long CS6BCR
CS0WCR_A: .long CS0WCR
CS1WCR_A: .long CS1WCR
CS2WCR_A: .long CS2WCR
CS4WCR_A: .long CS4WCR
CS5WCR_A: .long CS5WCR
CS6WCR_A: .long CS6WCR
CS5PCR_A: .long CS5PCR
CS6PCR_A: .long CS6PCR
MMSELR_A: .long MMSELR
BCR_A: .long BCR
CS0BCR_A: .long CS0BCR
CS1BCR_A: .long CS1BCR
CS2BCR_A: .long CS2BCR
CS4BCR_A: .long CS4BCR
CS5BCR_A: .long CS5BCR
CS6BCR_A: .long CS6BCR
CS0WCR_A: .long CS0WCR
CS1WCR_A: .long CS1WCR
CS2WCR_A: .long CS2WCR
CS4WCR_A: .long CS4WCR
CS5WCR_A: .long CS5WCR
CS6WCR_A: .long CS6WCR
CS5PCR_A: .long CS5PCR
CS6PCR_A: .long CS6PCR
MMSELR_D: .long 0xA5A50003
BCR_D: .long 0x00000000
@ -425,5 +367,5 @@ CS6WCR_D: .long 0x77777703
CS5PCR_D: .long 0x77000000
CS6PCR_D: .long 0x77000000
REPEAT0_R3: .long 0x00002000
REPEAT0_R1: .long 0x0000200
REPEAT0_R3: .long 0x00002000
REPEAT0_R1: .long 0x0000200

4
board/renesas/rsk7203/Makefile
View file

@ -26,6 +26,10 @@ LIB = lib$(BOARD).a
OBJS := rsk7203.o
SOBJS := lowlevel_init.o
LIB := $(addprefix $(obj),$(LIB))
OBJS := $(addprefix $(obj),$(OBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)

151
board/renesas/rsk7203/lowlevel_init.S
View file

@ -21,6 +21,7 @@
#include <version.h>
#include <asm/processor.h>
#include <asm/macro.h>
.global lowlevel_init
@ -29,153 +30,89 @@
lowlevel_init:
/* Cache setting */
mov.l CCR1_A ,r1
mov.l CCR1_D ,r0
mov.l r0,@r1
write32 CCR1_A ,CCR1_D
/* ConfigurePortPins */
mov.l PECRL3_A, r1
mov.l PECRL3_D, r0
mov.w r0,@r1
write16 PECRL3_A, PECRL3_D
mov.l PCCRL4_A, r1
mov.l PCCRL4_D0, r0
mov.w r0,@r1
write16 PCCRL4_A, PCCRL4_D0
mov.l PECRL4_A, r1
mov.l PECRL4_D0, r0
mov.w r0,@r1
write16 PECRL4_A, PECRL4_D0
mov.l PEIORL_A, r1
mov.l PEIORL_D0, r0
mov.w r0,@r1
write16 PEIORL_A, PEIORL_D0
mov.l PCIORL_A, r1
mov.l PCIORL_D, r0
mov.w r0,@r1
write16 PCIORL_A, PCIORL_D
mov.l PFCRH2_A, r1
mov.l PFCRH2_D, r0
mov.w r0,@r1
write16 PFCRH2_A, PFCRH2_D
mov.l PFCRH3_A, r1
mov.l PFCRH3_D, r0
mov.w r0,@r1
write16 PFCRH3_A, PFCRH3_D
mov.l PFCRH1_A, r1
mov.l PFCRH1_D, r0
mov.w r0,@r1
write16 PFCRH1_A, PFCRH1_D
mov.l PFIORH_A, r1
mov.l PFIORH_D, r0
mov.w r0,@r1
write16 PFIORH_A, PFIORH_D
mov.l PECRL1_A, r1
mov.l PECRL1_D0, r0
mov.w r0,@r1
write16 PECRL1_A, PECRL1_D0
mov.l PEIORL_A, r1
mov.l PEIORL_D1, r0
mov.w r0,@r1
write16 PEIORL_A, PEIORL_D1
/* Configure Operating Frequency */
mov.l WTCSR_A ,r1
mov.l WTCSR_D0 ,r0
mov.w r0,@r1
write16 WTCSR_A, WTCSR_D0
mov.l WTCSR_A ,r1
mov.l WTCSR_D1 ,r0
mov.w r0,@r1
write16 WTCSR_A, WTCSR_D1
mov.l WTCNT_A ,r1
mov.l WTCNT_D ,r0
mov.w r0,@r1
write16 WTCNT_A, WTCNT_D
/* Set clock mode*/
mov.l FRQCR_A,r1
mov.l FRQCR_D,r0
mov.w r0,@r1
write16 FRQCR_A, FRQCR_D
/* Configure Bus And Memory */
init_bsc_cs0:
mov.l PCCRL4_A,r1
mov.l PCCRL4_D1,r0
mov.w r0,@r1
write16 PCCRL4_A, PCCRL4_D1
mov.l PECRL1_A,r1
mov.l PECRL1_D1,r0
mov.w r0,@r1
write16 PECRL1_A, PECRL1_D1
mov.l CMNCR_A,r1
mov.l CMNCR_D,r0
mov.l r0,@r1
write32 CMNCR_A, CMNCR_D
mov.l SC0BCR_A,r1
mov.l SC0BCR_D,r0
mov.l r0,@r1
write32 SC0BCR_A, SC0BCR_D
mov.l CS0WCR_A,r1
mov.l CS0WCR_D,r0
mov.l r0,@r1
write32 CS0WCR_A, CS0WCR_D
init_bsc_cs1:
mov.l PECRL4_A,r1
mov.l PECRL4_D1,r0
mov.w r0,@r1
write16 PECRL4_A, PECRL4_D1
mov.l CS1WCR_A,r1
mov.l CS1WCR_D,r0
mov.l r0,@r1
write32 CS1WCR_A, CS1WCR_D
init_sdram:
mov.l PCCRL2_A,r1
mov.l PCCRL2_D,r0
mov.w r0,@r1
write16 PCCRL2_A, PCCRL2_D
mov.l PCCRL4_A,r1
mov.l PCCRL4_D2,r0
mov.w r0,@r1
write16 PCCRL4_A, PCCRL4_D2
mov.l PCCRL1_A,r1
mov.l PCCRL1_D,r0
mov.w r0,@r1
write16 PCCRL1_A, PCCRL1_D
mov.l PCCRL3_A,r1
mov.l PCCRL3_D,r0
mov.w r0,@r1
write16 PCCRL3_A, PCCRL3_D
mov.l CS3BCR_A,r1
mov.l CS3BCR_D,r0
mov.l r0,@r1
write32 CS3BCR_A, CS3BCR_D
mov.l CS3WCR_A,r1
mov.l CS3WCR_D,r0
mov.l r0,@r1
write32 CS3WCR_A, CS3WCR_D
mov.l SDCR_A,r1
mov.l SDCR_D,r0
mov.l r0,@r1
write32 SDCR_A, SDCR_D
mov.l RTCOR_A,r1
mov.l RTCOR_D,r0
mov.l r0,@r1
write32 RTCOR_A, RTCOR_D
mov.l RTCSR_A,r1
mov.l RTCSR_D,r0
mov.l r0,@r1
write32 RTCSR_A, RTCSR_D
/* wait 200us */
mov.l REPEAT_D,r3
mov #0,r2
mov.l REPEAT_D, r3
mov #0, r2
repeat0:
add #1,r2
cmp/hs r3,r2
bf repeat0
add #1, r2
cmp/hs r3, r2
bf repeat0
nop
mov.l SDRAM_MODE, r1
mov #0,r0
mov.l r0, @r1
mov.l SDRAM_MODE, r1
mov #0, r0
mov.l r0, @r1
nop
rts
@ -208,8 +145,8 @@ PECRL1_D0: .long 0x00000033
WTCSR_A: .long 0xFFFE0000
WTCSR_D0: .long 0x0000A518
WTCSR_D1: .long 0x0000A51D
WTCSR_D0: .long 0x0000A518
WTCSR_D1: .long 0x0000A51D
WTCNT_A: .long 0xFFFE0002
WTCNT_D: .long 0x00005A84
FRQCR_A: .long 0xFFFE0010
@ -259,7 +196,7 @@ STBCR4_A: .long 0xFFFE040C
STBCR4_D: .long 0x00000008
STBCR5_A: .long 0xFFFE0410
STBCR5_D: .long 0x00000000
STBCR6_A: .long 0xFFFE0414
STBCR6_A: .long 0xFFFE0414
STBCR6_D: .long 0x00000002
SDRAM_MODE: .long 0xFFFC5040
REPEAT_D: .long 0x00009C40

196
board/renesas/sh7763rdp/lowlevel_init.S
View file

@ -25,6 +25,7 @@
#include <version.h>
#include <asm/processor.h>
#include <asm/macro.h>
.global lowlevel_init
@ -33,218 +34,141 @@
lowlevel_init:
mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */
mov.l WDTCSR_D, r0
mov.l r0, @r1
write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */
mov.l WDTST_A, r1 /* Watchdog Stop Time Register */
mov.l WDTST_D, r0
mov.l r0, @r1
write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */
mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */
mov.l WDTBST_D, r0
mov.l r0, @r1
write32 WDTBST_A, WDTBST_D /*
* 0xFFCC0008
* Watchdog Base Stop Time Register
*/
mov.l CCR_A, r1 /* Address of Cache Control Register */
mov.l CCR_CACHE_ICI_D, r0 /* Instruction Cache Invalidate */
mov.l r0, @r1
write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */
/* Instruction Cache Invalidate */
mov.l MMUCR_A, r1 /* Address of MMU Control Register */
mov.l MMU_CONTROL_TI_D, r0 /* TI == TLB Invalidate bit */
mov.l r0, @r1
write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */
/* TI == TLB Invalidate bit */
mov.l MSTPCR0_A, r1 /* Address of Power Control Register 0 */
mov.l MSTPCR0_D, r0
mov.l r0, @r1
write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */
mov.l MSTPCR1_A, r1 /*i Address of Power Control Register 1 */
mov.l MSTPCR1_D, r0
mov.l r0, @r1
write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */
mov.l RAMCR_A,r1
mov.l RAMCR_D,r0
mov.l r0, @r1
write32 RAMCR_A, RAMCR_D
mov.l MMSELR_A,r1
mov.l MMSELR_D,r0
mov.l MMSELR_A, r1
mov.l MMSELR_D, r0
synco
mov.l r0, @r1
mov.l @r1,r2 /* execute two reads after setting MMSELR*/
mov.l @r1,r2
mov.l @r1, r2 /* execute two reads after setting MMSELR */
mov.l @r1, r2
synco
/* issue memory read */
mov.l DDRSD_START_A,r1 /* memory address to read*/
mov.l @r1,r0
mov.l DDRSD_START_A, r1 /* memory address to read*/
mov.l @r1, r0
synco
mov.l MIM8_A,r1
mov.l MIM8_D,r0
mov.l r0,@r1
write32 MIM8_A, MIM8_D
mov.l MIMC_A,r1
mov.l MIMC_D1,r0
mov.l r0,@r1
write32 MIMC_A, MIMC_D1
mov.l STRC_A,r1
mov.l STRC_D,r0
mov.l r0,@r1
write32 STRC_A, STRC_D
mov.l SDR4_A,r1
mov.l SDR4_D,r0
mov.l r0,@r1
write32 SDR4_A, SDR4_D
mov.l MIMC_A,r1
mov.l MIMC_D2,r0
mov.l r0,@r1
write32 MIMC_A, MIMC_D2
nop
nop
nop
mov.l SCR4_A,r1
mov.l SCR4_D3,r0
mov.l r0,@r1
write32 SCR4_A, SCR4_D3
mov.l SCR4_A,r1
mov.l SCR4_D2,r0
mov.l r0,@r1
write32 SCR4_A, SCR4_D2
mov.l SDMR02000_A,r1
mov.l SDMR02000_D,r0
mov.l r0,@r1
write32 SDMR02000_A, SDMR02000_D
mov.l SDMR00B08_A,r1
mov.l SDMR00B08_D,r0
mov.l r0,@r1
write32 SDMR00B08_A, SDMR00B08_D
mov.l SCR4_A,r1
mov.l SCR4_D2,r0
mov.l r0,@r1
write32 SCR4_A, SCR4_D2
mov.l SCR4_A,r1
mov.l SCR4_D4,r0
mov.l r0,@r1
write32 SCR4_A, SCR4_D4
nop
nop
nop
nop
mov.l SCR4_A,r1
mov.l SCR4_D4,r0
mov.l r0,@r1
write32 SCR4_A, SCR4_D4
nop
nop
nop
nop
mov.l SDMR00308_A,r1
mov.l SDMR00308_D,r0
mov.l r0,@r1
write32 SDMR00308_A, SDMR00308_D
mov.l MIMC_A,r1
mov.l MIMC_D3,r0
mov.l r0,@r1
write32 MIMC_A, MIMC_D3
mov.l SCR4_A,r1
mov.l SCR4_D1,r0
mov.l DELAY60_D,r3
mov.l SCR4_A, r1
mov.l SCR4_D1, r0
mov.l DELAY60_D, r3
delay_loop_60:
mov.l r0,@r1
mov.l r0, @r1
dt r3
bf delay_loop_60
nop
mov.l CCR_A, r1 /* Address of Cache Control Register */
mov.l CCR_CACHE_D_2, r0
mov.l r0, @r1
write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */
bsc_init:
mov.l BCR_A, r1
mov.l BCR_D, r0
mov.l r0, @r1
write32 BCR_A, BCR_D
mov.l CS0BCR_A, r1
mov.l CS0BCR_D, r0
mov.l r0, @r1
write32 CS0BCR_A, CS0BCR_D
mov.l CS1BCR_A,r1
mov.l CS1BCR_D,r0
mov.l r0,@r1
write32 CS1BCR_A, CS1BCR_D
mov.l CS2BCR_A, r1
mov.l CS2BCR_D, r0
mov.l r0, @r1
write32 CS2BCR_A, CS2BCR_D
mov.l CS4BCR_A, r1
mov.l CS4BCR_D, r0
mov.l r0, @r1
write32 CS4BCR_A, CS4BCR_D
mov.l CS5BCR_A, r1
mov.l CS5BCR_D, r0
mov.l r0, @r1
write32 CS5BCR_A, CS5BCR_D
mov.l CS6BCR_A, r1
mov.l CS6BCR_D, r0
mov.l r0, @r1
write32 CS6BCR_A, CS6BCR_D
mov.l CS0WCR_A, r1
mov.l CS0WCR_D, r0
mov.l r0, @r1
write32 CS0WCR_A, CS0WCR_D
mov.l CS1WCR_A, r1
mov.l CS1WCR_D, r0
mov.l r0, @r1
write32 CS1WCR_A, CS1WCR_D
mov.l CS2WCR_A, r1
mov.l CS2WCR_D, r0
mov.l r0, @r1
write32 CS2WCR_A, CS2WCR_D
mov.l CS4WCR_A, r1
mov.l CS4WCR_D, r0
mov.l r0, @r1
write32 CS4WCR_A, CS4WCR_D
mov.l CS5WCR_A, r1
mov.l CS5WCR_D, r0
mov.l r0, @r1
write32 CS5WCR_A, CS5WCR_D
mov.l CS6WCR_A, r1
mov.l CS6WCR_D, r0
mov.l r0, @r1
write32 CS6WCR_A, CS6WCR_D
mov.l CS5PCR_A, r1
mov.l CS5PCR_D, r0
mov.l r0, @r1
write32 CS5PCR_A, CS5PCR_D
mov.l CS6PCR_A, r1
mov.l CS6PCR_D, r0
mov.l r0, @r1
write32 CS6PCR_A, CS6PCR_D
mov.l DELAY200_D,r3
mov.l DELAY200_D, r3
delay_loop_200:
dt r3
bf delay_loop_200
nop
mov.l PSEL0_A,r1
mov.l PSEL0_D,r0
mov.w r0,@r1
write16 PSEL0_A, PSEL0_D
mov.l PSEL1_A,r1
mov.l PSEL1_D,r0
mov.w r0,@r1
write16 PSEL1_A, PSEL1_D
mov.l ICR0_A,r1
mov.l ICR0_D,r0
mov.l r0,@r1
write32 ICR0_A, ICR0_D
stc sr, r0 /* BL bit off(init=ON) */
mov.l SR_MASK_D, r1
mov.l SR_MASK_D, r1
and r1, r0
ldc r0, sr
@ -321,7 +245,7 @@ CS4BCR_D: .long 0x77777670
CS5BCR_D: .long 0x77777670
CS6BCR_D: .long 0x77777670
CS0WCR_D: .long 0x7777770F
CS1WCR_D: .long 0x22000002
CS1WCR_D: .long 0x22000002
CS2WCR_D: .long 0x7777770F
CS4WCR_D: .long 0x7777770F
CS5WCR_D: .long 0x7777770F

30
board/renesas/sh7785lcr/lowlevel_init.S
View file

@ -19,33 +19,7 @@
#include <config.h>
#include <version.h>
#include <asm/processor.h>
.macro write32, addr, data
mov.l \addr ,r1
mov.l \data ,r0
mov.l r0, @r1
.endm
.macro write16, addr, data
mov.l \addr ,r1
mov.l \data ,r0
mov.w r0, @r1
.endm
.macro write8, addr, data
mov.l \addr ,r1
mov.l \data ,r0
mov.b r0, @r1
.endm
.macro wait_timer, time
mov.l \time ,r3
1:
nop
tst r3, r3
bf/s 1b
dt r3
.endm
#include <asm/macro.h>
#include <asm/processor.h>
@ -305,7 +279,7 @@ CS4WCR_D: .long 0x00101012
CS_USB_BCR_D: .long 0x11111200
CS_USB_WCR_D: .long 0x00020004
/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
CS_SD_BCR_D: .long 0x00000300
CS_SD_WCR_D: .long 0x00030108

2
board/sbc8548/sbc8548.c
View file

@ -126,7 +126,7 @@ local_bus_init(void)
sys_info_t sysinfo;
get_sys_info(&sysinfo);
clkdiv = (lbc->lcrr & 0x0f) * 2;
clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;

10
board/sbc8641d/law.c
View file

@ -45,14 +45,14 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
};
int num_law_entries = ARRAY_SIZE(law_table);

8
board/sbc8641d/sbc8641d.c
View file

@ -247,14 +247,14 @@ void pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
@ -290,14 +290,14 @@ void pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI2_MEM_BASE,
CONFIG_SYS_PCI2_MEM_BUS,
CONFIG_SYS_PCI2_MEM_PHYS,
CONFIG_SYS_PCI2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCI2_IO_BASE,
CONFIG_SYS_PCI2_IO_BUS,
CONFIG_SYS_PCI2_IO_PHYS,
CONFIG_SYS_PCI2_IO_SIZE,
PCI_REGION_IO);

6
board/sc520_cdp/u-boot.lds
View file

@ -75,7 +75,7 @@ SECTIONS
* The fe00 and ff00 offsets of the start32 and start16
* segments are arbitrary, the just have to be mapped
* at reset and the code have to fit.
* The fff0 offset of reset is important, however.
* The fff0 offset of resetvec is important, however.
*/
@ -86,6 +86,6 @@ SECTIONS
.start16 : AT (0x387fff00) { *(.start16); }
. = 0xfff0;
.reset : AT (0x387ffff0) { *(.reset); }
_i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) );
.resetvec : AT (0x387ffff0) { *(.resetvec); }
_i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) );
}

6
board/sc520_spunk/u-boot.lds
View file

@ -76,7 +76,7 @@ SECTIONS
* The fe00 and ff00 offsets of the start32 and start16
* segments are arbitrary, the just have to be mapped
* at reset and the code have to fit.
* The fff0 offset of reset is important, however.
* The fff0 offset of resetvec is important, however.
*/
@ -87,6 +87,6 @@ SECTIONS
.start16 : AT (0x387fff00) { *(.start16); }
. = 0xfff0;
.reset : AT (0x387ffff0) { *(.reset); }
_i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) );
.resetvec : AT (0x387ffff0) { *(.resetvec); }
_i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) );
}

8
board/xilinx/xupv2p/Makefile → board/sheldon/simpc8313/Makefile
View file

@ -1,5 +1,5 @@
#
# (C) Copyright 2000-2006
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@ -25,14 +25,14 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o
COBJS := $(BOARD).o sdram.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $^
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)

13
board/sheldon/simpc8313/config.mk Normal file
View file

@ -0,0 +1,13 @@
ifndef NAND_SPL
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
endif
ifndef TEXT_BASE
TEXT_BASE = 0x00100000
endif
ifdef CONFIG_NAND_LP
PAD_TO = 0xFFF20000
else
PAD_TO = 0xFFF04000
endif

193
board/sheldon/simpc8313/sdram.c Normal file
View file

@ -0,0 +1,193 @@
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006-2007
* Copyright (C) Sheldon Instruments, Inc. 2008
*
* Author: Ron Madrid <info@sheldoninst.com>
*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc83xx.h>
#include <spd_sdram.h>
#include <asm/bitops.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
static long fixed_sdram(void);
#if defined(CONFIG_NAND_SPL)
void si_wait_i2c(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
while (!(__raw_readb(&im->i2c[0].sr) & 0x02))
;
__raw_writeb(0x00, &im->i2c[0].sr);
sync();
return;
}
void si_read_i2c(u32 lbyte, int count, u8 *buffer)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 i;
u8 chip = 0x50 << 1; /* boot sequencer I2C */
u32 ubyte = (lbyte & 0xff00) >> 8;
lbyte &= 0xff;
/*
* Set up controller
*/
__raw_writeb(0x3f, &im->i2c[0].fdr);
__raw_writeb(0x00, &im->i2c[0].adr);
__raw_writeb(0x00, &im->i2c[0].sr);
__raw_writeb(0x00, &im->i2c[0].dr);
while (__raw_readb(&im->i2c[0].sr) & 0x20)
;
/*
* Writing address to device
*/
__raw_writeb(0xb0, &im->i2c[0].cr);
sync();
__raw_writeb(chip, &im->i2c[0].dr);
si_wait_i2c();
__raw_writeb(0xb0, &im->i2c[0].cr);
sync();
__raw_writeb(ubyte, &im->i2c[0].dr);
si_wait_i2c();
__raw_writeb(lbyte, &im->i2c[0].dr);
si_wait_i2c();
__raw_writeb(0xb4, &im->i2c[0].cr);
sync();
__raw_writeb(chip + 1, &im->i2c[0].dr);
si_wait_i2c();
__raw_writeb(0xa0, &im->i2c[0].cr);
sync();
/*
* Dummy read
*/
__raw_readb(&im->i2c[0].dr);
si_wait_i2c();
/*
* Read actual data
*/
for (i = 0; i < count; i++)
{
if (i == (count - 2)) /* Reached next to last byte, No ACK */
__raw_writeb(0xa8, &im->i2c[0].cr);
if (i == (count - 1)) /* Reached last byte, STOP */
__raw_writeb(0x88, &im->i2c[0].cr);
/* Read byte of data */
buffer[i] = __raw_readb(&im->i2c[0].dr);
if (i == (count - 1))
break;
si_wait_i2c();
}
return;
}
#endif /* CONFIG_NAND_SPL */
phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile fsl_lbus_t *lbc= &im->lbus;
u32 msize;
if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
/* DDR SDRAM - Main SODIMM */
__raw_writel(CONFIG_SYS_DDR_BASE & LAWBAR_BAR, &im->sysconf.ddrlaw[0].bar);
msize = fixed_sdram();
/* Local Bus setup lbcr and mrtpr */
__raw_writel(CONFIG_SYS_LBC_LBCR, &lbc->lbcr);
__raw_writel(CONFIG_SYS_LBC_MRTPR, &lbc->mrtpr);
sync();
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
/*************************************************************************
* fixed sdram init -- reads values from boot sequencer I2C
************************************************************************/
static long fixed_sdram(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msizelog2, msize = 1;
#if defined(CONFIG_NAND_SPL)
u32 i;
const u8 bytecount = 135;
u8 buffer[bytecount];
u32 addr, data;
si_read_i2c(0, bytecount, buffer);
for (i = 18; i < bytecount; i += 7){
addr = (u32)buffer[i];
addr <<= 8;
addr |= (u32)buffer[i + 1];
addr <<= 2;
data = (u32)buffer[i + 2];
data <<= 8;
data |= (u32)buffer[i + 3];
data <<= 8;
data |= (u32)buffer[i + 4];
data <<= 8;
data |= (u32)buffer[i + 5];
__raw_writel(data, (u32 *)(CONFIG_SYS_IMMR + addr));
}
sync();
/* enable DDR controller */
__raw_writel((__raw_readl(&im->ddr.sdram_cfg) | SDRAM_CFG_MEM_EN), &im->ddr.sdram_cfg);
#endif /* (CONFIG_NAND_SPL) */
msizelog2 = ((__raw_readl(&im->sysconf.ddrlaw[0].ar) & LAWAR_SIZE) + 1);
msize <<= (msizelog2 - 20);
return msize;
}

134
board/sheldon/simpc8313/simpc8313.c Normal file
View file

@ -0,0 +1,134 @@
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006-2007
* Copyright (C) Sheldon Instruments, Inc. 2008
*
* Author: Ron Madrid <info@sheldoninst.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <libfdt.h>
#include <pci.h>
#include <mpc83xx.h>
#include <ns16550.h>
#include <nand.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
puts("Board: Sheldon Instruments SIMPC8313\n");
return 0;
}
#ifndef CONFIG_NAND_SPL
static struct pci_region pci_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
size: CONFIG_SYS_PCI1_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
size: CONFIG_SYS_PCI1_MMIO_SIZE,
flags: PCI_REGION_MEM
},
{
bus_start: CONFIG_SYS_PCI1_IO_BASE,
phys_start: CONFIG_SYS_PCI1_IO_PHYS,
size: CONFIG_SYS_PCI1_IO_SIZE,
flags: PCI_REGION_IO
}
};
void pci_init_board(void)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
struct pci_region *reg[] = { pci_regions };
int warmboot;
/* Enable all 3 PCI_CLK_OUTPUTs. */
clk->occr |= 0xe0000000;
/*
* Configure PCI Local Access Windows
*/
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
mpc83xx_pci_init(1, reg, warmboot);
}
/*
* Miscellaneous late-boot configurations
*/
int misc_init_r(void)
{
int rc = 0;
return rc;
}
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
}
#endif
#else /* CONFIG_NAND_SPL */
void board_init_f(ulong bootflag)
{
NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
puts("NAND boot... ");
init_timebase();
initdram(0);
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
CONFIG_SYS_NAND_U_BOOT_RELOC);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
nand_boot();
}
void putc(char c)
{
if (gd->flags & GD_FLG_SILENT)
return;
if (c == '\n')
NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
}
#endif

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