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phy: phy-mtk-tphy: add support USB phys
Support USB2 and USB3 PHY with shared banks when support multi-phys Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Chunfeng Yun
Marek Vasut
parent
cf67e45179
commit
ee6eabbedd
1 changed files with 218 additions and 9 deletions
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@ -20,11 +20,66 @@
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/* version V1 sub-banks offset base address */
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/* banks shared by multiple phys */
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#define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */
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#define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */
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#define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */
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/* u2 phy bank */
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#define SSUSB_SIFSLV_V1_U2PHY_COM 0x000
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/* u3/pcie/sata phy banks */
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#define SSUSB_SIFSLV_V1_U3PHYD 0x000
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#define SSUSB_SIFSLV_V1_U3PHYA 0x200
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#define U3P_USBPHYACR0 0x000
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#define PA0_RG_U2PLL_FORCE_ON BIT(15)
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#define PA0_RG_USB20_INTR_EN BIT(5)
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#define U3P_USBPHYACR5 0x014
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#define PA5_RG_U2_HSTX_SRCAL_EN BIT(15)
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#define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12)
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#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
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#define PA5_RG_U2_HS_100U_U3_EN BIT(11)
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#define U3P_USBPHYACR6 0x018
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#define PA6_RG_U2_BC11_SW_EN BIT(23)
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#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
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#define PA6_RG_U2_SQTH GENMASK(3, 0)
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#define PA6_RG_U2_SQTH_VAL(x) (0xf & (x))
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#define U3P_U2PHYACR4 0x020
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#define P2C_RG_USB20_GPIO_CTL BIT(9)
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#define P2C_USB20_GPIO_MODE BIT(8)
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#define P2C_U2_GPIO_CTR_MSK \
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(P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
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#define U3P_U2PHYDTM0 0x068
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#define P2C_FORCE_UART_EN BIT(26)
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#define P2C_FORCE_DATAIN BIT(23)
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#define P2C_FORCE_DM_PULLDOWN BIT(21)
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#define P2C_FORCE_DP_PULLDOWN BIT(20)
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#define P2C_FORCE_XCVRSEL BIT(19)
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#define P2C_FORCE_SUSPENDM BIT(18)
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#define P2C_FORCE_TERMSEL BIT(17)
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#define P2C_RG_DATAIN GENMASK(13, 10)
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#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)
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#define P2C_RG_DMPULLDOWN BIT(7)
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#define P2C_RG_DPPULLDOWN BIT(6)
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#define P2C_RG_XCVRSEL GENMASK(5, 4)
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#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)
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#define P2C_RG_SUSPENDM BIT(3)
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#define P2C_RG_TERMSEL BIT(2)
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#define P2C_DTM0_PART_MASK \
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(P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
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P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
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P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
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P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
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#define U3P_U2PHYDTM1 0x06C
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#define P2C_RG_UART_EN BIT(16)
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#define P2C_FORCE_IDDIG BIT(9)
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#define P2C_RG_VBUSVALID BIT(5)
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#define P2C_RG_SESSEND BIT(4)
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#define P2C_RG_AVALID BIT(2)
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#define P2C_RG_IDDIG BIT(1)
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#define U3P_U3_CHIP_GPIO_CTLD 0x0c
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#define P3C_REG_IP_SW_RST BIT(31)
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#define P3C_MCU_BUS_CK_GATE_EN BIT(30)
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@ -42,6 +97,14 @@
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#define P3A_RG_CLKDRV_AMP GENMASK(31, 29)
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#define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29)
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#define U3P_U3_PHYA_REG6 0x018
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#define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)
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#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
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#define U3P_U3_PHYA_REG9 0x024
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#define P3A_RG_RX_DAC_MUX GENMASK(5, 1)
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#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
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#define U3P_U3_PHYA_DA_REG0 0x100
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#define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16)
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#define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16)
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@ -77,6 +140,16 @@
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#define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0)
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#define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x))
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#define U3P_U3_PHYD_LFPS1 0x00c
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#define P3D_RG_FWAKE_TH GENMASK(21, 16)
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#define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16)
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#define U3P_U3_PHYD_CDR1 0x05c
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#define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24)
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#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
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#define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8)
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#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
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#define U3P_U3_PHYD_RXDET1 0x128
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#define P3D_RG_RXDET_STB2_SET GENMASK(17, 9)
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#define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9)
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@ -85,6 +158,16 @@
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#define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0)
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#define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
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#define U3P_SPLLC_XTALCTL3 0x018
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#define XC3_RG_U3_XTAL_RX_PWD BIT(9)
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#define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
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struct u2phy_banks {
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void __iomem *misc;
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void __iomem *fmreg;
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void __iomem *com;
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};
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struct u3phy_banks {
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void __iomem *spllc;
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void __iomem *chip;
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@ -95,21 +178,127 @@ struct u3phy_banks {
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struct mtk_phy_instance {
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void __iomem *port_base;
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const struct device_node *np;
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struct u3phy_banks u3_banks;
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union {
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struct u2phy_banks u2_banks;
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struct u3phy_banks u3_banks;
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};
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/* reference clock of anolog phy */
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struct clk ref_clk;
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u32 index;
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u8 type;
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u32 type;
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};
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struct mtk_tphy {
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struct udevice *dev;
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void __iomem *sif_base;
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struct mtk_phy_instance **phys;
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int nphys;
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};
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static void u2_phy_instance_init(struct mtk_tphy *tphy,
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struct mtk_phy_instance *instance)
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{
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struct u2phy_banks *u2_banks = &instance->u2_banks;
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/* switch to USB function, and enable usb pll */
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clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM0,
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P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM,
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P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0));
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clrbits_le32(u2_banks->com + U3P_U2PHYDTM1, P2C_RG_UART_EN);
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setbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN);
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/* disable switch 100uA current to SSUSB */
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clrbits_le32(u2_banks->com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
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clrbits_le32(u2_banks->com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
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/* DP/DM BC1.1 path Disable */
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clrsetbits_le32(u2_banks->com + U3P_USBPHYACR6,
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PA6_RG_U2_BC11_SW_EN | PA6_RG_U2_SQTH,
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PA6_RG_U2_SQTH_VAL(2));
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/* set HS slew rate */
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clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5,
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PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));
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dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
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}
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static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
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struct mtk_phy_instance *instance)
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{
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struct u2phy_banks *u2_banks = &instance->u2_banks;
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clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
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P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
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/* OTG Enable */
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setbits_le32(u2_banks->com + U3P_USBPHYACR6,
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PA6_RG_U2_OTG_VBUSCMP_EN);
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clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
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P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID);
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dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
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}
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static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
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struct mtk_phy_instance *instance)
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{
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struct u2phy_banks *u2_banks = &instance->u2_banks;
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clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
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P2C_RG_XCVRSEL | P2C_RG_DATAIN);
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/* OTG Disable */
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clrbits_le32(u2_banks->com + U3P_USBPHYACR6,
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PA6_RG_U2_OTG_VBUSCMP_EN);
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clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
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P2C_RG_VBUSVALID | P2C_RG_AVALID, P2C_RG_SESSEND);
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dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
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}
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static void u3_phy_instance_init(struct mtk_tphy *tphy,
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struct mtk_phy_instance *instance)
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{
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struct u3phy_banks *u3_banks = &instance->u3_banks;
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/* gating PCIe Analog XTAL clock */
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setbits_le32(u3_banks->spllc + U3P_SPLLC_XTALCTL3,
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XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD);
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/* gating XSQ */
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clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
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P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2));
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clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG9,
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P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4));
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clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG6,
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P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe));
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clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_CDR1,
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P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1,
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P3D_RG_CDR_BIR_LTD0_VAL(0xc) |
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P3D_RG_CDR_BIR_LTD1_VAL(0x3));
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clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_LFPS1,
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P3D_RG_FWAKE_TH, P3D_RG_FWAKE_TH_VAL(0x34));
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clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
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P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10));
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clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
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P3D_RG_RXDET_STB2_SET_P3,
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P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
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dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
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}
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static void pcie_phy_instance_init(struct mtk_tphy *tphy,
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struct mtk_phy_instance *instance)
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{
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@ -187,9 +376,16 @@ static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
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static void phy_v1_banks_init(struct mtk_tphy *tphy,
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struct mtk_phy_instance *instance)
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{
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struct u2phy_banks *u2_banks = &instance->u2_banks;
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struct u3phy_banks *u3_banks = &instance->u3_banks;
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switch (instance->type) {
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case PHY_TYPE_USB2:
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u2_banks->misc = NULL;
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u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
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u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
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break;
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case PHY_TYPE_USB3:
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case PHY_TYPE_PCIE:
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u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
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u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
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@ -197,6 +393,7 @@ static void phy_v1_banks_init(struct mtk_tphy *tphy,
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u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
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break;
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default:
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dev_err(tphy->dev, "incompatible PHY type\n");
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return;
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}
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}
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@ -212,10 +409,17 @@ static int mtk_phy_init(struct phy *phy)
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return ret;
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switch (instance->type) {
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case PHY_TYPE_USB2:
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u2_phy_instance_init(tphy, instance);
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break;
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case PHY_TYPE_USB3:
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u3_phy_instance_init(tphy, instance);
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break;
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case PHY_TYPE_PCIE:
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pcie_phy_instance_init(tphy, instance);
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break;
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default:
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dev_err(tphy->dev, "incompatible PHY type\n");
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return -EINVAL;
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}
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@ -227,7 +431,10 @@ static int mtk_phy_power_on(struct phy *phy)
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struct mtk_tphy *tphy = dev_get_priv(phy->dev);
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struct mtk_phy_instance *instance = tphy->phys[phy->id];
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pcie_phy_instance_power_on(tphy, instance);
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if (instance->type == PHY_TYPE_USB2)
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u2_phy_instance_power_on(tphy, instance);
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else if (instance->type == PHY_TYPE_PCIE)
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pcie_phy_instance_power_on(tphy, instance);
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return 0;
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}
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@ -237,7 +444,10 @@ static int mtk_phy_power_off(struct phy *phy)
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struct mtk_tphy *tphy = dev_get_priv(phy->dev);
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struct mtk_phy_instance *instance = tphy->phys[phy->id];
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pcie_phy_instance_power_off(tphy, instance);
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if (instance->type == PHY_TYPE_USB2)
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u2_phy_instance_power_off(tphy, instance);
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else if (instance->type == PHY_TYPE_PCIE)
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pcie_phy_instance_power_off(tphy, instance);
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return 0;
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}
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@ -285,8 +495,7 @@ static int mtk_phy_xlate(struct phy *phy,
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instance->type = args->args[1];
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if (!(instance->type == PHY_TYPE_USB2 ||
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instance->type == PHY_TYPE_USB3 ||
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instance->type == PHY_TYPE_PCIE ||
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instance->type == PHY_TYPE_SATA)) {
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instance->type == PHY_TYPE_PCIE)) {
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dev_err(phy->dev, "unsupported device type\n");
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return -EINVAL;
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}
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@ -310,14 +519,14 @@ static int mtk_tphy_probe(struct udevice *dev)
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ofnode subnode;
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int index = 0;
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dev_for_each_subnode(subnode, dev)
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tphy->nphys++;
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tphy->nphys = dev_get_child_count(dev);
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tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys),
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GFP_KERNEL);
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if (!tphy->phys)
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return -ENOMEM;
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tphy->dev = dev;
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tphy->sif_base = dev_read_addr_ptr(dev);
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if (!tphy->sif_base)
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return -ENOENT;
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