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rockchip: Add common reset cause

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Add cpu reset cause in common cpu-info file.

This would help to print the reset cause for
various resets.

Right now it support rk3288, rk3399. rest of rockchip
platforms doesn't have reset cause support ye but this
code is more feasible to extend the same.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Jagan Teki 2020-01-09 14:22:18 +05:30 committed by Kever Yang
parent b52a199e32
commit ee6321fa14
4 changed files with 62 additions and 52 deletions
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12
arch/arm/include/asm/arch-rockchip/cru.h
View file

@ -13,6 +13,18 @@
# include <asm/arch-rockchip/cru_rk3399.h>
#endif
/* CRU_GLB_RST_ST */
enum {
GLB_POR_RST,
FST_GLB_RST_ST = BIT(0),
SND_GLB_RST_ST = BIT(1),
FST_GLB_TSADC_RST_ST = BIT(2),
SND_GLB_TSADC_RST_ST = BIT(3),
FST_GLB_WDT_RST_ST = BIT(4),
SND_GLB_WDT_RST_ST = BIT(5),
GLB_RST_ST_MASK = GENMASK(5, 0),
};
#define MHz 1000000
#endif /* _ROCKCHIP_CLOCK_H */

14
arch/arm/include/asm/arch-rockchip/cru_rk3288.h
View file

@ -51,7 +51,7 @@ struct rockchip_cru {
u32 cru_glb_cnt_th;
u32 cru_glb_rst_con;
u32 reserved3;
u32 cru_glb_rst_st;
u32 glb_rst_st;
u32 reserved4;
u32 cru_sdmmc_con[2];
u32 cru_sdio0_con[2];
@ -227,16 +227,4 @@ enum {
CLKF_MASK = 0x1fff << CLKF_SHIFT,
};
/* CRU_GLB_RST_ST */
enum {
GLB_POR_RST,
FST_GLB_RST_ST = BIT(0),
SND_GLB_RST_ST = BIT(1),
FST_GLB_TSADC_RST_ST = BIT(2),
SND_GLB_TSADC_RST_ST = BIT(3),
FST_GLB_WDT_RST_ST = BIT(4),
SND_GLB_WDT_RST_ST = BIT(5),
GLB_RST_ST_MASK = GENMASK(5, 0),
};
#endif

49
arch/arm/mach-rockchip/cpu-info.c
View file

@ -5,10 +5,59 @@
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/hardware.h>
#include <linux/err.h>
static char *get_reset_cause(void)
{
struct rockchip_cru *cru = rockchip_get_cru();
char *cause = NULL;
if (IS_ERR(cru))
return cause;
switch (cru->glb_rst_st) {
case GLB_POR_RST:
cause = "POR";
break;
case FST_GLB_RST_ST:
case SND_GLB_RST_ST:
cause = "RST";
break;
case FST_GLB_TSADC_RST_ST:
case SND_GLB_TSADC_RST_ST:
cause = "THERMAL";
break;
case FST_GLB_WDT_RST_ST:
case SND_GLB_WDT_RST_ST:
cause = "WDOG";
break;
default:
cause = "unknown reset";
}
/**
* reset_reason env is used by rk3288, due to special use case
* to figure it the boot behavior. so keep this as it is.
*/
env_set("reset_reason", cause);
/*
* Clear glb_rst_st, so we can determine the last reset cause
* for following resets.
*/
rk_clrreg(&cru->glb_rst_st, GLB_RST_ST_MASK);
return cause;
}
int print_cpuinfo(void)
{
printf("SoC: Rockchip %s\n", CONFIG_SYS_SOC);
printf("Reset cause: %s\n", get_reset_cause());
/* TODO print operating temparature and clock */

39
arch/arm/mach-rockchip/rk3288/rk3288.c
View file

@ -102,43 +102,6 @@ void board_debug_uart_init(void)
}
#endif
static void rk3288_detect_reset_reason(void)
{
struct rockchip_cru *cru = rockchip_get_cru();
const char *reason;
if (IS_ERR(cru))
return;
switch (cru->cru_glb_rst_st) {
case GLB_POR_RST:
reason = "POR";
break;
case FST_GLB_RST_ST:
case SND_GLB_RST_ST:
reason = "RST";
break;
case FST_GLB_TSADC_RST_ST:
case SND_GLB_TSADC_RST_ST:
reason = "THERMAL";
break;
case FST_GLB_WDT_RST_ST:
case SND_GLB_WDT_RST_ST:
reason = "WDOG";
break;
default:
reason = "unknown reset";
}
env_set("reset_reason", reason);
/*
* Clear cru_glb_rst_st, so we can determine the last reset cause
* for following resets.
*/
rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
}
__weak int rk3288_board_late_init(void)
{
return 0;
@ -146,8 +109,6 @@ __weak int rk3288_board_late_init(void)
int rk_board_late_init(void)
{
rk3288_detect_reset_reason();
return rk3288_board_late_init();
}