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Revert "armv8: enable HAFDBS for other ELx when FEAT_HAFDBS is present"

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This reverts commit c1da6fdb5c. This is
part of a series trying to make use of the arm64 hardware features for
tracking dirty pages. Unfortunately this series causes problems for the
AC5/AC5X SoCs. Having exhausted other options the consensus seems to be
reverting this series is the best course of action.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
This commit is contained in:
Chris Packham 2023-10-27 13:23:52 +13:00 committed by Tom Rini
parent ac33a7976a
commit ee23d7466c
2 changed files with 3 additions and 13 deletions
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6
arch/arm/cpu/armv8/cache_v8.c
View file

@ -94,15 +94,11 @@ u64 get_tcr(u64 *pips, u64 *pva_bits)
if (el == 1) { if (el == 1) {
tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE; tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
if (gd->arch.has_hafdbs) if (gd->arch.has_hafdbs)
tcr |= TCR_EL1_HA | TCR_EL1_HD; tcr |= TCR_HA | TCR_HD;
} else if (el == 2) { } else if (el == 2) {
tcr = TCR_EL2_RSVD | (ips << 16); tcr = TCR_EL2_RSVD | (ips << 16);
if (gd->arch.has_hafdbs)
tcr |= TCR_EL2_HA | TCR_EL2_HD;
} else { } else {
tcr = TCR_EL3_RSVD | (ips << 16); tcr = TCR_EL3_RSVD | (ips << 16);
if (gd->arch.has_hafdbs)
tcr |= TCR_EL3_HA | TCR_EL3_HD;
} }
/* PTWs cacheable, inner/outer WBWA and inner shareable */ /* PTWs cacheable, inner/outer WBWA and inner shareable */

10
arch/arm/include/asm/armv8/mmu.h
View file

@ -102,14 +102,8 @@
#define TCR_TG0_16K (2 << 14) #define TCR_TG0_16K (2 << 14)
#define TCR_EPD1_DISABLE (1 << 23) #define TCR_EPD1_DISABLE (1 << 23)
#define TCR_EL1_HA BIT(39) #define TCR_HA BIT(39)
#define TCR_EL1_HD BIT(40) #define TCR_HD BIT(40)
#define TCR_EL2_HA BIT(21)
#define TCR_EL2_HD BIT(22)
#define TCR_EL3_HA BIT(21)
#define TCR_EL3_HD BIT(22)
#define TCR_EL1_RSVD (1U << 31) #define TCR_EL1_RSVD (1U << 31)
#define TCR_EL2_RSVD (1U << 31 | 1 << 23) #define TCR_EL2_RSVD (1U << 31 | 1 << 23)