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https://github.com/AsahiLinux/u-boot
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powerpc: mpc8xx: Change CONFIG_8xx to CONFIG_MPC8xx
CONFIG_8xx doesn't mean much outside of arch/powerpc/ This patch renames it CONFIG_MPC8xx just like CONFIG_MPC85xx etc ... It also renames 8xx_immap.h to immap_8xx.h to be consistent with other file names. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
This commit is contained in:
parent
0ebb5388b4
commit
ee1e600c13
19 changed files with 24 additions and 24 deletions
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@ -30,7 +30,7 @@ int platform_sys_info(struct sys_info *si)
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si->clk_bus = gd->bus_clk;
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si->clk_cpu = gd->cpu_clk;
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#if defined(CONFIG_8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
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#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
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#define bi_bar bi_immr_base
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#elif defined(CONFIG_MPC83xx)
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#define bi_bar bi_immrbar
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@ -30,7 +30,7 @@ config MPC86xx
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select SYS_FSL_DDR_BE
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imply CMD_REGINFO
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config 8xx
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config MPC8xx
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bool "MPC8xx"
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imply CMD_REGINFO
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@ -1,5 +1,5 @@
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menu "mpc8xx CPU"
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depends on 8xx
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depends on MPC8xx
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config SYS_CPU
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default "mpc8xx"
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@ -12,7 +12,7 @@
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#include <common.h>
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#include <command.h>
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#include <asm/8xx_immap.h>
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#include <asm/immap_8xx.h>
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#include <commproc.h>
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#include <asm/iopin_8xx.h>
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#include <asm/io.h>
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@ -7,7 +7,7 @@
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#include <asm/processor.h>
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/* bytes per L1 cache line */
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#if defined(CONFIG_8xx)
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#if defined(CONFIG_MPC8xx)
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#define L1_CACHE_SHIFT 4
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#elif defined(CONFIG_PPC64BRIDGE)
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#define L1_CACHE_SHIFT 7
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@ -72,7 +72,7 @@ void disable_cpc_sram(void);
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#define L2CACHE_NONE 0x03 /* NONE */
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#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
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#ifdef CONFIG_8xx
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#ifdef CONFIG_MPC8xx
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/* Cache control on the MPC8xx is provided through some additional
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* special purpose registers.
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*/
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@ -139,6 +139,6 @@ static inline void wr_dc_adr(uint val)
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mtspr(DC_ADR, val);
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}
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#endif
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#endif /* CONFIG_8xx */
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#endif /* CONFIG_MPC8xx */
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#endif
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@ -19,7 +19,7 @@ struct arch_global_data {
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u8 sdhc_adapter;
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#endif
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#endif
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#if defined(CONFIG_8xx)
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#if defined(CONFIG_MPC8xx)
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unsigned long brg_clk;
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#endif
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#if defined(CONFIG_CPM2)
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@ -11,7 +11,7 @@
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#define _ASM_IOPIN_8XX_H_
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#include <linux/types.h>
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#include <asm/8xx_immap.h>
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#include <asm/immap_8xx.h>
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#include <asm/io.h>
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#ifdef __KERNEL__
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@ -13,8 +13,8 @@
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#ifndef __ASSEMBLY__
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#if defined(CONFIG_8xx)
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#include <asm/8xx_immap.h>
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#if defined(CONFIG_MPC8xx)
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#include <asm/immap_8xx.h>
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#endif
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#ifdef CONFIG_MPC86xx
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#include <mpc86xx.h>
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@ -180,7 +180,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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print_bi_flash(bd);
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print_num("sramstart", bd->bi_sramstart);
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print_num("sramsize", bd->bi_sramsize);
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#if defined(CONFIG_8xx) || defined(CONFIG_E500)
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#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500)
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print_num("immr_base", bd->bi_immr_base);
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#endif
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print_num("bootflags", bd->bi_bootflags);
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@ -1,6 +1,6 @@
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CONFIG_PPC=y
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CONFIG_SYS_TEXT_BASE=0x4000000
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CONFIG_8xx=y
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CONFIG_MPC8xx=y
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CONFIG_TARGET_MCR3000=y
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CONFIG_8xx_GCLK_FREQ=132000000
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CONFIG_CMD_IMMAP=y
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@ -331,7 +331,7 @@ config RENESAS_RAVB
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config MPC8XX_FEC
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bool "Fast Ethernet Controller on MPC8XX"
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depends on 8xx
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depends on MPC8xx
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select MII
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help
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This driver implements support for the Fast Ethernet Controller
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@ -624,7 +624,7 @@ config ZYNQ_SERIAL
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config MPC8XX_CONS
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bool "Console driver for MPC8XX"
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depends on 8xx
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depends on MPC8xx
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default y
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choice
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@ -276,7 +276,7 @@ config LPC32XX_SSP
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config MPC8XX_SPI
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bool "MPC8XX SPI Driver"
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depends on 8xx
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depends on MPC8xx
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help
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Enable support for SPI on MPC8XX
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@ -37,7 +37,7 @@ typedef struct bd_info {
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unsigned long bi_dsp_freq; /* dsp core frequency */
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unsigned long bi_ddr_freq; /* ddr frequency */
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#endif
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#if defined(CONFIG_8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
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#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
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unsigned long bi_immr_base; /* base of IMMR register */
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#endif
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#if defined(CONFIG_M68K)
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@ -16,7 +16,7 @@
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#ifndef __CPM_8XX__
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#define __CPM_8XX__
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#include <asm/8xx_immap.h>
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#include <asm/immap_8xx.h>
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/* CPM Command register.
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*/
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@ -81,7 +81,7 @@
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#define TBSCR_TBIRQ2 0x0400 /* Time Base Interrupt Request 2 */
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#define TBSCR_TBIRQ1 0x0200 /* Time Base Interrupt Request 1 */
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#define TBSCR_TBIRQ0 0x0100 /* Time Base Interrupt Request 0 */
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#if 0 /* already in asm/8xx_immap.h */
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#if 0 /* already in asm/immap_8xx.h */
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#define TBSCR_REFA 0x0080 /* Reference Interrupt Status A */
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#define TBSCR_REFB 0x0040 /* Reference Interrupt Status B */
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#define TBSCR_REFAE 0x0008 /* Second Interrupt Enable A */
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@ -95,7 +95,7 @@
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*/
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#undef PISCR_PIRQ /* TBD */
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#define PISCR_PITF 0x0002 /* Periodic Interrupt Timer Freeze */
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#if 0 /* already in asm/8xx_immap.h */
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#if 0 /* already in asm/immap_8xx.h */
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#define PISCR_PS 0x0080 /* Periodic interrupt Status */
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#define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */
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#define PISCR_PTE 0x0001 /* Periodic Timer Enable */
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@ -81,7 +81,7 @@
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#define r30 30
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#define r31 31
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#if defined(CONFIG_8xx)
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#if defined(CONFIG_MPC8xx)
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/* Some special registers */
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@ -93,10 +93,10 @@
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#define LCTRL2 157 /* Load/Store Support (37-41) */
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#define ICTRL 158
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#endif /* CONFIG_8xx */
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#endif /* CONFIG_MPC8xx */
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#if defined(CONFIG_8xx)
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#if defined(CONFIG_MPC8xx)
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/* Registers in the processor's internal memory map that we use.
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*/
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@ -73,7 +73,7 @@ int init_func_watchdog_reset(void);
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*/
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/* MPC 8xx */
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#if defined(CONFIG_8xx) && !defined(__ASSEMBLY__)
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#if defined(CONFIG_MPC8xx) && !defined(__ASSEMBLY__)
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void reset_8xx_watchdog(immap_t __iomem *immr);
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#endif
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