Merge tag 'u-boot-rockchip-20231110' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

- Add Board: rk3588 Pine64 QuartzPro64;
- Fix rk3066 enter download mode;
- Fix for ringneck-px30 board;

arch/arm/dts/Makefile

@@ -194,6 +194,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \
 	rk3588-nanopc-t6.dtb \
 	rk3588s-orangepi-5.dtb \
 	rk3588-orangepi-5-plus.dtb \
+	rk3588-quartzpro64.dtb \
 	rk3588s-rock-5a.dtb \
 	rk3588-rock-5b.dtb
 

arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi

@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Google, Inc
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+	chosen {
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+	};
+};

arch/arm/dts/rv1126-u-boot.dtsi

@@ -15,6 +15,18 @@
 		compatible = "rockchip,rv1126-dmc";
 		bootph-all;
 	};
+
+	otp: otp@ff5c0000 {
+		compatible = "rockchip,rv1126-otp";
+		reg = <0xff5c0000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		status = "okay";
+
+		cpu_id: id@7 {
+			reg = <0x07 0x10>;
+		};
+	};
 };
 
 &gpio0 {
@@ -26,15 +38,15 @@
 };
 
 &grf {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &pmu {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &pmugrf {
-	bootph-pre-ram;
+	bootph-all;
 };
 
 &xin24m {

arch/arm/include/asm/arch-rk3066/boot0.h

@@ -3,6 +3,81 @@
 #ifndef __ASM_ARCH_BOOT0_H__
 #define __ASM_ARCH_BOOT0_H__
 
-#include <asm/arch-rockchip/boot0.h>
+#include <asm/arch-rockchip/boot_mode.h>
 
+/*
+ * Execution starts on the instruction following this 4-byte header
+ * (containing the magic 'RK30'). This magic constant will be written into
+ * the final image by the rkimage tool, but we need to reserve space for it here.
+ */
+#ifdef CONFIG_SPL_BUILD
+	b	1f  /* if overwritten, entry-address is at the next word */
+1:
+#endif
+
+#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM)
+/*
+ * Keep track of the re-entries with help of the lr register.
+ * This binary can be re-used and called from various BROM functions.
+ * Only when it's called from the part that handles SPI, NAND or EMMC
+ * hardware it needs to early return to BROM ones.
+ * In download mode when it handles data on USB OTG and UART0
+ * this section must be skipped.
+ */
+	ldr	r3, =CONFIG_ROCKCHIP_BOOT_LR_REG
+	cmp	lr, r3          /* if (LR != CONFIG_ROCKCHIP_BOOT_LR_REG)        */
+	bne	reset           /*     goto reset;                               */
+/*
+ * Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in
+ * support to enter download mode on return to BROM. This binary must check
+ * the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's set.
+ * It then returns to BROM to the end of the function that reads boot blocks.
+ * From there the BROM code goes into a download mode and waits for data
+ * on USB OTG and UART0.
+ */
+	ldr	r2, =BOOT_BROM_DOWNLOAD
+	ldr	r3, =CONFIG_ROCKCHIP_BOOT_MODE_REG
+	ldr	r0, [r3]        /* if (readl(CONFIG_ROCKCHIP_BOOT_MODE_REG) !=   */
+	cmp	r0, r2          /*     BOOT_BROM_DOWNLOAD) {                     */
+	bne	early_return    /*     goto early_return;                        */
+				/* } else {                                      */
+	mov	r0, #0
+	str	r0, [r3]        /*     writel(0, CONFIG_ROCKCHIP_BOOT_MODE_REG); */
+
+	ldr	r3, =CONFIG_ROCKCHIP_BOOT_RETURN_REG
+	bx	r3              /*     return to CONFIG_ROCKCHIP_BOOT_RETURN_REG;*/
+				/* }                                             */
+early_return:
+	bx	lr              /* return to LR in BROM                          */
+
+SAVE_SP_ADDR:
+	.word 0
+
+	.globl save_boot_params
+save_boot_params:
+	push	{r1-r12, lr}
+	ldr	r0, =SAVE_SP_ADDR
+	str	sp, [r0]
+	b	save_boot_params_ret
+
+	.globl back_to_bootrom
+back_to_bootrom:
+	ldr	r0, =SAVE_SP_ADDR
+	ldr	sp, [r0]
+	mov	r0, #0
+	pop	{r1-r12, pc}
+#endif
+
+#if (defined(CONFIG_SPL_BUILD))
+/* U-Boot proper of armv7 does not need this */
+	b reset
+#endif
+
+/*
+ * For armv7, the addr '_start' will be used as vector start address
+ * and is written to the VBAR register, which needs to aligned to 0x20.
+ */
+	.align(5), 0x0
+_start:
+	ARM_VECTORS
 #endif

arch/arm/mach-rockchip/Kconfig

@@ -359,6 +359,8 @@ config ROCKCHIP_RV1126
 	select BOARD_LATE_INIT
 	imply ROCKCHIP_COMMON_BOARD
 	imply OF_LIBFDT_OVERLAY
+	imply ROCKCHIP_OTP
+	imply MISC_INIT_R
 	imply TPL_DM
 	imply TPL_LIBCOMMON_SUPPORT
 	imply TPL_LIBGENERIC_SUPPORT
@@ -401,7 +403,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM
 config TPL_ROCKCHIP_BACK_TO_BROM
 	bool "TPL returns to bootrom"
 	default y
-	select ROCKCHIP_BROM_HELPER
+	select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066
 	select TPL_BOOTROM_SUPPORT
 	depends on TPL
 	help

arch/arm/mach-rockchip/rk3066/Kconfig

@@ -10,6 +10,14 @@ config TARGET_MK808
 config ROCKCHIP_BOOT_MODE_REG
 	default 0x20004040
 
+config ROCKCHIP_BOOT_LR_REG
+	hex
+	default 0x00001058
+
+config ROCKCHIP_BOOT_RETURN_REG
+	hex
+	default 0x00001100
+
 config SYS_SOC
 	default "rk3066"
 

arch/arm/mach-rockchip/rk3588/Kconfig

@@ -125,6 +125,13 @@ config TARGET_ROCK5B_RK3588
 	  USB PD over USB Type-C
 	  Size: 100mm x 72mm (Pico-ITX form factor)
 
+config TARGET_QUARTZPRO64_RK3588
+	bool "Pine64 QuartzPro64 RK3588 board"
+	select BOARD_LATE_INIT
+	help
+	  Pine64 QuartzPro64 is a Rockchip RK3588 based SBC (Single Board
+	  Computer) by Pine64.
+
 config ROCKCHIP_BOOT_MODE_REG
 	default 0xfd588080
 
@@ -139,6 +146,7 @@ config SYS_MALLOC_F_LEN
 
 source board/edgeble/neural-compute-module-6/Kconfig
 source board/friendlyelec/nanopc-t6-rk3588/Kconfig
+source board/pine64/quartzpro64-rk3588/Kconfig
 source board/rockchip/evb_rk3588/Kconfig
 source board/radxa/rock5a-rk3588s/Kconfig
 source board/radxa/rock5b-rk3588/Kconfig

board/pine64/quartzpro64-rk3588/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_QUARTZPRO64_RK3588
+
+config SYS_BOARD
+	default "quartzpro64-rk3588"
+
+config SYS_VENDOR
+	default "pine64"
+
+config SYS_CONFIG_NAME
+	default "quartzpro64-rk3588"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif

board/pine64/quartzpro64-rk3588/MAINTAINERS

@@ -0,0 +1,8 @@
+QUARTZPRO64-RK3588
+M:	Tom Fitzhenry <tom@tom-fitzhenry.me.uk>
+S:	Maintained
+F:	board/pine64/quartzpro64-rk3588
+F:	include/configs/quartzpro64-rk3588.h
+F:	configs/quartzpro64-rk3588_defconfig
+F:	arch/arm/dts/rk3588-quartzpro64.dts
+F:	arch/arm/dts/rk3588-quartzpro64-u-boot.dtsi

board/pine64/quartzpro64-rk3588/Makefile

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier:     GPL-2.0+
+
+obj-y += quartzpro64-rk3588.o

board/pine64/quartzpro64-rk3588/quartzpro64-rk3588.c

@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 Google, Inc
+ */
+
+#include <fdtdec.h>
+#include <fdt_support.h>
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int quartzpro64_add_reserved_memory_fdt_nodes(void *new_blob)
+{
+	struct fdt_memory gap1 = {
+		.start = 0x3fc000000,
+		.end = 0x3fc4fffff,
+	};
+	struct fdt_memory gap2 = {
+		.start = 0x3fff00000,
+		.end = 0x3ffffffff,
+	};
+	unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
+	unsigned int ret;
+
+	/*
+	 * Inject the reserved-memory nodes into the DTS
+	 */
+	ret = fdtdec_add_reserved_memory(new_blob, "gap1", &gap1,  NULL, 0,
+					 NULL, flags);
+	if (ret)
+		return ret;
+
+	return fdtdec_add_reserved_memory(new_blob, "gap2", &gap2,  NULL, 0,
+					  NULL, flags);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return quartzpro64_add_reserved_memory_fdt_nodes(blob);
+}
+#endif

board/theobroma-systems/ringneck_px30/ringneck-px30.c

@@ -16,12 +16,14 @@
 #include <usb.h>
 #include <dm/pinctrl.h>
 #include <dm/uclass-internal.h>
+#include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/setup.h>
 #include <asm/arch-rockchip/clock.h>
 #include <asm/arch-rockchip/hardware.h>
 #include <asm/arch-rockchip/periph.h>
 #include <asm/arch-rockchip/misc.h>
+#include <linux/delay.h>
 #include <power/regulator.h>
 #include <u-boot/sha256.h>
 
@@ -169,3 +171,54 @@ int misc_init_r(void)
 
 	return 0;
 }
+
+#define STM32_RST	100 /* GPIO3_A4 */
+#define STM32_BOOT	101 /* GPIO3_A5 */
+
+void spl_board_init(void)
+{
+	/*
+	 * Glitches on STM32_BOOT and STM32_RST lines during poweroff or power
+	 * on may put the STM32 companion microcontroller into DFU mode, let's
+	 * always reset it into normal mode instead.
+	 * Toggling the STM32_RST line is safe to do with the ATtiny companion
+	 * microcontroller variant because it will not trigger an MCU reset
+	 * since only a UPDI reset command will. Since a UPDI reset is difficult
+	 * to mistakenly trigger, glitches to the lines are theoretically also
+	 * incapable of triggering an actual ATtiny reset.
+	 */
+	int ret;
+
+	ret = gpio_request(STM32_RST, "STM32_RST");
+	if (ret) {
+		debug("Failed to request STM32_RST\n");
+		return;
+	}
+
+	ret = gpio_request(STM32_BOOT, "STM32_BOOT");
+	if (ret) {
+		debug("Failed to request STM32_BOOT\n");
+		return;
+	}
+
+	/* Rely on HW pull-down for inactive level */
+	ret = gpio_direction_input(STM32_BOOT);
+	if (ret) {
+		debug("Failed to configure STM32_BOOT as input\n");
+		return;
+	}
+
+	ret = gpio_direction_output(STM32_RST, 0);
+	if (ret) {
+		debug("Failed to configure STM32_RST as output low\n");
+		return;
+	}
+
+	mdelay(1);
+
+	ret = gpio_direction_output(STM32_RST, 1);
+	if (ret) {
+		debug("Failed to configure STM32_RST as output high\n");
+		return;
+	}
+}

configs/quartzpro64-rk3588_defconfig

@@ -0,0 +1,72 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_DEFAULT_DEVICE_TREE="rk3588-quartzpro64"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_QUARTZPRO64_RK3588=y
+CONFIG_SPL_STACK=0x400000
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-quartzpro64.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x4000000
+CONFIG_SPL_BSS_MAX_SIZE=0x4000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_RTL8169=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_ERRNO_STR=y

configs/ringneck-px30_defconfig

@@ -38,6 +38,7 @@ CONFIG_SPL_PAD_TO=0x0
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x4000000
 CONFIG_SPL_BSS_MAX_SIZE=0x4000
+CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
@@ -53,6 +54,7 @@ CONFIG_SPL_ATF=y
 # CONFIG_CMD_LZMADEC is not set
 # CONFIG_CMD_UNZIP is not set
 CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y

doc/board/rockchip/rockchip.rst

@@ -116,6 +116,7 @@ List of mainline supported Rockchip boards:
      - Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588)
      - Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588)
      - FriendlyElec NanoPC-T6 (nanopc-t6-rk3588)
+     - Pine64 QuartzPro64 (quartzpro64-rk3588)
      - Radxa ROCK 5A (rock5a-rk3588s)
      - Radxa ROCK 5B (rock5b-rk3588)
      - Xunlong Orange Pi 5 (orangepi-5-rk3588s)

drivers/misc/rockchip-otp.c

@@ -61,11 +61,20 @@
 #define RK3588_OTPC_INT_ST		0x0084
 #define RK3588_RD_DONE			BIT(1)
 
+#define RV1126_OTP_NVM_CEB		0x00
+#define RV1126_OTP_NVM_RSTB		0x04
+#define RV1126_OTP_NVM_ST		0x18
+#define RV1126_OTP_NVM_RADDR		0x1C
+#define RV1126_OTP_NVM_RSTART		0x20
+#define RV1126_OTP_NVM_RDATA		0x24
+#define RV1126_OTP_READ_ST		0x30
+
 struct rockchip_otp_plat {
 	void __iomem *base;
 };
 
 struct rockchip_otp_data {
+	int (*init)(struct udevice *dev);
 	int (*read)(struct udevice *dev, int offset, void *buf, int size);
 	int offset;
 	int size;
@@ -232,6 +241,48 @@ static int rockchip_rk3588_otp_read(struct udevice *dev, int offset,
 	return 0;
 }
 
+static int rockchip_rv1126_otp_init(struct udevice *dev)
+{
+	struct rockchip_otp_plat *otp = dev_get_plat(dev);
+	int ret;
+
+	writel(0x0, otp->base + RV1126_OTP_NVM_CEB);
+	ret = rockchip_otp_poll_timeout(otp, 0x1, RV1126_OTP_NVM_ST);
+
+	if (ret)
+		return ret;
+
+	writel(0x1, otp->base + RV1126_OTP_NVM_RSTB);
+	ret = rockchip_otp_poll_timeout(otp, 0x4, RV1126_OTP_NVM_ST);
+
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int rockchip_rv1126_otp_read(struct udevice *dev, int offset, void *buf,
+				    int size)
+{
+	struct rockchip_otp_plat *otp = dev_get_plat(dev);
+	u32 status = 0;
+	u8 *buffer = buf;
+	int ret = 0;
+
+	while (size--) {
+		writel(offset++, otp->base + RV1126_OTP_NVM_RADDR);
+		writel(0x1, otp->base + RV1126_OTP_NVM_RSTART);
+		ret = readl_poll_timeout(otp->base + RV1126_OTP_READ_ST,
+					 status, !status, OTPC_TIMEOUT);
+		if (ret)
+			return ret;
+
+		*buffer++ = (u8)(readl(otp->base + RV1126_OTP_NVM_RDATA) & 0xFF);
+	}
+
+	return 0;
+}
+
 static int rockchip_otp_read(struct udevice *dev, int offset,
 			     void *buf, int size)
 {
@@ -286,6 +337,20 @@ static int rockchip_otp_of_to_plat(struct udevice *dev)
 	return 0;
 }
 
+static int rockchip_otp_probe(struct udevice *dev)
+{
+	struct rockchip_otp_data *data;
+
+	data = (struct rockchip_otp_data *)dev_get_driver_data(dev);
+	if (!data)
+		return -EINVAL;
+
+	if (data->init)
+		return data->init(dev);
+
+	return 0;
+}
+
 static const struct rockchip_otp_data px30_data = {
 	.read = rockchip_px30_otp_read,
 	.size = 0x40,
@@ -304,6 +369,12 @@ static const struct rockchip_otp_data rk3588_data = {
 	.block_size = 4,
 };
 
+static const struct rockchip_otp_data rv1126_data = {
+	.init = rockchip_rv1126_otp_init,
+	.read = rockchip_rv1126_otp_read,
+	.size = 0x40,
+};
+
 static const struct udevice_id rockchip_otp_ids[] = {
 	{
 		.compatible = "rockchip,px30-otp",
@@ -321,6 +392,10 @@ static const struct udevice_id rockchip_otp_ids[] = {
 		.compatible = "rockchip,rk3588-otp",
 		.data = (ulong)&rk3588_data,
 	},
+	{
+		.compatible = "rockchip,rv1126-otp",
+		.data = (ulong)&rv1126_data,
+	},
 	{}
 };
 
@@ -331,4 +406,5 @@ U_BOOT_DRIVER(rockchip_otp) = {
 	.of_to_plat = rockchip_otp_of_to_plat,
 	.plat_auto = sizeof(struct rockchip_otp_plat),
 	.ops = &rockchip_otp_ops,
+	.probe = rockchip_otp_probe,
 };

include/configs/quartzpro64-rk3588.h

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ * Copyright 2023 Google, Inc
+ */
+
+#ifndef __QUARTZPRO64_RK3588_H
+#define __QUARTZPRO64_RK3588_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+		"stdout=serial,vidconsole\0" \
+		"stderr=serial,vidconsole\0"
+
+#include <configs/rk3588_common.h>
+
+#endif /* __QUARTZPRO64_RK3588_H */