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ppc: Remove xpedite boards
These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this includes the last ARCH_MPC8572 platform, remove that as well. Cc: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Peter Tyser <ptyser@xes-inc.com>
This commit is contained in:
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66e3c64f2c
commit
ed7fe2bee1
44 changed files with 5 additions and 3765 deletions
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@ -185,20 +185,6 @@ config TARGET_KMCENT2
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bool "Support kmcent2"
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bool "Support kmcent2"
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select VENDOR_KM
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select VENDOR_KM
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config TARGET_XPEDITE520X
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bool "Support xpedite520x"
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select ARCH_MPC8548
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config TARGET_XPEDITE537X
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bool "Support xpedite537x"
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select ARCH_MPC8572
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# Use DDR3 controller with DDR2 DIMMs on this board
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select SYS_FSL_DDRC_GEN3
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config TARGET_XPEDITE550X
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bool "Support xpedite550x"
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select ARCH_P2020
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config TARGET_UCP1020
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config TARGET_UCP1020
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bool "Support uCP1020"
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bool "Support uCP1020"
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select ARCH_P1020
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select ARCH_P1020
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@ -374,23 +360,6 @@ config ARCH_MPC8560
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select FSL_LAW
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select FSL_LAW
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select SYS_FSL_HAS_DDR1
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select SYS_FSL_HAS_DDR1
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config ARCH_MPC8572
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bool
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select FSL_LAW
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select SYS_FSL_ERRATUM_A004508
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select SYS_FSL_ERRATUM_A005125
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select SYS_FSL_ERRATUM_DDR_115
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select SYS_FSL_ERRATUM_DDR111_DDR134
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select FSL_PCIE_RESET
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select SYS_FSL_HAS_DDR2
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_BE
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select SYS_FSL_SEC_COMPAT_2
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select SYS_PPC_E500_USE_DEBUG_TLB
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select FSL_ELBC
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imply CMD_NAND
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config ARCH_P1010
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config ARCH_P1010
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bool
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bool
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select FSL_LAW
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select FSL_LAW
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@ -865,7 +834,6 @@ config MAX_CPUS
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ARCH_T2080
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ARCH_T2080
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default 2 if ARCH_B4420 || \
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default 2 if ARCH_B4420 || \
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ARCH_BSC9132 || \
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ARCH_BSC9132 || \
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ARCH_MPC8572 || \
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ARCH_P1020 || \
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ARCH_P1020 || \
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ARCH_P1021 || \
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ARCH_P1021 || \
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ARCH_P1023 || \
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ARCH_P1023 || \
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@ -891,7 +859,6 @@ config SYS_CCSRBAR_DEFAULT
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ARCH_MPC8544 || \
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ARCH_MPC8544 || \
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ARCH_MPC8548 || \
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ARCH_MPC8548 || \
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ARCH_MPC8560 || \
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ARCH_MPC8560 || \
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ARCH_MPC8572 || \
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ARCH_P1010 || \
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ARCH_P1010 || \
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ARCH_P1011 || \
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ARCH_P1011 || \
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ARCH_P1020 || \
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ARCH_P1020 || \
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@ -1104,7 +1071,6 @@ config SYS_FSL_NUM_LAWS
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ARCH_BSC9132 || \
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ARCH_BSC9132 || \
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ARCH_C29X || \
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ARCH_C29X || \
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ARCH_MPC8536 || \
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ARCH_MPC8536 || \
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ARCH_MPC8572 || \
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ARCH_P1010 || \
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ARCH_P1010 || \
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ARCH_P1011 || \
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ARCH_P1011 || \
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ARCH_P1020 || \
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ARCH_P1020 || \
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@ -1151,8 +1117,7 @@ config SYS_PPC_E500_DEBUG_TLB
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depends on SYS_PPC_E500_USE_DEBUG_TLB
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depends on SYS_PPC_E500_USE_DEBUG_TLB
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default 0 if ARCH_MPC8544 || ARCH_MPC8548
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default 0 if ARCH_MPC8544 || ARCH_MPC8548
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default 1 if ARCH_MPC8536
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default 1 if ARCH_MPC8536
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default 2 if ARCH_MPC8572 || \
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default 2 if ARCH_P1011 || \
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ARCH_P1011 || \
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ARCH_P1020 || \
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ARCH_P1020 || \
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ARCH_P1021 || \
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ARCH_P1021 || \
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ARCH_P1024 || \
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ARCH_P1024 || \
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@ -1216,9 +1181,6 @@ source "board/freescale/t208xrdb/Kconfig"
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source "board/freescale/t4rdb/Kconfig"
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source "board/freescale/t4rdb/Kconfig"
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source "board/keymile/Kconfig"
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source "board/keymile/Kconfig"
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source "board/socrates/Kconfig"
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source "board/socrates/Kconfig"
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source "board/xes/xpedite520x/Kconfig"
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source "board/xes/xpedite537x/Kconfig"
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source "board/xes/xpedite550x/Kconfig"
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source "board/Arcturus/ucp1020/Kconfig"
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source "board/Arcturus/ucp1020/Kconfig"
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endmenu
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endmenu
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@ -61,7 +61,6 @@ obj-$(CONFIG_ARCH_C29X) += c29x_serdes.o
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obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
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obj-$(CONFIG_ARCH_MPC8536) += mpc8536_serdes.o
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obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
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obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
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obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
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obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o
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obj-$(CONFIG_ARCH_MPC8572) += mpc8572_serdes.o
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obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
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obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
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obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o
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obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o
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obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o
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obj-$(CONFIG_ARCH_P1020) += p1021_serdes.o
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@ -1,74 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*/
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#include <config.h>
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#include <common.h>
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#include <log.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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#define SRDS1_MAX_LANES 8
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static u32 serdes1_prtcl_map;
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static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
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[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
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[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
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[0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
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[0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3},
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[0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
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[0xc] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
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[0xd] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
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[0xe] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
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[0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
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};
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int is_serdes_configured(enum srds_prtcl prtcl)
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{
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if (!(serdes1_prtcl_map & (1 << NONE)))
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fsl_serdes_init();
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return (1 << prtcl) & serdes1_prtcl_map;
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}
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void fsl_serdes_init(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 pordevsr = in_be32(&gur->pordevsr);
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u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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int lane;
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if (serdes1_prtcl_map & (1 << NONE))
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return;
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debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
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if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
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printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
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return;
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}
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for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
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serdes1_prtcl_map |= (1 << lane_prtcl);
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}
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if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
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serdes1_prtcl_map |= (1 << SGMII_TSEC1);
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if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
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serdes1_prtcl_map |= (1 << SGMII_TSEC2);
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if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
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serdes1_prtcl_map |= (1 << SGMII_TSEC3);
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if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
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serdes1_prtcl_map |= (1 << SGMII_TSEC4);
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/* Set the first bit to indicate serdes has been initialized */
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serdes1_prtcl_map |= (1 << NONE);
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}
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@ -13,10 +13,6 @@ config TARGET_SBC8641D
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select ARCH_MPC8641
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select ARCH_MPC8641
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select BOARD_EARLY_INIT_F
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select BOARD_EARLY_INIT_F
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config TARGET_XPEDITE517X
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bool "Support xpedite517x"
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select ARCH_MPC8641
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endchoice
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endchoice
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config ARCH_MPC8610
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config ARCH_MPC8610
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@ -52,6 +48,5 @@ config SYS_FSL_NUM_LAWS
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If not sure, do not change.
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If not sure, do not change.
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source "board/sbc8641d/Kconfig"
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source "board/sbc8641d/Kconfig"
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source "board/xes/xpedite517x/Kconfig"
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endmenu
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endmenu
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@ -84,7 +84,7 @@ enum law_trgt_if {
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#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
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#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
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LAW_TRGT_IF_OCN_DSP = 0x03,
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LAW_TRGT_IF_OCN_DSP = 0x03,
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#else
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#else
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#if !defined(CONFIG_ARCH_MPC8572) && !defined(CONFIG_ARCH_P2020)
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#if !defined(CONFIG_ARCH_P2020)
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LAW_TRGT_IF_PCIE_3 = 0x03,
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LAW_TRGT_IF_PCIE_3 = 0x03,
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#endif
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#endif
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#endif
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#endif
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@ -120,7 +120,7 @@ enum law_trgt_if {
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#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
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#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
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#endif
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#endif
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#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
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#if defined(CONFIG_ARCH_P2020)
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#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
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#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
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#endif
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#endif
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#endif /* CONFIG_FSL_CORENET */
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#endif /* CONFIG_FSL_CORENET */
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@ -2853,7 +2853,7 @@ struct ccsr_pman {
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#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
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#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
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#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
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#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
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#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
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#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
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#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
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#if defined(CONFIG_ARCH_P2020)
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#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
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#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
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#else
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#else
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#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
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#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
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@ -4,7 +4,6 @@
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o
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obj-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o
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obj-$(CONFIG_ARCH_MPC8572) += fsl_8xxx_clk.o
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obj-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o
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obj-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o
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obj-$(CONFIG_ARCH_P2020) += fsl_8xxx_clk.o
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obj-$(CONFIG_ARCH_P2020) += fsl_8xxx_clk.o
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obj-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o
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obj-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o
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@ -1,12 +0,0 @@
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if TARGET_XPEDITE517X
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config SYS_BOARD
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default "xpedite517x"
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config SYS_VENDOR
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default "xes"
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config SYS_CONFIG_NAME
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default "xpedite517x"
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endif
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@ -1,6 +0,0 @@
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XPEDITE517X BOARD
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M: Peter Tyser <ptyser@xes-inc.com>
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S: Maintained
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F: board/xes/xpedite517x/
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F: include/configs/xpedite517x.h
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F: configs/xpedite517x_defconfig
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@ -1,8 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y += xpedite517x.o
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obj-y += ddr.o
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obj-y += law.o
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@ -1,124 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2009 Extreme Engineering Solutions, Inc.
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* Copyright 2007-2008 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#include <log.h>
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void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
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{
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i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
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sizeof(ddr2_spd_eeprom_t));
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}
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/*
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* There are four board-specific SDRAM timing parameters which must be
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* calculated based on the particular PCB artwork. These are:
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* 1.) CPO (Read Capture Delay)
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* - TIMING_CFG_2 register
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* Source: Calculation based on board trace lengths and
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* chip-specific internal delays.
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* 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
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* - TIMING_CFG_2 register
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* Source: Calculation based on board trace lengths.
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* Unless clock and DQ lanes are very different
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* lengths (>2"), this should be set to the nominal value
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* of 1/2 clock delay.
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* 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
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* - DDR_SDRAM_CLK_CNTL register
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* Source: Signal Integrity Simulations
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* 4.) 2T Timing on Addr/Ctl
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* - TIMING_CFG_2 register
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* Source: Signal Integrity Simulations
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||||||
* Usually only needed with heavy load/very high speed (>DDR2-800)
|
|
||||||
*
|
|
||||||
* PCB routing on the XPedite5170 is nearly identical to the XPedite5370
|
|
||||||
* so we use the XPedite5370 settings as a basis for the XPedite5170.
|
|
||||||
*/
|
|
||||||
|
|
||||||
typedef struct board_memctl_options {
|
|
||||||
uint16_t datarate_mhz_low;
|
|
||||||
uint16_t datarate_mhz_high;
|
|
||||||
uint8_t clk_adjust;
|
|
||||||
uint8_t cpo_override;
|
|
||||||
uint8_t write_data_delay;
|
|
||||||
} board_memctl_options_t;
|
|
||||||
|
|
||||||
static struct board_memctl_options bopts_ctrl[][2] = {
|
|
||||||
{
|
|
||||||
/* Controller 0 */
|
|
||||||
{
|
|
||||||
/* DDR2 600/667 */
|
|
||||||
.datarate_mhz_low = 500,
|
|
||||||
.datarate_mhz_high = 750,
|
|
||||||
.clk_adjust = 5,
|
|
||||||
.cpo_override = 8,
|
|
||||||
.write_data_delay = 2,
|
|
||||||
},
|
|
||||||
{
|
|
||||||
/* DDR2 800 */
|
|
||||||
.datarate_mhz_low = 750,
|
|
||||||
.datarate_mhz_high = 850,
|
|
||||||
.clk_adjust = 5,
|
|
||||||
.cpo_override = 9,
|
|
||||||
.write_data_delay = 2,
|
|
||||||
},
|
|
||||||
},
|
|
||||||
{
|
|
||||||
/* Controller 1 */
|
|
||||||
{
|
|
||||||
/* DDR2 600/667 */
|
|
||||||
.datarate_mhz_low = 500,
|
|
||||||
.datarate_mhz_high = 750,
|
|
||||||
.clk_adjust = 5,
|
|
||||||
.cpo_override = 7,
|
|
||||||
.write_data_delay = 2,
|
|
||||||
},
|
|
||||||
{
|
|
||||||
/* DDR2 800 */
|
|
||||||
.datarate_mhz_low = 750,
|
|
||||||
.datarate_mhz_high = 850,
|
|
||||||
.clk_adjust = 5,
|
|
||||||
.cpo_override = 8,
|
|
||||||
.write_data_delay = 2,
|
|
||||||
},
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
void fsl_ddr_board_options(memctl_options_t *popts,
|
|
||||||
dimm_params_t *pdimm,
|
|
||||||
unsigned int ctrl_num)
|
|
||||||
{
|
|
||||||
struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
|
|
||||||
sys_info_t sysinfo;
|
|
||||||
int i;
|
|
||||||
unsigned int datarate;
|
|
||||||
|
|
||||||
get_sys_info(&sysinfo);
|
|
||||||
datarate = get_ddr_freq(0) / 1000000;
|
|
||||||
|
|
||||||
for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
|
|
||||||
if ((bopts[i].datarate_mhz_low <= datarate) &&
|
|
||||||
(bopts[i].datarate_mhz_high >= datarate)) {
|
|
||||||
debug("controller %d:\n", ctrl_num);
|
|
||||||
debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
|
|
||||||
debug(" cpo = %d\n", bopts[i].cpo_override);
|
|
||||||
debug(" write_data_delay = %d\n",
|
|
||||||
bopts[i].write_data_delay);
|
|
||||||
popts->clk_adjust = bopts[i].clk_adjust;
|
|
||||||
popts->cpo_override = bopts[i].cpo_override;
|
|
||||||
popts->write_data_delay = bopts[i].write_data_delay;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Factors to consider for half-strength driver enable:
|
|
||||||
* - number of DIMMs installed
|
|
||||||
*/
|
|
||||||
popts->half_strength_driver_enable = 0;
|
|
||||||
}
|
|
|
@ -1,27 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
|
||||||
*
|
|
||||||
* (C) Copyright 2000
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/fsl_law.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Notes:
|
|
||||||
* CCSRBAR don't need a configured Local Access Window.
|
|
||||||
* If flash is 8M at default position (last 8M), no LAW needed.
|
|
||||||
*/
|
|
||||||
|
|
||||||
struct law_entry law_table[] = {
|
|
||||||
SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
|
|
||||||
#ifdef CONFIG_SYS_NAND_BASE
|
|
||||||
/* NAND LAW covers 2 NAND flashes */
|
|
||||||
SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_512K, LAW_TRGT_IF_LBC),
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
int num_law_entries = ARRAY_SIZE(law_table);
|
|
|
@ -1,86 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2009 Extreme Engineering Solutions, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <init.h>
|
|
||||||
#include <asm/global_data.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
#include <fsl_ddr_sdram.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <fdt_support.h>
|
|
||||||
#include <pca953x.h>
|
|
||||||
#include "../common/fsl_8xxx_misc.h"
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
|
|
||||||
extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Print out which flash was booted from and if booting from the 2nd flash,
|
|
||||||
* swap flash chip selects to maintain consistent flash numbering/addresses.
|
|
||||||
*/
|
|
||||||
static void flash_cs_fixup(void)
|
|
||||||
{
|
|
||||||
int flash_sel;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Print boot dev and swap flash flash chip selects if booted from 2nd
|
|
||||||
* flash. Swapping chip selects presents user with a common memory
|
|
||||||
* map regardless of which flash was booted from.
|
|
||||||
*/
|
|
||||||
flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
|
|
||||||
CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
|
|
||||||
printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
|
|
||||||
|
|
||||||
if (flash_sel) {
|
|
||||||
set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
|
|
||||||
set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
|
|
||||||
|
|
||||||
set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
|
|
||||||
set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
int board_early_init_r(void)
|
|
||||||
{
|
|
||||||
/* Initialize PCA9557 devices */
|
|
||||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
|
|
||||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
|
|
||||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
|
|
||||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
|
|
||||||
|
|
||||||
flash_cs_fixup();
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int dram_init(void)
|
|
||||||
{
|
|
||||||
phys_size_t dram_size = fsl_ddr_sdram();
|
|
||||||
|
|
||||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
|
||||||
/* Initialize and enable DDR ECC */
|
|
||||||
ddr_enable_ecc(dram_size);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
gd->ram_size = dram_size;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
|
||||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
|
||||||
{
|
|
||||||
#ifdef CONFIG_PCI
|
|
||||||
ft_board_pci_setup(blob, bd);
|
|
||||||
#endif
|
|
||||||
ft_cpu_setup(blob, bd);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
#endif
|
|
|
@ -1,12 +0,0 @@
|
||||||
if TARGET_XPEDITE520X
|
|
||||||
|
|
||||||
config SYS_BOARD
|
|
||||||
default "xpedite520x"
|
|
||||||
|
|
||||||
config SYS_VENDOR
|
|
||||||
default "xes"
|
|
||||||
|
|
||||||
config SYS_CONFIG_NAME
|
|
||||||
default "xpedite520x"
|
|
||||||
|
|
||||||
endif
|
|
|
@ -1,6 +0,0 @@
|
||||||
XPEDITE520X BOARD
|
|
||||||
M: Peter Tyser <ptyser@xes-inc.com>
|
|
||||||
S: Maintained
|
|
||||||
F: board/xes/xpedite520x/
|
|
||||||
F: include/configs/xpedite520x.h
|
|
||||||
F: configs/xpedite520x_defconfig
|
|
|
@ -1,11 +0,0 @@
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
# Copyright 2008 Extreme Engineering Solutions, Inc.
|
|
||||||
# Copyright 2004 Freescale Semiconductor.
|
|
||||||
# (C) Copyright 2001-2006
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
|
|
||||||
obj-y += xpedite520x.o
|
|
||||||
obj-y += ddr.o
|
|
||||||
obj-y += law.o
|
|
||||||
obj-y += tlb.o
|
|
|
@ -1,68 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0
|
|
||||||
/*
|
|
||||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <i2c.h>
|
|
||||||
|
|
||||||
#include <fsl_ddr_sdram.h>
|
|
||||||
#include <fsl_ddr_dimm_params.h>
|
|
||||||
|
|
||||||
void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
|
|
||||||
{
|
|
||||||
i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
|
|
||||||
|
|
||||||
/* We use soldered memory, but use an SPD EEPROM to describe it.
|
|
||||||
* The SPD has an unspecified dimm type, but the DDR2 initialization
|
|
||||||
* code requires a specific type to be specified. This sets the type
|
|
||||||
* as a standard unregistered SO-DIMM. */
|
|
||||||
if (spd->dimm_type == 0) {
|
|
||||||
spd->dimm_type = 0x4;
|
|
||||||
((uchar *)spd)[63] += 0x4;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void fsl_ddr_board_options(memctl_options_t *popts,
|
|
||||||
dimm_params_t *pdimm,
|
|
||||||
unsigned int ctrl_num)
|
|
||||||
{
|
|
||||||
/*
|
|
||||||
* Factors to consider for clock adjust:
|
|
||||||
* - number of chips on bus
|
|
||||||
* - position of slot
|
|
||||||
* - DDR1 vs. DDR2?
|
|
||||||
* - ???
|
|
||||||
*
|
|
||||||
* This needs to be determined on a board-by-board basis.
|
|
||||||
* 0110 3/4 cycle late
|
|
||||||
* 0111 7/8 cycle late
|
|
||||||
*/
|
|
||||||
popts->clk_adjust = 7;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Factors to consider for CPO:
|
|
||||||
* - frequency
|
|
||||||
* - ddr1 vs. ddr2
|
|
||||||
*/
|
|
||||||
popts->cpo_override = 9;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Factors to consider for write data delay:
|
|
||||||
* - number of DIMMs
|
|
||||||
*
|
|
||||||
* 1 = 1/4 clock delay
|
|
||||||
* 2 = 1/2 clock delay
|
|
||||||
* 3 = 3/4 clock delay
|
|
||||||
* 4 = 1 clock delay
|
|
||||||
* 5 = 5/4 clock delay
|
|
||||||
* 6 = 3/2 clock delay
|
|
||||||
*/
|
|
||||||
popts->write_data_delay = 3;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Factors to consider for half-strength driver enable:
|
|
||||||
* - number of DIMMs installed
|
|
||||||
*/
|
|
||||||
popts->half_strength_driver_enable = 0;
|
|
||||||
}
|
|
|
@ -1,26 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2008 Extreme Engineering Solutions, Inc.
|
|
||||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
|
||||||
*
|
|
||||||
* (C) Copyright 2000
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/fsl_law.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Notes:
|
|
||||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
|
|
||||||
* If flash is 8M at default position (last 8M), no LAW needed.
|
|
||||||
*/
|
|
||||||
|
|
||||||
struct law_entry law_table[] = {
|
|
||||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
|
|
||||||
SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
|
|
||||||
SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
|
|
||||||
};
|
|
||||||
|
|
||||||
int num_law_entries = ARRAY_SIZE(law_table);
|
|
|
@ -1,68 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2008 Extreme Engineering Solutions, Inc.
|
|
||||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
|
||||||
*
|
|
||||||
* (C) Copyright 2000
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
|
|
||||||
struct fsl_e_tlb_entry tlb_table[] = {
|
|
||||||
/* TLB 0 - for temp stack in cache */
|
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
|
||||||
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
|
||||||
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
|
||||||
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
||||||
|
|
||||||
/* W**G* - NOR flashes */
|
|
||||||
/* This will be changed to *I*G* after relocation to RAM. */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
|
|
||||||
0, 0, BOOKE_PAGESZ_256M, 1),
|
|
||||||
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 1, BOOKE_PAGESZ_1M, 1),
|
|
||||||
|
|
||||||
/* *I*G* - NAND flash */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 2, BOOKE_PAGESZ_1M, 1),
|
|
||||||
|
|
||||||
#if CONFIG_PCI1
|
|
||||||
/* *I*G* - PCI MEM */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 3, BOOKE_PAGESZ_1G, 1),
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if CONFIG_PCI2
|
|
||||||
/* *I*G* - PCI MEM */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 4, BOOKE_PAGESZ_256M, 1),
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
|
|
||||||
/* *I*G* - PCI IO */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 5, BOOKE_PAGESZ_16M, 1),
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
|
|
@ -1,82 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2008 Extreme Engineering Solutions, Inc.
|
|
||||||
* Copyright 2004, 2007 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <command.h>
|
|
||||||
#include <init.h>
|
|
||||||
#include <pci.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
#include <asm/immap_85xx.h>
|
|
||||||
#include <asm/fsl_pci.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <asm/cache.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
#include <linux/libfdt.h>
|
|
||||||
#include <fdt_support.h>
|
|
||||||
#include <pca953x.h>
|
|
||||||
|
|
||||||
extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
|
|
||||||
|
|
||||||
static void flash_cs_fixup(void)
|
|
||||||
{
|
|
||||||
int flash_sel;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Print boot dev and swap flash flash chip selects if booted from 2nd
|
|
||||||
* flash. Swapping chip selects presents user with a common memory
|
|
||||||
* map regardless of which flash was booted from.
|
|
||||||
*/
|
|
||||||
flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
|
|
||||||
CONFIG_SYS_PCA953X_FLASH_PASS_CS));
|
|
||||||
printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
|
|
||||||
|
|
||||||
if (flash_sel) {
|
|
||||||
set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
|
|
||||||
set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
|
|
||||||
|
|
||||||
set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
|
|
||||||
set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
int board_early_init_r(void)
|
|
||||||
{
|
|
||||||
/* Initialize PCA9557 devices */
|
|
||||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
|
|
||||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Remap NOR flash region to caching-inhibited
|
|
||||||
* so that flash can be erased/programmed properly.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
|
||||||
flush_dcache();
|
|
||||||
invalidate_icache();
|
|
||||||
|
|
||||||
/* Invalidate existing TLB entry for NOR flash */
|
|
||||||
disable_tlb(0);
|
|
||||||
set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
|
|
||||||
(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 0, BOOKE_PAGESZ_256M, 1);
|
|
||||||
|
|
||||||
flash_cs_fixup();
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
|
||||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
|
||||||
{
|
|
||||||
#ifdef CONFIG_PCI
|
|
||||||
ft_board_pci_setup(blob, bd);
|
|
||||||
#endif
|
|
||||||
ft_cpu_setup(blob, bd);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
#endif
|
|
|
@ -1,12 +0,0 @@
|
||||||
if TARGET_XPEDITE537X
|
|
||||||
|
|
||||||
config SYS_BOARD
|
|
||||||
default "xpedite537x"
|
|
||||||
|
|
||||||
config SYS_VENDOR
|
|
||||||
default "xes"
|
|
||||||
|
|
||||||
config SYS_CONFIG_NAME
|
|
||||||
default "xpedite537x"
|
|
||||||
|
|
||||||
endif
|
|
|
@ -1,6 +0,0 @@
|
||||||
XPEDITE537X BOARD
|
|
||||||
M: Peter Tyser <ptyser@xes-inc.com>
|
|
||||||
S: Maintained
|
|
||||||
F: board/xes/xpedite537x/
|
|
||||||
F: include/configs/xpedite537x.h
|
|
||||||
F: configs/xpedite537x_defconfig
|
|
|
@ -1,11 +0,0 @@
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
# Copyright 2008 Extreme Engineering Solutions, Inc.
|
|
||||||
# Copyright 2007 Freescale Semiconductor, Inc.
|
|
||||||
# (C) Copyright 2001-2006
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
|
|
||||||
obj-y += xpedite537x.o
|
|
||||||
obj-y += ddr.o
|
|
||||||
obj-y += law.o
|
|
||||||
obj-y += tlb.o
|
|
|
@ -1,234 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2008 Extreme Engineering Solutions, Inc.
|
|
||||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <i2c.h>
|
|
||||||
#include <log.h>
|
|
||||||
|
|
||||||
#include <fsl_ddr_sdram.h>
|
|
||||||
#include <fsl_ddr_dimm_params.h>
|
|
||||||
|
|
||||||
void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
|
|
||||||
{
|
|
||||||
i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
|
|
||||||
sizeof(ddr2_spd_eeprom_t));
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* There are four board-specific SDRAM timing parameters which must be
|
|
||||||
* calculated based on the particular PCB artwork. These are:
|
|
||||||
* 1.) CPO (Read Capture Delay)
|
|
||||||
* - TIMING_CFG_2 register
|
|
||||||
* Source: Calculation based on board trace lengths and
|
|
||||||
* chip-specific internal delays.
|
|
||||||
* 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
|
|
||||||
* - TIMING_CFG_2 register
|
|
||||||
* Source: Calculation based on board trace lengths.
|
|
||||||
* Unless clock and DQ lanes are very different
|
|
||||||
* lengths (>2"), this should be set to the nominal value
|
|
||||||
* of 1/2 clock delay.
|
|
||||||
* 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
|
|
||||||
* - DDR_SDRAM_CLK_CNTL register
|
|
||||||
* Source: Signal Integrity Simulations
|
|
||||||
* 4.) 2T Timing on Addr/Ctl
|
|
||||||
* - TIMING_CFG_2 register
|
|
||||||
* Source: Signal Integrity Simulations
|
|
||||||
* Usually only needed with heavy load/very high speed (>DDR2-800)
|
|
||||||
*
|
|
||||||
* ====== XPedite5370 DDR2-600 read delay calculations ======
|
|
||||||
*
|
|
||||||
* See Freescale's App Note AN2583 as refrence. This document also
|
|
||||||
* contains the chip-specific delays for 8548E, 8572, etc.
|
|
||||||
*
|
|
||||||
* For MPC8572E
|
|
||||||
* Minimum chip delay (Ch 0): 1.372ns
|
|
||||||
* Maximum chip delay (Ch 0): 2.914ns
|
|
||||||
* Minimum chip delay (Ch 1): 1.220ns
|
|
||||||
* Maximum chip delay (Ch 1): 2.595ns
|
|
||||||
*
|
|
||||||
* CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps
|
|
||||||
*
|
|
||||||
* Minimum delay calc (Ch 0):
|
|
||||||
* clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
|
|
||||||
* 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps
|
|
||||||
* = 3808ps
|
|
||||||
* = 3.808ns
|
|
||||||
*
|
|
||||||
* Maximum delay calc (Ch 0):
|
|
||||||
* clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
|
|
||||||
* 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps
|
|
||||||
* = 6240ps
|
|
||||||
* = 6.240ns
|
|
||||||
*
|
|
||||||
* Minimum delay calc (Ch 1):
|
|
||||||
* clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
|
|
||||||
* 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps
|
|
||||||
* = 3288ps
|
|
||||||
* = 3.288ns
|
|
||||||
*
|
|
||||||
* Maximum delay calc (Ch 1):
|
|
||||||
* clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
|
|
||||||
* 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps
|
|
||||||
* = 5536ps
|
|
||||||
* = 5.536ns
|
|
||||||
*
|
|
||||||
* Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target)
|
|
||||||
* This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
|
|
||||||
* Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target)
|
|
||||||
* This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7)
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* ====== XPedite5370 DDR2-800 read delay calculations ======
|
|
||||||
*
|
|
||||||
* See Freescale's App Note AN2583 as refrence. This document also
|
|
||||||
* contains the chip-specific delays for 8548E, 8572, etc.
|
|
||||||
*
|
|
||||||
* For MPC8572E
|
|
||||||
* Minimum chip delay (Ch 0): 1.372ns
|
|
||||||
* Maximum chip delay (Ch 0): 2.914ns
|
|
||||||
* Minimum chip delay (Ch 1): 1.220ns
|
|
||||||
* Maximum chip delay (Ch 1): 2.595ns
|
|
||||||
*
|
|
||||||
* CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps
|
|
||||||
*
|
|
||||||
* Minimum delay calc (Ch 0):
|
|
||||||
* clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
|
|
||||||
* 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps
|
|
||||||
* = 3341ps
|
|
||||||
* = 3.341ns
|
|
||||||
*
|
|
||||||
* Maximum delay calc (Ch 0):
|
|
||||||
* clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
|
|
||||||
* 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps
|
|
||||||
* = 5673ps
|
|
||||||
* = 5.673ns
|
|
||||||
*
|
|
||||||
* Minimum delay calc (Ch 1):
|
|
||||||
* clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
|
|
||||||
* 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps
|
|
||||||
* = 2822ps
|
|
||||||
* = 2.822ns
|
|
||||||
*
|
|
||||||
* Maximum delay calc (Ch 1):
|
|
||||||
* clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
|
|
||||||
* 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps
|
|
||||||
* = 4968ps
|
|
||||||
* = 4.968ns
|
|
||||||
*
|
|
||||||
* Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target)
|
|
||||||
* This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9)
|
|
||||||
* Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target)
|
|
||||||
* This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
|
|
||||||
*
|
|
||||||
* Write latency (WR_DATA_DELAY) is calculated by doing the following:
|
|
||||||
*
|
|
||||||
* The DDR SDRAM specification requires DQS be received no sooner than
|
|
||||||
* 75% of an SDRAM clock period—and no later than 125% of a clock
|
|
||||||
* period—from the capturing clock edge of the command/address at the
|
|
||||||
* SDRAM.
|
|
||||||
*
|
|
||||||
* Based on the above tracelengths, the following are calculated:
|
|
||||||
* Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns
|
|
||||||
* Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns
|
|
||||||
* Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns
|
|
||||||
* Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns
|
|
||||||
*
|
|
||||||
* Difference in arrival time CLK vs. DQS:
|
|
||||||
* Ch. 0 0.072ns
|
|
||||||
* Ch. 1 0.138ns
|
|
||||||
*
|
|
||||||
* Both of these values are much less than 25% of the clock
|
|
||||||
* period at DDR2-600 or DDR2-800, so no additional delay is needed over
|
|
||||||
* the 1/2 cycle which normally aligns the first DQS transition
|
|
||||||
* exactly WL (CAS latency minus one cycle) after the CAS strobe.
|
|
||||||
* See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
|
|
||||||
* terminology corresponds to exactly one clock period delay after
|
|
||||||
* the CAS strobe. (due to the fact that the "delay" is referenced
|
|
||||||
* from the *falling* edge of the CLK, just after the rising edge
|
|
||||||
* which the CAS strobe is latched on.
|
|
||||||
*/
|
|
||||||
|
|
||||||
typedef struct board_memctl_options {
|
|
||||||
uint16_t datarate_mhz_low;
|
|
||||||
uint16_t datarate_mhz_high;
|
|
||||||
uint8_t clk_adjust;
|
|
||||||
uint8_t cpo_override;
|
|
||||||
uint8_t write_data_delay;
|
|
||||||
} board_memctl_options_t;
|
|
||||||
|
|
||||||
static struct board_memctl_options bopts_ctrl[][2] = {
|
|
||||||
{
|
|
||||||
/* Controller 0 */
|
|
||||||
{
|
|
||||||
/* DDR2 600/667 */
|
|
||||||
.datarate_mhz_low = 500,
|
|
||||||
.datarate_mhz_high = 750,
|
|
||||||
.clk_adjust = 5,
|
|
||||||
.cpo_override = 8,
|
|
||||||
.write_data_delay = 2,
|
|
||||||
},
|
|
||||||
{
|
|
||||||
/* DDR2 800 */
|
|
||||||
.datarate_mhz_low = 750,
|
|
||||||
.datarate_mhz_high = 850,
|
|
||||||
.clk_adjust = 5,
|
|
||||||
.cpo_override = 9,
|
|
||||||
.write_data_delay = 2,
|
|
||||||
},
|
|
||||||
},
|
|
||||||
{
|
|
||||||
/* Controller 1 */
|
|
||||||
{
|
|
||||||
/* DDR2 600/667 */
|
|
||||||
.datarate_mhz_low = 500,
|
|
||||||
.datarate_mhz_high = 750,
|
|
||||||
.clk_adjust = 5,
|
|
||||||
.cpo_override = 7,
|
|
||||||
.write_data_delay = 2,
|
|
||||||
},
|
|
||||||
{
|
|
||||||
/* DDR2 800 */
|
|
||||||
.datarate_mhz_low = 750,
|
|
||||||
.datarate_mhz_high = 850,
|
|
||||||
.clk_adjust = 5,
|
|
||||||
.cpo_override = 8,
|
|
||||||
.write_data_delay = 2,
|
|
||||||
},
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
void fsl_ddr_board_options(memctl_options_t *popts,
|
|
||||||
dimm_params_t *pdimm,
|
|
||||||
unsigned int ctrl_num)
|
|
||||||
{
|
|
||||||
struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
|
|
||||||
sys_info_t sysinfo;
|
|
||||||
int i;
|
|
||||||
unsigned int datarate;
|
|
||||||
|
|
||||||
get_sys_info(&sysinfo);
|
|
||||||
datarate = sysinfo.freq_ddrbus / 1000 / 1000;
|
|
||||||
|
|
||||||
for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
|
|
||||||
if ((bopts[i].datarate_mhz_low <= datarate) &&
|
|
||||||
(bopts[i].datarate_mhz_high >= datarate)) {
|
|
||||||
debug("controller %d:\n", ctrl_num);
|
|
||||||
debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
|
|
||||||
debug(" cpo = %d\n", bopts[i].cpo_override);
|
|
||||||
debug(" write_data_delay = %d\n",
|
|
||||||
bopts[i].write_data_delay);
|
|
||||||
popts->clk_adjust = bopts[i].clk_adjust;
|
|
||||||
popts->cpo_override = bopts[i].cpo_override;
|
|
||||||
popts->write_data_delay = bopts[i].write_data_delay;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Factors to consider for half-strength driver enable:
|
|
||||||
* - number of DIMMs installed
|
|
||||||
*/
|
|
||||||
popts->half_strength_driver_enable = 0;
|
|
||||||
}
|
|
|
@ -1,25 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2008 Extreme Engineering Solutions, Inc.
|
|
||||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
|
||||||
*
|
|
||||||
* (C) Copyright 2000
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/fsl_law.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Notes:
|
|
||||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
|
|
||||||
* If flash is 8M at default position (last 8M), no LAW needed.
|
|
||||||
*/
|
|
||||||
|
|
||||||
struct law_entry law_table[] = {
|
|
||||||
SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
|
|
||||||
SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
|
|
||||||
};
|
|
||||||
|
|
||||||
int num_law_entries = ARRAY_SIZE(law_table);
|
|
|
@ -1,82 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2008 Extreme Engineering Solutions, Inc.
|
|
||||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
|
||||||
*
|
|
||||||
* (C) Copyright 2000
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
|
|
||||||
struct fsl_e_tlb_entry tlb_table[] = {
|
|
||||||
/* TLB 0 - for temp stack in cache */
|
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
|
||||||
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
|
||||||
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
|
||||||
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
||||||
|
|
||||||
/* W**G* - NOR flashes */
|
|
||||||
/* This will be changed to *I*G* after relocation to RAM. */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
|
|
||||||
0, 0, BOOKE_PAGESZ_256M, 1),
|
|
||||||
|
|
||||||
/* *I*G* - CCSRBAR */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 1, BOOKE_PAGESZ_1M, 1),
|
|
||||||
|
|
||||||
/* *I*G* - NAND flash */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 2, BOOKE_PAGESZ_1M, 1),
|
|
||||||
|
|
||||||
/* **M** - Boot page for secondary processors */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
|
|
||||||
0, 3, BOOKE_PAGESZ_4K, 1),
|
|
||||||
|
|
||||||
#ifdef CONFIG_PCIE1
|
|
||||||
/* *I*G* - PCIe */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 4, BOOKE_PAGESZ_1G, 1),
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_PCIE2
|
|
||||||
/* *I*G* - PCIe */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 5, BOOKE_PAGESZ_256M, 1),
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_PCIE3
|
|
||||||
/* *I*G* - PCIe */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 6, BOOKE_PAGESZ_256M, 1),
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
|
|
||||||
/* *I*G* - PCIe */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 7, BOOKE_PAGESZ_64M, 1),
|
|
||||||
#endif
|
|
||||||
|
|
||||||
};
|
|
||||||
|
|
||||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
|
|
@ -1,82 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2008 Extreme Engineering Solutions, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <command.h>
|
|
||||||
#include <init.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
#include <asm/immap_85xx.h>
|
|
||||||
#include <asm/fsl_pci.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <asm/cache.h>
|
|
||||||
#include <linux/libfdt.h>
|
|
||||||
#include <fdt_support.h>
|
|
||||||
#include <pca953x.h>
|
|
||||||
|
|
||||||
extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
|
|
||||||
|
|
||||||
static void flash_cs_fixup(void)
|
|
||||||
{
|
|
||||||
int flash_sel;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Print boot dev and swap flash flash chip selects if booted from 2nd
|
|
||||||
* flash. Swapping chip selects presents user with a common memory
|
|
||||||
* map regardless of which flash was booted from.
|
|
||||||
*/
|
|
||||||
flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
|
|
||||||
CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
|
|
||||||
printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
|
|
||||||
|
|
||||||
if (flash_sel) {
|
|
||||||
set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
|
|
||||||
set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
|
|
||||||
|
|
||||||
set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
|
|
||||||
set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
int board_early_init_r(void)
|
|
||||||
{
|
|
||||||
/* Initialize PCA9557 devices */
|
|
||||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
|
|
||||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
|
|
||||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
|
|
||||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Remap NOR flash region to caching-inhibited
|
|
||||||
* so that flash can be erased/programmed properly.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
|
||||||
flush_dcache();
|
|
||||||
invalidate_icache();
|
|
||||||
|
|
||||||
/* Invalidate existing TLB entry for NOR flash */
|
|
||||||
disable_tlb(0);
|
|
||||||
set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
|
|
||||||
(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 0, BOOKE_PAGESZ_256M, 1);
|
|
||||||
|
|
||||||
flash_cs_fixup();
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
|
||||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
|
||||||
{
|
|
||||||
#ifdef CONFIG_PCI
|
|
||||||
ft_board_pci_setup(blob, bd);
|
|
||||||
#endif
|
|
||||||
ft_cpu_setup(blob, bd);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
#endif
|
|
|
@ -1,12 +0,0 @@
|
||||||
if TARGET_XPEDITE550X
|
|
||||||
|
|
||||||
config SYS_BOARD
|
|
||||||
default "xpedite550x"
|
|
||||||
|
|
||||||
config SYS_VENDOR
|
|
||||||
default "xes"
|
|
||||||
|
|
||||||
config SYS_CONFIG_NAME
|
|
||||||
default "xpedite550x"
|
|
||||||
|
|
||||||
endif
|
|
|
@ -1,6 +0,0 @@
|
||||||
XPEDITE550X BOARD
|
|
||||||
M: Peter Tyser <ptyser@xes-inc.com>
|
|
||||||
S: Maintained
|
|
||||||
F: board/xes/xpedite550x/
|
|
||||||
F: include/configs/xpedite550x.h
|
|
||||||
F: configs/xpedite550x_defconfig
|
|
|
@ -1,8 +0,0 @@
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
# Copyright 2007-2008 Freescale Semiconductor, Inc.
|
|
||||||
|
|
||||||
obj-y += xpedite550x.o
|
|
||||||
obj-y += ddr.o
|
|
||||||
obj-y += law.o
|
|
||||||
obj-y += tlb.o
|
|
|
@ -1,135 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2010 Extreme Engineering Solutions, Inc.
|
|
||||||
* Copyright 2007-2008 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <i2c.h>
|
|
||||||
|
|
||||||
#include <fsl_ddr_sdram.h>
|
|
||||||
#include <fsl_ddr_dimm_params.h>
|
|
||||||
|
|
||||||
void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address)
|
|
||||||
{
|
|
||||||
i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
|
|
||||||
sizeof(ddr3_spd_eeprom_t));
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* There are traditionally three board-specific SDRAM timing parameters
|
|
||||||
* which must be calculated based on the particular PCB artwork. These are:
|
|
||||||
* 1.) CPO (Read Capture Delay)
|
|
||||||
* - TIMING_CFG_2 register
|
|
||||||
* Source: Calculation based on board trace lengths and
|
|
||||||
* chip-specific internal delays.
|
|
||||||
* 2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
|
|
||||||
* - DDR_SDRAM_CLK_CNTL register
|
|
||||||
* Source: Signal Integrity Simulations
|
|
||||||
* 3.) 2T Timing on Addr/Ctl
|
|
||||||
* - TIMING_CFG_2 register
|
|
||||||
* Source: Signal Integrity Simulations
|
|
||||||
* Usually only needed with heavy load/very high speed (>DDR2-800)
|
|
||||||
*
|
|
||||||
* ====== XPedite550x DDR3-800 read delay calculations ======
|
|
||||||
*
|
|
||||||
* The P2020 processor provides an autoleveling option. Setting CPO to
|
|
||||||
* 0x1f enables this auto configuration.
|
|
||||||
*/
|
|
||||||
|
|
||||||
typedef struct {
|
|
||||||
unsigned short datarate_mhz_low;
|
|
||||||
unsigned short datarate_mhz_high;
|
|
||||||
unsigned char clk_adjust;
|
|
||||||
unsigned char cpo;
|
|
||||||
} board_specific_parameters_t;
|
|
||||||
|
|
||||||
const board_specific_parameters_t board_specific_parameters[][20] = {
|
|
||||||
{
|
|
||||||
/* Controller 0 */
|
|
||||||
{
|
|
||||||
/* DDR3-600/667 */
|
|
||||||
.datarate_mhz_low = 500,
|
|
||||||
.datarate_mhz_high = 750,
|
|
||||||
.clk_adjust = 5,
|
|
||||||
.cpo = 31,
|
|
||||||
},
|
|
||||||
{
|
|
||||||
/* DDR3-800 */
|
|
||||||
.datarate_mhz_low = 750,
|
|
||||||
.datarate_mhz_high = 850,
|
|
||||||
.clk_adjust = 5,
|
|
||||||
.cpo = 31,
|
|
||||||
},
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
void fsl_ddr_board_options(memctl_options_t *popts,
|
|
||||||
dimm_params_t *pdimm,
|
|
||||||
unsigned int ctrl_num)
|
|
||||||
{
|
|
||||||
const board_specific_parameters_t *pbsp =
|
|
||||||
&(board_specific_parameters[ctrl_num][0]);
|
|
||||||
u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
|
|
||||||
sizeof(board_specific_parameters[0][0]);
|
|
||||||
u32 i;
|
|
||||||
ulong ddr_freq;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
|
|
||||||
* that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
|
|
||||||
* there are two dimms in the controller, set odt_rd_cfg to 3 and
|
|
||||||
* odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
|
|
||||||
*/
|
|
||||||
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
|
|
||||||
if (i&1) { /* odd CS */
|
|
||||||
popts->cs_local_opts[i].odt_rd_cfg = 0;
|
|
||||||
popts->cs_local_opts[i].odt_wr_cfg = 0;
|
|
||||||
} else { /* even CS */
|
|
||||||
if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
|
|
||||||
popts->cs_local_opts[i].odt_rd_cfg = 0;
|
|
||||||
popts->cs_local_opts[i].odt_wr_cfg = 4;
|
|
||||||
} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
|
|
||||||
popts->cs_local_opts[i].odt_rd_cfg = 3;
|
|
||||||
popts->cs_local_opts[i].odt_wr_cfg = 3;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
|
|
||||||
* freqency and n_banks specified in board_specific_parameters table.
|
|
||||||
*/
|
|
||||||
ddr_freq = get_ddr_freq(0) / 1000000;
|
|
||||||
|
|
||||||
for (i = 0; i < num_params; i++) {
|
|
||||||
if (ddr_freq >= pbsp->datarate_mhz_low &&
|
|
||||||
ddr_freq <= pbsp->datarate_mhz_high) {
|
|
||||||
popts->clk_adjust = pbsp->clk_adjust;
|
|
||||||
popts->cpo_override = pbsp->cpo;
|
|
||||||
popts->twot_en = 0;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
pbsp++;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (i == num_params) {
|
|
||||||
printf("Warning: board specific timing not found "
|
|
||||||
"for data rate %lu MT/s!\n", ddr_freq);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Factors to consider for half-strength driver enable:
|
|
||||||
* - number of DIMMs installed
|
|
||||||
*/
|
|
||||||
popts->half_strength_driver_enable = 0;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Enable on-die termination.
|
|
||||||
* From the Micron Technical Node TN-41-04, RTT_Nom should typically
|
|
||||||
* be 30 to 40 ohms, while RTT_WR should be 120 ohms. Setting RTT_WR
|
|
||||||
* is handled in the Freescale DDR3 driver. Set RTT_Nom here.
|
|
||||||
*/
|
|
||||||
popts->rtt_override = 1;
|
|
||||||
popts->rtt_override_value = 3;
|
|
||||||
}
|
|
|
@ -1,25 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2010 Extreme Engineering Solutions, Inc.
|
|
||||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
|
||||||
*
|
|
||||||
* (C) Copyright 2000
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/fsl_law.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Notes:
|
|
||||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
|
|
||||||
* If flash is 8M at default position (last 8M), no LAW needed.
|
|
||||||
*/
|
|
||||||
|
|
||||||
struct law_entry law_table[] = {
|
|
||||||
SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
|
|
||||||
SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
|
|
||||||
};
|
|
||||||
|
|
||||||
int num_law_entries = ARRAY_SIZE(law_table);
|
|
|
@ -1,81 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2008 Extreme Engineering Solutions, Inc.
|
|
||||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
|
||||||
*
|
|
||||||
* (C) Copyright 2000
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
|
|
||||||
struct fsl_e_tlb_entry tlb_table[] = {
|
|
||||||
/* TLB 0 - for temp stack in cache */
|
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
|
||||||
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
|
||||||
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
|
||||||
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
||||||
|
|
||||||
/* W**G* - NOR flashes */
|
|
||||||
/* This will be changed to *I*G* after relocation to RAM. */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
|
|
||||||
0, 0, BOOKE_PAGESZ_256M, 1),
|
|
||||||
|
|
||||||
/* *I*G* - CCSRBAR */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 1, BOOKE_PAGESZ_1M, 1),
|
|
||||||
|
|
||||||
/* *I*G* - NAND flash */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 2, BOOKE_PAGESZ_1M, 1),
|
|
||||||
|
|
||||||
/* **M** - Boot page for secondary processors */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
|
|
||||||
0, 3, BOOKE_PAGESZ_4K, 1),
|
|
||||||
|
|
||||||
#ifdef CONFIG_PCIE1
|
|
||||||
/* *I*G* - PCIe */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 4, BOOKE_PAGESZ_1G, 1),
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_PCIE2
|
|
||||||
/* *I*G* - PCIe */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 5, BOOKE_PAGESZ_256M, 1),
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_PCIE3
|
|
||||||
/* *I*G* - PCIe */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 6, BOOKE_PAGESZ_256M, 1),
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
|
|
||||||
/* *I*G* - PCIe */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 7, BOOKE_PAGESZ_64M, 1),
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
|
|
@ -1,82 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2010 Extreme Engineering Solutions, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <command.h>
|
|
||||||
#include <init.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
#include <asm/immap_85xx.h>
|
|
||||||
#include <asm/fsl_pci.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <asm/cache.h>
|
|
||||||
#include <linux/libfdt.h>
|
|
||||||
#include <fdt_support.h>
|
|
||||||
#include <pca953x.h>
|
|
||||||
|
|
||||||
extern void ft_board_pci_setup(void *blob, struct bd_info *bd);
|
|
||||||
|
|
||||||
static void flash_cs_fixup(void)
|
|
||||||
{
|
|
||||||
int flash_sel;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Print boot dev and swap flash flash chip selects if booted from 2nd
|
|
||||||
* flash. Swapping chip selects presents user with a common memory
|
|
||||||
* map regardless of which flash was booted from.
|
|
||||||
*/
|
|
||||||
flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
|
|
||||||
CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
|
|
||||||
printf("Flash: Executed from flash%d\n", flash_sel ? 2 : 1);
|
|
||||||
|
|
||||||
if (flash_sel) {
|
|
||||||
set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
|
|
||||||
set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
|
|
||||||
|
|
||||||
set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
|
|
||||||
set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
int board_early_init_r(void)
|
|
||||||
{
|
|
||||||
/* Initialize PCA9557 devices */
|
|
||||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
|
|
||||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
|
|
||||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
|
|
||||||
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Remap NOR flash region to caching-inhibited
|
|
||||||
* so that flash can be erased/programmed properly.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
|
||||||
flush_dcache();
|
|
||||||
invalidate_icache();
|
|
||||||
|
|
||||||
/* Invalidate existing TLB entry for NOR flash */
|
|
||||||
disable_tlb(0);
|
|
||||||
set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
|
|
||||||
(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 0, BOOKE_PAGESZ_256M, 1);
|
|
||||||
|
|
||||||
flash_cs_fixup();
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
|
||||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
|
||||||
{
|
|
||||||
#ifdef CONFIG_PCI
|
|
||||||
ft_board_pci_setup(blob, bd);
|
|
||||||
#endif
|
|
||||||
ft_cpu_setup(blob, bd);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
#endif
|
|
|
@ -1,54 +0,0 @@
|
||||||
CONFIG_PPC=y
|
|
||||||
CONFIG_SYS_TEXT_BASE=0xfff00000
|
|
||||||
CONFIG_ENV_SIZE=0x8000
|
|
||||||
CONFIG_ENV_SECT_SIZE=0x20000
|
|
||||||
CONFIG_MPC86xx=y
|
|
||||||
CONFIG_HIGH_BATS=y
|
|
||||||
CONFIG_TARGET_XPEDITE517X=y
|
|
||||||
CONFIG_FIT=y
|
|
||||||
CONFIG_FIT_VERBOSE=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_BOOTDELAY=3
|
|
||||||
CONFIG_USE_PREBOOT=y
|
|
||||||
CONFIG_BOARD_EARLY_INIT_R=y
|
|
||||||
CONFIG_HUSH_PARSER=y
|
|
||||||
# CONFIG_AUTO_COMPLETE is not set
|
|
||||||
CONFIG_CMD_IMLS=y
|
|
||||||
CONFIG_CMD_ASKENV=y
|
|
||||||
CONFIG_CMD_EEPROM=y
|
|
||||||
CONFIG_CMD_I2C=y
|
|
||||||
CONFIG_CMD_NAND=y
|
|
||||||
CONFIG_CMD_PCI=y
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_CMD_DHCP=y
|
|
||||||
CONFIG_CMD_MII=y
|
|
||||||
CONFIG_CMD_PING=y
|
|
||||||
CONFIG_CMD_SNTP=y
|
|
||||||
CONFIG_CMD_DATE=y
|
|
||||||
CONFIG_CMD_JFFS2=y
|
|
||||||
CONFIG_CMD_IRQ=y
|
|
||||||
CONFIG_ENV_ADDR=0xFFF80000
|
|
||||||
CONFIG_CMD_PCA953X=y
|
|
||||||
CONFIG_DS4510=y
|
|
||||||
# CONFIG_MMC is not set
|
|
||||||
CONFIG_MTD=y
|
|
||||||
CONFIG_MTD_NOR_FLASH=y
|
|
||||||
CONFIG_FLASH_CFI_DRIVER=y
|
|
||||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|
||||||
CONFIG_SYS_FLASH_CFI=y
|
|
||||||
CONFIG_MTD_RAW_NAND=y
|
|
||||||
CONFIG_PHY_ATHEROS=y
|
|
||||||
CONFIG_PHY_BROADCOM=y
|
|
||||||
CONFIG_PHY_DAVICOM=y
|
|
||||||
CONFIG_PHY_LXT=y
|
|
||||||
CONFIG_PHY_MARVELL=y
|
|
||||||
CONFIG_PHY_NATSEMI=y
|
|
||||||
CONFIG_PHY_REALTEK=y
|
|
||||||
CONFIG_PHY_SMSC=y
|
|
||||||
CONFIG_PHY_VITESSE=y
|
|
||||||
CONFIG_MII=y
|
|
||||||
CONFIG_TSEC_ENET=y
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_PANIC_HANG=y
|
|
||||||
CONFIG_OF_LIBFDT=y
|
|
|
@ -1,54 +0,0 @@
|
||||||
CONFIG_PPC=y
|
|
||||||
CONFIG_SYS_TEXT_BASE=0xFFF80000
|
|
||||||
CONFIG_ENV_SIZE=0x8000
|
|
||||||
CONFIG_ENV_SECT_SIZE=0x20000
|
|
||||||
CONFIG_MPC85xx=y
|
|
||||||
# CONFIG_CMD_ERRATA is not set
|
|
||||||
CONFIG_TARGET_XPEDITE520X=y
|
|
||||||
CONFIG_FIT=y
|
|
||||||
CONFIG_FIT_VERBOSE=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_BOOTDELAY=3
|
|
||||||
CONFIG_USE_PREBOOT=y
|
|
||||||
CONFIG_BOARD_EARLY_INIT_R=y
|
|
||||||
# CONFIG_MISC_INIT_R is not set
|
|
||||||
CONFIG_HUSH_PARSER=y
|
|
||||||
CONFIG_CMD_IMLS=y
|
|
||||||
CONFIG_CMD_ASKENV=y
|
|
||||||
CONFIG_CMD_EEPROM=y
|
|
||||||
CONFIG_CMD_I2C=y
|
|
||||||
CONFIG_CMD_NAND=y
|
|
||||||
CONFIG_CMD_PCI=y
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_CMD_DHCP=y
|
|
||||||
CONFIG_CMD_MII=y
|
|
||||||
CONFIG_CMD_PING=y
|
|
||||||
CONFIG_CMD_SNTP=y
|
|
||||||
CONFIG_CMD_DATE=y
|
|
||||||
# CONFIG_CMD_HASH is not set
|
|
||||||
CONFIG_CMD_JFFS2=y
|
|
||||||
# CONFIG_CMD_IRQ is not set
|
|
||||||
CONFIG_ENV_ADDR=0xFFF40000
|
|
||||||
CONFIG_CMD_PCA953X=y
|
|
||||||
# CONFIG_MMC is not set
|
|
||||||
CONFIG_MTD=y
|
|
||||||
CONFIG_MTD_NOR_FLASH=y
|
|
||||||
CONFIG_FLASH_CFI_DRIVER=y
|
|
||||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|
||||||
CONFIG_SYS_FLASH_CFI=y
|
|
||||||
CONFIG_MTD_RAW_NAND=y
|
|
||||||
CONFIG_PHY_ATHEROS=y
|
|
||||||
CONFIG_PHY_BROADCOM=y
|
|
||||||
CONFIG_PHY_DAVICOM=y
|
|
||||||
CONFIG_PHY_LXT=y
|
|
||||||
CONFIG_PHY_MARVELL=y
|
|
||||||
CONFIG_PHY_NATSEMI=y
|
|
||||||
CONFIG_PHY_REALTEK=y
|
|
||||||
CONFIG_PHY_SMSC=y
|
|
||||||
CONFIG_PHY_VITESSE=y
|
|
||||||
CONFIG_MII=y
|
|
||||||
CONFIG_TSEC_ENET=y
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_PANIC_HANG=y
|
|
||||||
CONFIG_OF_LIBFDT=y
|
|
|
@ -1,57 +0,0 @@
|
||||||
CONFIG_PPC=y
|
|
||||||
CONFIG_SYS_TEXT_BASE=0xFFF80000
|
|
||||||
CONFIG_ENV_SIZE=0x8000
|
|
||||||
CONFIG_ENV_SECT_SIZE=0x20000
|
|
||||||
CONFIG_MPC85xx=y
|
|
||||||
# CONFIG_CMD_ERRATA is not set
|
|
||||||
CONFIG_TARGET_XPEDITE537X=y
|
|
||||||
CONFIG_FIT=y
|
|
||||||
CONFIG_FIT_VERBOSE=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_BOOTDELAY=3
|
|
||||||
CONFIG_USE_PREBOOT=y
|
|
||||||
CONFIG_BOARD_EARLY_INIT_R=y
|
|
||||||
# CONFIG_MISC_INIT_R is not set
|
|
||||||
CONFIG_HUSH_PARSER=y
|
|
||||||
CONFIG_CMD_REGINFO=y
|
|
||||||
CONFIG_CMD_IMLS=y
|
|
||||||
CONFIG_CMD_ASKENV=y
|
|
||||||
CONFIG_CMD_EEPROM=y
|
|
||||||
CONFIG_CMD_I2C=y
|
|
||||||
CONFIG_CMD_PCI=y
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_CMD_DHCP=y
|
|
||||||
CONFIG_CMD_MII=y
|
|
||||||
CONFIG_CMD_PING=y
|
|
||||||
CONFIG_CMD_SNTP=y
|
|
||||||
CONFIG_CMD_DATE=y
|
|
||||||
CONFIG_MP=y
|
|
||||||
# CONFIG_CMD_HASH is not set
|
|
||||||
CONFIG_CMD_JFFS2=y
|
|
||||||
# CONFIG_CMD_IRQ is not set
|
|
||||||
CONFIG_ENV_ADDR=0xFFF40000
|
|
||||||
CONFIG_SYS_FSL_DDR2=y
|
|
||||||
CONFIG_CMD_PCA953X=y
|
|
||||||
CONFIG_DS4510=y
|
|
||||||
# CONFIG_MMC is not set
|
|
||||||
CONFIG_MTD=y
|
|
||||||
CONFIG_MTD_NOR_FLASH=y
|
|
||||||
CONFIG_FLASH_CFI_DRIVER=y
|
|
||||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|
||||||
CONFIG_SYS_FLASH_CFI=y
|
|
||||||
CONFIG_MTD_RAW_NAND=y
|
|
||||||
CONFIG_PHY_ATHEROS=y
|
|
||||||
CONFIG_PHY_BROADCOM=y
|
|
||||||
CONFIG_PHY_DAVICOM=y
|
|
||||||
CONFIG_PHY_LXT=y
|
|
||||||
CONFIG_PHY_MARVELL=y
|
|
||||||
CONFIG_PHY_NATSEMI=y
|
|
||||||
CONFIG_PHY_REALTEK=y
|
|
||||||
CONFIG_PHY_SMSC=y
|
|
||||||
CONFIG_PHY_VITESSE=y
|
|
||||||
CONFIG_MII=y
|
|
||||||
CONFIG_TSEC_ENET=y
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_PANIC_HANG=y
|
|
||||||
CONFIG_OF_LIBFDT=y
|
|
|
@ -1,57 +0,0 @@
|
||||||
CONFIG_PPC=y
|
|
||||||
CONFIG_SYS_TEXT_BASE=0xFFF80000
|
|
||||||
CONFIG_ENV_SIZE=0x8000
|
|
||||||
CONFIG_ENV_SECT_SIZE=0x20000
|
|
||||||
CONFIG_MPC85xx=y
|
|
||||||
# CONFIG_CMD_ERRATA is not set
|
|
||||||
CONFIG_TARGET_XPEDITE550X=y
|
|
||||||
CONFIG_FIT=y
|
|
||||||
CONFIG_FIT_VERBOSE=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_BOOTDELAY=3
|
|
||||||
CONFIG_USE_PREBOOT=y
|
|
||||||
CONFIG_BOARD_EARLY_INIT_R=y
|
|
||||||
# CONFIG_MISC_INIT_R is not set
|
|
||||||
CONFIG_HUSH_PARSER=y
|
|
||||||
CONFIG_CMD_IMLS=y
|
|
||||||
CONFIG_CMD_ASKENV=y
|
|
||||||
CONFIG_CMD_I2C=y
|
|
||||||
CONFIG_CMD_PCI=y
|
|
||||||
CONFIG_CMD_USB=y
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_CMD_DHCP=y
|
|
||||||
CONFIG_CMD_MII=y
|
|
||||||
CONFIG_CMD_PING=y
|
|
||||||
CONFIG_CMD_SNTP=y
|
|
||||||
CONFIG_CMD_DATE=y
|
|
||||||
CONFIG_MP=y
|
|
||||||
# CONFIG_CMD_HASH is not set
|
|
||||||
CONFIG_CMD_JFFS2=y
|
|
||||||
# CONFIG_CMD_IRQ is not set
|
|
||||||
CONFIG_ENV_IS_IN_FLASH=y
|
|
||||||
CONFIG_ENV_ADDR=0xFFF40000
|
|
||||||
CONFIG_CMD_PCA953X=y
|
|
||||||
# CONFIG_MMC is not set
|
|
||||||
CONFIG_MTD=y
|
|
||||||
CONFIG_MTD_NOR_FLASH=y
|
|
||||||
CONFIG_FLASH_CFI_DRIVER=y
|
|
||||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|
||||||
CONFIG_SYS_FLASH_CFI=y
|
|
||||||
CONFIG_MTD_RAW_NAND=y
|
|
||||||
CONFIG_PHY_ATHEROS=y
|
|
||||||
CONFIG_PHY_BROADCOM=y
|
|
||||||
CONFIG_PHY_DAVICOM=y
|
|
||||||
CONFIG_PHY_LXT=y
|
|
||||||
CONFIG_PHY_MARVELL=y
|
|
||||||
CONFIG_PHY_NATSEMI=y
|
|
||||||
CONFIG_PHY_REALTEK=y
|
|
||||||
CONFIG_PHY_SMSC=y
|
|
||||||
CONFIG_PHY_VITESSE=y
|
|
||||||
CONFIG_MII=y
|
|
||||||
CONFIG_TSEC_ENET=y
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_USB=y
|
|
||||||
CONFIG_USB_STORAGE=y
|
|
||||||
CONFIG_PANIC_HANG=y
|
|
||||||
CONFIG_OF_LIBFDT=y
|
|
|
@ -41,7 +41,6 @@ config SYS_NUM_DDR_CTLRS
|
||||||
ARCH_T4240
|
ARCH_T4240
|
||||||
default 2 if ARCH_B4860 || \
|
default 2 if ARCH_B4860 || \
|
||||||
ARCH_BSC9132 || \
|
ARCH_BSC9132 || \
|
||||||
ARCH_MPC8572 || \
|
|
||||||
ARCH_MPC8641 || \
|
ARCH_MPC8641 || \
|
||||||
ARCH_P4080 || \
|
ARCH_P4080 || \
|
||||||
ARCH_P5040 || \
|
ARCH_P5040 || \
|
||||||
|
|
2
env/Kconfig
vendored
2
env/Kconfig
vendored
|
@ -85,7 +85,7 @@ config ENV_IS_IN_FLASH
|
||||||
default y if M548x || M547x || M5282
|
default y if M548x || M547x || M5282
|
||||||
default y if MCF532x || MCF52x2
|
default y if MCF532x || MCF52x2
|
||||||
default y if MPC86xx || MPC83xx
|
default y if MPC86xx || MPC83xx
|
||||||
default y if ARCH_MPC8572 || ARCH_MPC8548 || ARCH_MPC8641
|
default y if ARCH_MPC8548 || ARCH_MPC8641
|
||||||
default y if SH && !CPU_SH4
|
default y if SH && !CPU_SH4
|
||||||
help
|
help
|
||||||
Define this if you have a flash device which you want to use for the
|
Define this if you have a flash device which you want to use for the
|
||||||
|
|
|
@ -1,646 +0,0 @@
|
||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
||||||
/*
|
|
||||||
* Copyright 2009 Extreme Engineering Solutions, Inc.
|
|
||||||
* Copyright 2007-2008 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* xpedite517x board configuration file
|
|
||||||
*/
|
|
||||||
#ifndef __CONFIG_H
|
|
||||||
#define __CONFIG_H
|
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_BOARD_NAME "XPedite5170"
|
|
||||||
#define CONFIG_SYS_FORM_3U_VPX 1
|
|
||||||
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
|
|
||||||
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
|
|
||||||
#define CONFIG_ALTIVEC 1
|
|
||||||
|
|
||||||
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
|
|
||||||
#define CONFIG_PCIE1 1 /* PCIE controller 1 */
|
|
||||||
#define CONFIG_PCIE2 1 /* PCIE controller 2 */
|
|
||||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
|
|
||||||
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
|
|
||||||
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* DDR config
|
|
||||||
*/
|
|
||||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
|
|
||||||
#define CONFIG_DDR_SPD
|
|
||||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
|
|
||||||
#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
|
|
||||||
#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
|
|
||||||
#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
|
|
||||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
|
||||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
|
|
||||||
#define CONFIG_DDR_ECC
|
|
||||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
|
|
||||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
|
||||||
#define CONFIG_VERY_BIG_RAM
|
|
||||||
#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* virtual address to be used for temporary mappings. There
|
|
||||||
* should be 128k free at this VA.
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_SCRATCH_VA 0xe0000000
|
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
|
||||||
#include <linux/stringify.h>
|
|
||||||
extern unsigned long get_board_sys_clk(unsigned long dummy);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* L2CR setup
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_L2
|
|
||||||
#define L2_INIT 0
|
|
||||||
#define L2_ENABLE (L2CR_L2E)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Base addresses -- Note these are effective addresses where the
|
|
||||||
* actual resources get mapped (not physical addresses)
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
|
|
||||||
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
|
|
||||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
|
|
||||||
#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
|
|
||||||
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Diagnostics
|
|
||||||
*/
|
|
||||||
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
|
|
||||||
CONFIG_SYS_POST_I2C)
|
|
||||||
/* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
|
|
||||||
#define I2C_ADDR_IGNORE_LIST {0x50}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Memory map
|
|
||||||
* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
|
|
||||||
* 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
|
|
||||||
* 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
|
|
||||||
* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
|
|
||||||
* 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
|
|
||||||
* 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
|
|
||||||
* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
|
|
||||||
* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
|
|
||||||
* 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
|
|
||||||
* 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* NAND flash configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_NAND_BASE 0xef800000
|
|
||||||
#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
|
|
||||||
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
|
|
||||||
#define CONFIG_SYS_MAX_NAND_DEVICE 2
|
|
||||||
#define CONFIG_NAND_ACTL
|
|
||||||
#define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
|
|
||||||
#define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
|
|
||||||
#define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
|
|
||||||
#define CONFIG_SYS_NAND_ACTL_DELAY 25
|
|
||||||
#define CONFIG_JFFS2_NAND
|
|
||||||
|
|
||||||
/*
|
|
||||||
* NOR flash configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_FLASH_BASE 0xf8000000
|
|
||||||
#define CONFIG_SYS_FLASH_BASE2 0xf0000000
|
|
||||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
|
||||||
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
|
|
||||||
{0xf7f00000, 0xc0000} }
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Chip select configuration
|
|
||||||
*/
|
|
||||||
/* NOR Flash 0 on CS0 */
|
|
||||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
|
|
||||||
BR_PS_16 |\
|
|
||||||
BR_V)
|
|
||||||
#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
|
|
||||||
OR_GPCM_CSNT |\
|
|
||||||
OR_GPCM_XACS |\
|
|
||||||
OR_GPCM_ACS_DIV2 |\
|
|
||||||
OR_GPCM_SCY_8 |\
|
|
||||||
OR_GPCM_TRLX |\
|
|
||||||
OR_GPCM_EHTR |\
|
|
||||||
OR_GPCM_EAD)
|
|
||||||
|
|
||||||
/* NOR Flash 1 on CS1 */
|
|
||||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
|
|
||||||
BR_PS_16 |\
|
|
||||||
BR_V)
|
|
||||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
|
|
||||||
|
|
||||||
/* NAND flash on CS2 */
|
|
||||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
|
|
||||||
BR_PS_8 |\
|
|
||||||
BR_V)
|
|
||||||
#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
|
|
||||||
OR_GPCM_BCTLD |\
|
|
||||||
OR_GPCM_CSNT |\
|
|
||||||
OR_GPCM_ACS_DIV4 |\
|
|
||||||
OR_GPCM_SCY_4 |\
|
|
||||||
OR_GPCM_TRLX |\
|
|
||||||
OR_GPCM_EHTR)
|
|
||||||
|
|
||||||
/* Optional NAND flash on CS3 */
|
|
||||||
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
|
|
||||||
BR_PS_8 |\
|
|
||||||
BR_V)
|
|
||||||
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Use L1 as initial stack
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
|
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
|
|
||||||
|
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
|
|
||||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Serial Port
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_NS16550_SERIAL
|
|
||||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
|
||||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
|
||||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
|
||||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
|
||||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
|
||||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* I2C
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_I2C
|
|
||||||
#define CONFIG_SYS_I2C_FSL
|
|
||||||
#define CONFIG_SYS_FSL_I2C_SPEED 100000
|
|
||||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
|
||||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
|
||||||
#define CONFIG_SYS_FSL_I2C2_SPEED 100000
|
|
||||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
|
||||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
|
||||||
|
|
||||||
/* PEX8518 slave I2C interface */
|
|
||||||
#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
|
|
||||||
|
|
||||||
/* I2C DS1631 temperature sensor */
|
|
||||||
#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
|
|
||||||
|
|
||||||
/* I2C EEPROM - AT24C128B */
|
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
|
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
|
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
|
|
||||||
|
|
||||||
/* I2C RTC */
|
|
||||||
#define CONFIG_RTC_M41T11 1
|
|
||||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
|
||||||
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
|
|
||||||
|
|
||||||
/* GPIO */
|
|
||||||
#define CONFIG_PCA953X
|
|
||||||
#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
|
|
||||||
#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
|
|
||||||
#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
|
|
||||||
#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
|
|
||||||
#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
|
|
||||||
#define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
|
|
||||||
|
|
||||||
/*
|
|
||||||
* PU = pulled high, PD = pulled low
|
|
||||||
* I = input, O = output, IO = input/output
|
|
||||||
*/
|
|
||||||
/* PCA9557 @ 0x18*/
|
|
||||||
#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
|
|
||||||
#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
|
|
||||||
#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
|
|
||||||
#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
|
|
||||||
#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
|
|
||||||
#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
|
|
||||||
|
|
||||||
/* PCA9557 @ 0x1c*/
|
|
||||||
#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
|
|
||||||
#define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
|
|
||||||
#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
|
|
||||||
#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
|
|
||||||
#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
|
|
||||||
#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
|
|
||||||
#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
|
|
||||||
#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
|
|
||||||
|
|
||||||
/* PCA9557 @ 0x1e*/
|
|
||||||
#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
|
|
||||||
#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
|
|
||||||
#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
|
|
||||||
#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
|
|
||||||
#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
|
|
||||||
#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
|
|
||||||
#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
|
|
||||||
|
|
||||||
/* PCA9557 @ 0x1f */
|
|
||||||
#define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
|
|
||||||
#define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
|
|
||||||
#define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
|
|
||||||
#define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* General PCI
|
|
||||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
|
||||||
*/
|
|
||||||
/* PCIE1 - PEX8518 */
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
|
|
||||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
|
||||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
|
|
||||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
|
|
||||||
|
|
||||||
/* PCIE2 - VPX P1 */
|
|
||||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
|
|
||||||
#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
|
|
||||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
|
|
||||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
|
||||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
|
|
||||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Networking options
|
|
||||||
*/
|
|
||||||
#define CONFIG_ETHPRIME "eTSEC1"
|
|
||||||
|
|
||||||
#define CONFIG_TSEC1 1
|
|
||||||
#define CONFIG_TSEC1_NAME "eTSEC1"
|
|
||||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
||||||
#define TSEC1_PHY_ADDR 1
|
|
||||||
#define TSEC1_PHYIDX 0
|
|
||||||
#define CONFIG_HAS_ETH0
|
|
||||||
|
|
||||||
#define CONFIG_TSEC2 1
|
|
||||||
#define CONFIG_TSEC2_NAME "eTSEC2"
|
|
||||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
||||||
#define TSEC2_PHY_ADDR 2
|
|
||||||
#define TSEC2_PHYIDX 0
|
|
||||||
#define CONFIG_HAS_ETH1
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BAT mappings
|
|
||||||
*/
|
|
||||||
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
|
|
||||||
#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
|
|
||||||
BATL_PP_RW |\
|
|
||||||
BATL_CACHEINHIBIT |\
|
|
||||||
BATL_GUARDEDSTORAGE)
|
|
||||||
#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
|
|
||||||
BATU_BL_1M |\
|
|
||||||
BATU_VS |\
|
|
||||||
BATU_VP)
|
|
||||||
#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
|
|
||||||
BATL_PP_RW |\
|
|
||||||
BATL_CACHEINHIBIT)
|
|
||||||
#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BAT0 2G Cacheable, non-guarded
|
|
||||||
* 0x0000_0000 2G DDR
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
|
|
||||||
#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
|
|
||||||
#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
|
|
||||||
#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BAT1 1G Cache-inhibited, guarded
|
|
||||||
* 0x8000_0000 1G PCI-Express 1 Memory
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
|
|
||||||
BATL_PP_RW |\
|
|
||||||
BATL_CACHEINHIBIT |\
|
|
||||||
BATL_GUARDEDSTORAGE)
|
|
||||||
#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
|
|
||||||
BATU_BL_1G |\
|
|
||||||
BATU_VS |\
|
|
||||||
BATU_VP)
|
|
||||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
|
|
||||||
BATL_PP_RW |\
|
|
||||||
BATL_CACHEINHIBIT)
|
|
||||||
#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BAT2 512M Cache-inhibited, guarded
|
|
||||||
* 0xc000_0000 512M PCI-Express 2 Memory
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
|
|
||||||
BATL_PP_RW |\
|
|
||||||
BATL_CACHEINHIBIT |\
|
|
||||||
BATL_GUARDEDSTORAGE)
|
|
||||||
#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
|
|
||||||
BATU_BL_512M |\
|
|
||||||
BATU_VS |\
|
|
||||||
BATU_VP)
|
|
||||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
|
|
||||||
BATL_PP_RW |\
|
|
||||||
BATL_CACHEINHIBIT)
|
|
||||||
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BAT3 1M Cache-inhibited, guarded
|
|
||||||
* 0xe000_0000 1M CCSR
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
|
|
||||||
BATL_PP_RW |\
|
|
||||||
BATL_CACHEINHIBIT |\
|
|
||||||
BATL_GUARDEDSTORAGE)
|
|
||||||
#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
|
|
||||||
BATU_BL_1M |\
|
|
||||||
BATU_VS |\
|
|
||||||
BATU_VP)
|
|
||||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
|
|
||||||
BATL_PP_RW |\
|
|
||||||
BATL_CACHEINHIBIT)
|
|
||||||
#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BAT4 32M Cache-inhibited, guarded
|
|
||||||
* 0xe200_0000 16M PCI-Express 1 I/O
|
|
||||||
* 0xe300_0000 16M PCI-Express 2 I/0
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
|
|
||||||
BATL_PP_RW |\
|
|
||||||
BATL_CACHEINHIBIT |\
|
|
||||||
BATL_GUARDEDSTORAGE)
|
|
||||||
#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
|
|
||||||
BATU_BL_32M |\
|
|
||||||
BATU_VS |\
|
|
||||||
BATU_VP)
|
|
||||||
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
|
|
||||||
BATL_PP_RW |\
|
|
||||||
BATL_CACHEINHIBIT)
|
|
||||||
#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BAT5 128K Cacheable, non-guarded
|
|
||||||
* 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
|
|
||||||
BATL_PP_RW |\
|
|
||||||
BATL_MEMCOHERENCE)
|
|
||||||
#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
|
|
||||||
BATU_BL_128K |\
|
|
||||||
BATU_VS |\
|
|
||||||
BATU_VP)
|
|
||||||
#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
|
|
||||||
#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BAT6 256M Cache-inhibited, guarded
|
|
||||||
* 0xf000_0000 256M FLASH
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
|
|
||||||
BATL_PP_RW |\
|
|
||||||
BATL_CACHEINHIBIT |\
|
|
||||||
BATL_GUARDEDSTORAGE)
|
|
||||||
#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
|
|
||||||
BATU_BL_256M |\
|
|
||||||
BATU_VS |\
|
|
||||||
BATU_VP)
|
|
||||||
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
|
|
||||||
BATL_PP_RW |\
|
|
||||||
BATL_MEMCOHERENCE)
|
|
||||||
#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
|
|
||||||
|
|
||||||
/* Map the last 1M of flash where we're running from reset */
|
|
||||||
#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
|
|
||||||
BATL_PP_RW |\
|
|
||||||
BATL_CACHEINHIBIT |\
|
|
||||||
BATL_GUARDEDSTORAGE)
|
|
||||||
#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
|
|
||||||
BATU_BL_1M |\
|
|
||||||
BATU_VS |\
|
|
||||||
BATU_VP)
|
|
||||||
#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
|
|
||||||
BATL_PP_RW |\
|
|
||||||
BATL_MEMCOHERENCE)
|
|
||||||
#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BAT7 64M Cache-inhibited, guarded
|
|
||||||
* 0xe800_0000 64K NAND FLASH
|
|
||||||
* 0xe804_0000 128K DUART Registers
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
|
|
||||||
BATL_PP_RW |\
|
|
||||||
BATL_CACHEINHIBIT |\
|
|
||||||
BATL_GUARDEDSTORAGE)
|
|
||||||
#define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
|
|
||||||
BATU_BL_512K |\
|
|
||||||
BATU_VS |\
|
|
||||||
BATU_VP)
|
|
||||||
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
|
|
||||||
BATL_PP_RW |\
|
|
||||||
BATL_CACHEINHIBIT)
|
|
||||||
#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
|
||||||
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
|
|
||||||
#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data
|
|
||||||
* have to be in the first 16 MB of memory, since this is
|
|
||||||
* the maximum mapped by the Linux kernel during initialization.
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
|
|
||||||
#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment Configuration
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Flash memory map:
|
|
||||||
* fffc0000 - ffffffff Pri FDT (256KB)
|
|
||||||
* fff80000 - fffbffff Pri U-Boot Environment (256 KB)
|
|
||||||
* fff00000 - fff7ffff Pri U-Boot (512 KB)
|
|
||||||
* fef00000 - ffefffff Pri OS image (16MB)
|
|
||||||
* f8000000 - feefffff Pri OS Use/Filesystem (111MB)
|
|
||||||
*
|
|
||||||
* f7fc0000 - f7ffffff Sec FDT (256KB)
|
|
||||||
* f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
|
|
||||||
* f7f00000 - f7f7ffff Sec U-Boot (512 KB)
|
|
||||||
* f6f00000 - f7efffff Sec OS image (16MB)
|
|
||||||
* f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
|
|
||||||
*/
|
|
||||||
#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
|
|
||||||
#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
|
|
||||||
#define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
|
|
||||||
#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
|
|
||||||
#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
|
|
||||||
#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
|
|
||||||
|
|
||||||
#define CONFIG_PROG_UBOOT1 \
|
|
||||||
"$download_cmd $loadaddr $ubootfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
|
|
||||||
"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
|
|
||||||
"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
|
|
||||||
"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
|
|
||||||
"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_UBOOT2 \
|
|
||||||
"$download_cmd $loadaddr $ubootfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
|
|
||||||
"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
|
|
||||||
"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
|
|
||||||
"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
|
|
||||||
"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_BOOT_OS_NET \
|
|
||||||
"$download_cmd $osaddr $osfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"if test -n $fdtaddr; then " \
|
|
||||||
"$download_cmd $fdtaddr $fdtfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"bootm $osaddr - $fdtaddr; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT DOWNLOAD FAILED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"bootm $osaddr; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_OS1 \
|
|
||||||
"$download_cmd $osaddr $osfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
|
|
||||||
"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
|
|
||||||
"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo OS PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_OS2 \
|
|
||||||
"$download_cmd $osaddr $osfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
|
|
||||||
"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
|
|
||||||
"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo OS PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_FDT1 \
|
|
||||||
"$download_cmd $fdtaddr $fdtfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
|
|
||||||
"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
|
|
||||||
"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo FDT PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_FDT2 \
|
|
||||||
"$download_cmd $fdtaddr $fdtfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
|
|
||||||
"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
|
|
||||||
"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo FDT PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
||||||
"autoload=yes\0" \
|
|
||||||
"download_cmd=tftp\0" \
|
|
||||||
"console_args=console=ttyS0,115200\0" \
|
|
||||||
"root_args=root=/dev/nfs rw\0" \
|
|
||||||
"misc_args=ip=on\0" \
|
|
||||||
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
|
|
||||||
"bootfile=/home/user/file\0" \
|
|
||||||
"osfile=/home/user/board.uImage\0" \
|
|
||||||
"fdtfile=/home/user/board.dtb\0" \
|
|
||||||
"ubootfile=/home/user/u-boot.bin\0" \
|
|
||||||
"fdtaddr=0x1e00000\0" \
|
|
||||||
"osaddr=0x1000000\0" \
|
|
||||||
"loadaddr=0x1000000\0" \
|
|
||||||
"prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
|
|
||||||
"prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
|
|
||||||
"prog_os1="CONFIG_PROG_OS1"\0" \
|
|
||||||
"prog_os2="CONFIG_PROG_OS2"\0" \
|
|
||||||
"prog_fdt1="CONFIG_PROG_FDT1"\0" \
|
|
||||||
"prog_fdt2="CONFIG_PROG_FDT2"\0" \
|
|
||||||
"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
|
|
||||||
"bootcmd_flash1=run set_bootargs; " \
|
|
||||||
"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
|
|
||||||
"bootcmd_flash2=run set_bootargs; " \
|
|
||||||
"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
|
|
||||||
"bootcmd=run bootcmd_flash1\0"
|
|
||||||
#endif /* __CONFIG_H */
|
|
|
@ -1,445 +0,0 @@
|
||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
||||||
/*
|
|
||||||
* Copyright 2008 Extreme Engineering Solutions, Inc.
|
|
||||||
* Copyright 2004-2008 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* xpedite520x board configuration file
|
|
||||||
*/
|
|
||||||
#ifndef __CONFIG_H
|
|
||||||
#define __CONFIG_H
|
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_BOARD_NAME "XPedite5200"
|
|
||||||
#define CONFIG_SYS_FORM_PMC_XMC 1
|
|
||||||
|
|
||||||
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
|
|
||||||
#define CONFIG_PCI1 1 /* PCI controller 1 */
|
|
||||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
|
|
||||||
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
|
|
||||||
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* DDR config
|
|
||||||
*/
|
|
||||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
|
|
||||||
#define CONFIG_DDR_SPD
|
|
||||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
|
|
||||||
#define SPD_EEPROM_ADDRESS 0x54
|
|
||||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
|
||||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
|
|
||||||
#define CONFIG_DDR_ECC
|
|
||||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
|
|
||||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
|
||||||
#define CONFIG_VERY_BIG_RAM
|
|
||||||
|
|
||||||
#define CONFIG_SYS_CLK_FREQ 66666666
|
|
||||||
|
|
||||||
/*
|
|
||||||
* These can be toggled for performance analysis, otherwise use default.
|
|
||||||
*/
|
|
||||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
|
||||||
#define CONFIG_BTB /* toggle branch predition */
|
|
||||||
#define CONFIG_ENABLE_36BIT_PHYS 1
|
|
||||||
|
|
||||||
#define CONFIG_SYS_CCSRBAR 0xef000000
|
|
||||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Diagnostics
|
|
||||||
*/
|
|
||||||
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
|
|
||||||
CONFIG_SYS_POST_I2C)
|
|
||||||
#define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
|
|
||||||
CONFIG_SYS_I2C_EEPROM_ADDR, \
|
|
||||||
CONFIG_SYS_I2C_PCA953X_ADDR0, \
|
|
||||||
CONFIG_SYS_I2C_PCA953X_ADDR1, \
|
|
||||||
CONFIG_SYS_I2C_RTC_ADDR}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Memory map
|
|
||||||
* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
|
|
||||||
* 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
|
|
||||||
* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
|
|
||||||
* 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
|
|
||||||
* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
|
|
||||||
* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
|
|
||||||
* 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
|
|
||||||
* 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* NAND flash configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_NAND_BASE 0xef800000
|
|
||||||
#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
|
|
||||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
|
||||||
#define CONFIG_NAND_ACTL
|
|
||||||
#define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
|
|
||||||
#define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
|
|
||||||
#define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
|
|
||||||
#define CONFIG_SYS_NAND_ACTL_DELAY 25
|
|
||||||
|
|
||||||
/*
|
|
||||||
* NOR flash configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_FLASH_BASE 0xfc000000
|
|
||||||
#define CONFIG_SYS_FLASH_BASE2 0xf8000000
|
|
||||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
|
||||||
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
|
|
||||||
{0xfbf40000, 0xc0000} }
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Chip select configuration
|
|
||||||
*/
|
|
||||||
/* NOR Flash 0 on CS0 */
|
|
||||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
|
|
||||||
BR_PS_16 | \
|
|
||||||
BR_V)
|
|
||||||
#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
|
|
||||||
OR_GPCM_ACS_DIV4 | \
|
|
||||||
OR_GPCM_SCY_8)
|
|
||||||
|
|
||||||
/* NOR Flash 1 on CS1 */
|
|
||||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
|
|
||||||
BR_PS_16 | \
|
|
||||||
BR_V)
|
|
||||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
|
|
||||||
|
|
||||||
/* NAND flash on CS2 */
|
|
||||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
|
|
||||||
BR_PS_8 | \
|
|
||||||
BR_V)
|
|
||||||
|
|
||||||
/* NAND flash on CS2 */
|
|
||||||
#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
|
|
||||||
OR_GPCM_BCTLD | \
|
|
||||||
OR_GPCM_CSNT | \
|
|
||||||
OR_GPCM_ACS_DIV4 | \
|
|
||||||
OR_GPCM_SCY_4 | \
|
|
||||||
OR_GPCM_TRLX | \
|
|
||||||
OR_GPCM_EHTR)
|
|
||||||
|
|
||||||
/* NAND flash on CS3 */
|
|
||||||
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
|
|
||||||
BR_PS_8 | \
|
|
||||||
BR_V)
|
|
||||||
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Use L1 as initial stack
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
|
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
|
|
||||||
|
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
|
|
||||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Serial Port
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_NS16550_SERIAL
|
|
||||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
|
||||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
|
||||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
|
||||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
|
||||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
|
||||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* I2C
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_I2C
|
|
||||||
#define CONFIG_SYS_I2C_FSL
|
|
||||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
|
||||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
|
||||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
|
||||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
|
||||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
|
||||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
|
||||||
|
|
||||||
/* I2C EEPROM */
|
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
|
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
|
|
||||||
|
|
||||||
/* I2C RTC */
|
|
||||||
#define CONFIG_RTC_M41T11 1
|
|
||||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
|
||||||
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
|
|
||||||
|
|
||||||
/* GPIO */
|
|
||||||
#define CONFIG_PCA953X
|
|
||||||
#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
|
|
||||||
#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
|
|
||||||
#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
|
|
||||||
|
|
||||||
/* PCA957 @ 0x18 */
|
|
||||||
#define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
|
|
||||||
#define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
|
|
||||||
#define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
|
|
||||||
#define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
|
|
||||||
#define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
|
|
||||||
#define CONFIG_SYS_PCA953X_NVM_WP 0x20
|
|
||||||
#define CONFIG_SYS_PCA953X_MONARCH 0x40
|
|
||||||
#define CONFIG_SYS_PCA953X_EREADY 0x80
|
|
||||||
|
|
||||||
/* PCA957 @ 0x19 */
|
|
||||||
#define CONFIG_SYS_PCA953X_P14_IO0 0x01
|
|
||||||
#define CONFIG_SYS_PCA953X_P14_IO1 0x02
|
|
||||||
#define CONFIG_SYS_PCA953X_P14_IO2 0x04
|
|
||||||
#define CONFIG_SYS_PCA953X_P14_IO3 0x08
|
|
||||||
#define CONFIG_SYS_PCA953X_P14_IO4 0x10
|
|
||||||
#define CONFIG_SYS_PCA953X_P14_IO5 0x20
|
|
||||||
#define CONFIG_SYS_PCA953X_P14_IO6 0x40
|
|
||||||
#define CONFIG_SYS_PCA953X_P14_IO7 0x80
|
|
||||||
|
|
||||||
/* 12-bit ADC used to measure CPU diode */
|
|
||||||
#define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
|
|
||||||
|
|
||||||
/*
|
|
||||||
* General PCI
|
|
||||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
|
|
||||||
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
|
|
||||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
|
|
||||||
#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
|
|
||||||
#define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
|
|
||||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Networking options
|
|
||||||
*/
|
|
||||||
#define CONFIG_ETHPRIME "eTSEC1"
|
|
||||||
|
|
||||||
#define CONFIG_TSEC1 1
|
|
||||||
#define CONFIG_TSEC1_NAME "eTSEC1"
|
|
||||||
#define TSEC1_FLAGS TSEC_GIGABIT
|
|
||||||
#define TSEC1_PHY_ADDR 1
|
|
||||||
#define TSEC1_PHYIDX 0
|
|
||||||
#define CONFIG_HAS_ETH0
|
|
||||||
|
|
||||||
#define CONFIG_TSEC2 1
|
|
||||||
#define CONFIG_TSEC2_NAME "eTSEC2"
|
|
||||||
#define TSEC2_FLAGS TSEC_GIGABIT
|
|
||||||
#define TSEC2_PHY_ADDR 2
|
|
||||||
#define TSEC2_PHYIDX 0
|
|
||||||
#define CONFIG_HAS_ETH1
|
|
||||||
|
|
||||||
#define CONFIG_TSEC3 1
|
|
||||||
#define CONFIG_TSEC3_NAME "eTSEC3"
|
|
||||||
#define TSEC3_FLAGS TSEC_GIGABIT
|
|
||||||
#define TSEC3_PHY_ADDR 3
|
|
||||||
#define TSEC3_PHYIDX 0
|
|
||||||
#define CONFIG_HAS_ETH2
|
|
||||||
|
|
||||||
#define CONFIG_TSEC4 1
|
|
||||||
#define CONFIG_TSEC4_NAME "eTSEC4"
|
|
||||||
#define TSEC4_FLAGS TSEC_GIGABIT
|
|
||||||
#define TSEC4_PHY_ADDR 4
|
|
||||||
#define TSEC4_PHYIDX 0
|
|
||||||
#define CONFIG_HAS_ETH3
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options
|
|
||||||
*/
|
|
||||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
|
||||||
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
|
|
||||||
#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
|
|
||||||
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data
|
|
||||||
* have to be in the first 16 MB of memory, since this is
|
|
||||||
* the maximum mapped by the Linux kernel during initialization.
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
|
|
||||||
#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment Configuration
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Flash memory map:
|
|
||||||
* fff80000 - ffffffff Pri U-Boot (512 KB)
|
|
||||||
* fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
|
|
||||||
* fff00000 - fff3ffff Pri FDT (256KB)
|
|
||||||
* fef00000 - ffefffff Pri OS image (16MB)
|
|
||||||
* fc000000 - feefffff Pri OS Use/Filesystem (47MB)
|
|
||||||
*
|
|
||||||
* fbf80000 - fbffffff Sec U-Boot (512 KB)
|
|
||||||
* fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
|
|
||||||
* fbf00000 - fbf3ffff Sec FDT (256KB)
|
|
||||||
* faf00000 - fbefffff Sec OS image (16MB)
|
|
||||||
* f8000000 - faefffff Sec OS Use/Filesystem (47MB)
|
|
||||||
*/
|
|
||||||
#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
|
|
||||||
#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000)
|
|
||||||
#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
|
|
||||||
#define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000)
|
|
||||||
#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
|
|
||||||
#define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000)
|
|
||||||
|
|
||||||
#define CONFIG_PROG_UBOOT1 \
|
|
||||||
"$download_cmd $loadaddr $ubootfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
|
|
||||||
"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
|
|
||||||
"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
|
|
||||||
"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
|
|
||||||
"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_UBOOT2 \
|
|
||||||
"$download_cmd $loadaddr $ubootfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
|
|
||||||
"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
|
|
||||||
"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
|
|
||||||
"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
|
|
||||||
"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_BOOT_OS_NET \
|
|
||||||
"$download_cmd $osaddr $osfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"if test -n $fdtaddr; then " \
|
|
||||||
"$download_cmd $fdtaddr $fdtfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"bootm $osaddr - $fdtaddr; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT DOWNLOAD FAILED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"bootm $osaddr; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_OS1 \
|
|
||||||
"$download_cmd $osaddr $osfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
|
|
||||||
"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
|
|
||||||
"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo OS PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_OS2 \
|
|
||||||
"$download_cmd $osaddr $osfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
|
|
||||||
"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
|
|
||||||
"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo OS PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_FDT1 \
|
|
||||||
"$download_cmd $fdtaddr $fdtfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
|
|
||||||
"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
|
|
||||||
"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo FDT PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_FDT2 \
|
|
||||||
"$download_cmd $fdtaddr $fdtfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
|
|
||||||
"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
|
|
||||||
"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo FDT PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
||||||
"autoload=yes\0" \
|
|
||||||
"download_cmd=tftp\0" \
|
|
||||||
"console_args=console=ttyS0,115200\0" \
|
|
||||||
"root_args=root=/dev/nfs rw\0" \
|
|
||||||
"misc_args=ip=on\0" \
|
|
||||||
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
|
|
||||||
"bootfile=/home/user/file\0" \
|
|
||||||
"osfile=/home/user/board.uImage\0" \
|
|
||||||
"fdtfile=/home/user/board.dtb\0" \
|
|
||||||
"ubootfile=/home/user/u-boot.bin\0" \
|
|
||||||
"fdtaddr=0x1e00000\0" \
|
|
||||||
"osaddr=0x1000000\0" \
|
|
||||||
"loadaddr=0x1000000\0" \
|
|
||||||
"prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
|
|
||||||
"prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
|
|
||||||
"prog_os1="CONFIG_PROG_OS1"\0" \
|
|
||||||
"prog_os2="CONFIG_PROG_OS2"\0" \
|
|
||||||
"prog_fdt1="CONFIG_PROG_FDT1"\0" \
|
|
||||||
"prog_fdt2="CONFIG_PROG_FDT2"\0" \
|
|
||||||
"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
|
|
||||||
"bootcmd_flash1=run set_bootargs; " \
|
|
||||||
"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
|
|
||||||
"bootcmd_flash2=run set_bootargs; " \
|
|
||||||
"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
|
|
||||||
"bootcmd=run bootcmd_flash1\0"
|
|
||||||
#endif /* __CONFIG_H */
|
|
|
@ -1,496 +0,0 @@
|
||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
||||||
/*
|
|
||||||
* Copyright 2008 Extreme Engineering Solutions, Inc.
|
|
||||||
* Copyright 2007-2008 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* xpedite537x board configuration file
|
|
||||||
*/
|
|
||||||
#ifndef __CONFIG_H
|
|
||||||
#define __CONFIG_H
|
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_BOARD_NAME "XPedite5370"
|
|
||||||
#define CONFIG_SYS_FORM_3U_VPX 1
|
|
||||||
|
|
||||||
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
|
|
||||||
#define CONFIG_PCIE1 1 /* PCIE controller 1 */
|
|
||||||
#define CONFIG_PCIE2 1 /* PCIE controller 2 */
|
|
||||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
|
|
||||||
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
|
|
||||||
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Multicore config
|
|
||||||
*/
|
|
||||||
#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
|
|
||||||
#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* DDR config
|
|
||||||
*/
|
|
||||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
|
|
||||||
#define CONFIG_DDR_SPD
|
|
||||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
|
|
||||||
#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
|
|
||||||
#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
|
|
||||||
#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
|
|
||||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
|
||||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
|
|
||||||
#define CONFIG_DDR_ECC
|
|
||||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
|
|
||||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
|
||||||
#define CONFIG_VERY_BIG_RAM
|
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
|
||||||
#include <linux/stringify.h>
|
|
||||||
extern unsigned long get_board_sys_clk(unsigned long dummy);
|
|
||||||
extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
|
|
||||||
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* These can be toggled for performance analysis, otherwise use default.
|
|
||||||
*/
|
|
||||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
|
||||||
#define CONFIG_BTB /* toggle branch predition */
|
|
||||||
#define CONFIG_ENABLE_36BIT_PHYS 1
|
|
||||||
|
|
||||||
#define CONFIG_SYS_CCSRBAR 0xef000000
|
|
||||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Diagnostics
|
|
||||||
*/
|
|
||||||
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
|
|
||||||
CONFIG_SYS_POST_I2C)
|
|
||||||
/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
|
|
||||||
#define I2C_ADDR_IGNORE_LIST {0x50}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Memory map
|
|
||||||
* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
|
|
||||||
* 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
|
|
||||||
* 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
|
|
||||||
* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
|
|
||||||
* 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
|
|
||||||
* 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
|
|
||||||
* 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
|
|
||||||
* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
|
|
||||||
* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
|
|
||||||
* 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
|
|
||||||
* 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* NAND flash configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_NAND_BASE 0xef800000
|
|
||||||
#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
|
|
||||||
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
|
|
||||||
CONFIG_SYS_NAND_BASE2}
|
|
||||||
#define CONFIG_SYS_MAX_NAND_DEVICE 2
|
|
||||||
#define CONFIG_NAND_FSL_ELBC
|
|
||||||
|
|
||||||
/*
|
|
||||||
* NOR flash configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_FLASH_BASE 0xf8000000
|
|
||||||
#define CONFIG_SYS_FLASH_BASE2 0xf0000000
|
|
||||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
|
||||||
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
|
|
||||||
{0xf7f40000, 0xc0000} }
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Chip select configuration
|
|
||||||
*/
|
|
||||||
/* NOR Flash 0 on CS0 */
|
|
||||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
|
|
||||||
BR_PS_16 | \
|
|
||||||
BR_V)
|
|
||||||
#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
|
|
||||||
OR_GPCM_CSNT | \
|
|
||||||
OR_GPCM_XACS | \
|
|
||||||
OR_GPCM_ACS_DIV2 | \
|
|
||||||
OR_GPCM_SCY_8 | \
|
|
||||||
OR_GPCM_TRLX | \
|
|
||||||
OR_GPCM_EHTR | \
|
|
||||||
OR_GPCM_EAD)
|
|
||||||
|
|
||||||
/* NOR Flash 1 on CS1 */
|
|
||||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
|
|
||||||
BR_PS_16 | \
|
|
||||||
BR_V)
|
|
||||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
|
|
||||||
|
|
||||||
/* NAND flash on CS2 */
|
|
||||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
|
|
||||||
(2<<BR_DECC_SHIFT) | \
|
|
||||||
BR_PS_8 | \
|
|
||||||
BR_MS_FCM | \
|
|
||||||
BR_V)
|
|
||||||
|
|
||||||
/* NAND flash on CS2 */
|
|
||||||
#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
|
|
||||||
OR_FCM_PGS | \
|
|
||||||
OR_FCM_CSCT | \
|
|
||||||
OR_FCM_CST | \
|
|
||||||
OR_FCM_CHT | \
|
|
||||||
OR_FCM_SCY_1 | \
|
|
||||||
OR_FCM_TRLX | \
|
|
||||||
OR_FCM_EHTR)
|
|
||||||
|
|
||||||
/* NAND flash on CS3 */
|
|
||||||
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
|
|
||||||
(2<<BR_DECC_SHIFT) | \
|
|
||||||
BR_PS_8 | \
|
|
||||||
BR_MS_FCM | \
|
|
||||||
BR_V)
|
|
||||||
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Use L1 as initial stack
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
|
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
|
|
||||||
|
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
|
|
||||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Serial Port
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_NS16550_SERIAL
|
|
||||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
|
||||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
|
||||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
|
||||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
|
||||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
|
||||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* I2C
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_I2C
|
|
||||||
#define CONFIG_SYS_I2C_FSL
|
|
||||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
|
||||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
|
||||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
|
||||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
|
||||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
|
||||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
|
||||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
|
||||||
|
|
||||||
/* PEX8518 slave I2C interface */
|
|
||||||
#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
|
|
||||||
|
|
||||||
/* I2C DS1631 temperature sensor */
|
|
||||||
#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
|
|
||||||
|
|
||||||
/* I2C EEPROM - AT24C128B */
|
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
|
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
|
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
|
|
||||||
|
|
||||||
/* I2C RTC */
|
|
||||||
#define CONFIG_RTC_M41T11 1
|
|
||||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
|
||||||
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
|
|
||||||
|
|
||||||
/* GPIO */
|
|
||||||
#define CONFIG_PCA953X
|
|
||||||
#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
|
|
||||||
#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
|
|
||||||
#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
|
|
||||||
#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
|
|
||||||
#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
|
|
||||||
|
|
||||||
/*
|
|
||||||
* PU = pulled high, PD = pulled low
|
|
||||||
* I = input, O = output, IO = input/output
|
|
||||||
*/
|
|
||||||
/* PCA9557 @ 0x18*/
|
|
||||||
#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
|
|
||||||
#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
|
|
||||||
#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
|
|
||||||
#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
|
|
||||||
#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
|
|
||||||
#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
|
|
||||||
#define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */
|
|
||||||
#define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */
|
|
||||||
|
|
||||||
/* PCA9557 @ 0x1c*/
|
|
||||||
#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
|
|
||||||
#define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */
|
|
||||||
#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
|
|
||||||
#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
|
|
||||||
#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
|
|
||||||
#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
|
|
||||||
#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
|
|
||||||
#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
|
|
||||||
|
|
||||||
/* PCA9557 @ 0x1e*/
|
|
||||||
#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
|
|
||||||
#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
|
|
||||||
#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
|
|
||||||
#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
|
|
||||||
#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
|
|
||||||
#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */
|
|
||||||
#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
|
|
||||||
|
|
||||||
/* PCA9557 @ 0x1f */
|
|
||||||
#define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */
|
|
||||||
#define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */
|
|
||||||
#define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */
|
|
||||||
#define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */
|
|
||||||
#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* General PCI
|
|
||||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
|
||||||
*/
|
|
||||||
/* PCIE1 - VPX P1 */
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
|
|
||||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
|
||||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
|
|
||||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
|
|
||||||
|
|
||||||
/* PCIE2 - PEX8518 */
|
|
||||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
|
|
||||||
#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
|
|
||||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
|
|
||||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
|
||||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
|
|
||||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Networking options
|
|
||||||
*/
|
|
||||||
#define CONFIG_TSEC_TBI
|
|
||||||
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
|
|
||||||
#define CONFIG_ETHPRIME "eTSEC2"
|
|
||||||
|
|
||||||
/*
|
|
||||||
* In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
|
|
||||||
* 1000mbps SGMII link
|
|
||||||
*/
|
|
||||||
#define CONFIG_TSEC_TBICR_SETTINGS ( \
|
|
||||||
TBICR_PHY_RESET \
|
|
||||||
| TBICR_FULL_DUPLEX \
|
|
||||||
| TBICR_SPEED1_SET \
|
|
||||||
)
|
|
||||||
|
|
||||||
#define CONFIG_TSEC1 1
|
|
||||||
#define CONFIG_TSEC1_NAME "eTSEC1"
|
|
||||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
||||||
#define TSEC1_PHY_ADDR 1
|
|
||||||
#define TSEC1_PHYIDX 0
|
|
||||||
#define CONFIG_HAS_ETH0
|
|
||||||
|
|
||||||
#define CONFIG_TSEC2 1
|
|
||||||
#define CONFIG_TSEC2_NAME "eTSEC2"
|
|
||||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
||||||
#define TSEC2_PHY_ADDR 2
|
|
||||||
#define TSEC2_PHYIDX 0
|
|
||||||
#define CONFIG_HAS_ETH1
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
|
||||||
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
|
|
||||||
#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data
|
|
||||||
* have to be in the first 16 MB of memory, since this is
|
|
||||||
* the maximum mapped by the Linux kernel during initialization.
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
|
|
||||||
#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment Configuration
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Flash memory map:
|
|
||||||
* fff80000 - ffffffff Pri U-Boot (512 KB)
|
|
||||||
* fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
|
|
||||||
* fff00000 - fff3ffff Pri FDT (256KB)
|
|
||||||
* fef00000 - ffefffff Pri OS image (16MB)
|
|
||||||
* f8000000 - feefffff Pri OS Use/Filesystem (111MB)
|
|
||||||
*
|
|
||||||
* f7f80000 - f7ffffff Sec U-Boot (512 KB)
|
|
||||||
* f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
|
|
||||||
* f7f00000 - f7f3ffff Sec FDT (256KB)
|
|
||||||
* f6f00000 - f7efffff Sec OS image (16MB)
|
|
||||||
* f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
|
|
||||||
*/
|
|
||||||
#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
|
|
||||||
#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
|
|
||||||
#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
|
|
||||||
#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
|
|
||||||
#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
|
|
||||||
#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
|
|
||||||
|
|
||||||
#define CONFIG_PROG_UBOOT1 \
|
|
||||||
"$download_cmd $loadaddr $ubootfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
|
|
||||||
"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
|
|
||||||
"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
|
|
||||||
"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
|
|
||||||
"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_UBOOT2 \
|
|
||||||
"$download_cmd $loadaddr $ubootfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
|
|
||||||
"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
|
|
||||||
"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
|
|
||||||
"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
|
|
||||||
"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_BOOT_OS_NET \
|
|
||||||
"$download_cmd $osaddr $osfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"if test -n $fdtaddr; then " \
|
|
||||||
"$download_cmd $fdtaddr $fdtfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"bootm $osaddr - $fdtaddr; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT DOWNLOAD FAILED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"bootm $osaddr; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_OS1 \
|
|
||||||
"$download_cmd $osaddr $osfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
|
|
||||||
"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
|
|
||||||
"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo OS PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_OS2 \
|
|
||||||
"$download_cmd $osaddr $osfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
|
|
||||||
"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
|
|
||||||
"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo OS PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_FDT1 \
|
|
||||||
"$download_cmd $fdtaddr $fdtfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
|
|
||||||
"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
|
|
||||||
"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo FDT PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_FDT2 \
|
|
||||||
"$download_cmd $fdtaddr $fdtfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
|
|
||||||
"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
|
|
||||||
"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo FDT PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
||||||
"autoload=yes\0" \
|
|
||||||
"download_cmd=tftp\0" \
|
|
||||||
"console_args=console=ttyS0,115200\0" \
|
|
||||||
"root_args=root=/dev/nfs rw\0" \
|
|
||||||
"misc_args=ip=on\0" \
|
|
||||||
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
|
|
||||||
"bootfile=/home/user/file\0" \
|
|
||||||
"osfile=/home/user/board.uImage\0" \
|
|
||||||
"fdtfile=/home/user/board.dtb\0" \
|
|
||||||
"ubootfile=/home/user/u-boot.bin\0" \
|
|
||||||
"fdtaddr=0x1e00000\0" \
|
|
||||||
"osaddr=0x1000000\0" \
|
|
||||||
"loadaddr=0x1000000\0" \
|
|
||||||
"prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
|
|
||||||
"prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
|
|
||||||
"prog_os1="CONFIG_PROG_OS1"\0" \
|
|
||||||
"prog_os2="CONFIG_PROG_OS2"\0" \
|
|
||||||
"prog_fdt1="CONFIG_PROG_FDT1"\0" \
|
|
||||||
"prog_fdt2="CONFIG_PROG_FDT2"\0" \
|
|
||||||
"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
|
|
||||||
"bootcmd_flash1=run set_bootargs; " \
|
|
||||||
"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
|
|
||||||
"bootcmd_flash2=run set_bootargs; " \
|
|
||||||
"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
|
|
||||||
"bootcmd=run bootcmd_flash1\0"
|
|
||||||
#endif /* __CONFIG_H */
|
|
|
@ -1,494 +0,0 @@
|
||||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
||||||
/*
|
|
||||||
* Copyright 2010 Extreme Engineering Solutions, Inc.
|
|
||||||
* Copyright 2007-2008 Freescale Semiconductor, Inc.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* xpedite550x board configuration file
|
|
||||||
*/
|
|
||||||
#ifndef __CONFIG_H
|
|
||||||
#define __CONFIG_H
|
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_BOARD_NAME "XPedite5500"
|
|
||||||
#define CONFIG_SYS_FORM_PMC_XMC 1
|
|
||||||
#define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
|
|
||||||
|
|
||||||
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
|
|
||||||
#define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */
|
|
||||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
|
|
||||||
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
|
|
||||||
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Multicore config
|
|
||||||
*/
|
|
||||||
#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
|
|
||||||
#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* DDR config
|
|
||||||
*/
|
|
||||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
|
|
||||||
#define CONFIG_DDR_SPD
|
|
||||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
|
|
||||||
#define SPD_EEPROM_ADDRESS 0x54
|
|
||||||
#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
|
|
||||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
|
||||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
|
|
||||||
#define CONFIG_DDR_ECC
|
|
||||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
|
|
||||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
|
||||||
#define CONFIG_VERY_BIG_RAM
|
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
|
||||||
#include <linux/stringify.h>
|
|
||||||
extern unsigned long get_board_sys_clk(unsigned long dummy);
|
|
||||||
extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
|
|
||||||
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* These can be toggled for performance analysis, otherwise use default.
|
|
||||||
*/
|
|
||||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
|
||||||
#define CONFIG_BTB /* toggle branch predition */
|
|
||||||
#define CONFIG_ENABLE_36BIT_PHYS 1
|
|
||||||
|
|
||||||
#define CONFIG_SYS_CCSRBAR 0xef000000
|
|
||||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Diagnostics
|
|
||||||
*/
|
|
||||||
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
|
|
||||||
CONFIG_SYS_POST_I2C)
|
|
||||||
#define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \
|
|
||||||
CONFIG_SYS_I2C_LM75_ADDR, \
|
|
||||||
CONFIG_SYS_I2C_LM90_ADDR, \
|
|
||||||
CONFIG_SYS_I2C_PCA953X_ADDR0, \
|
|
||||||
CONFIG_SYS_I2C_PCA953X_ADDR2, \
|
|
||||||
CONFIG_SYS_I2C_PCA953X_ADDR3, \
|
|
||||||
CONFIG_SYS_I2C_RTC_ADDR}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Memory map
|
|
||||||
* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
|
|
||||||
* 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
|
|
||||||
* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
|
|
||||||
* 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
|
|
||||||
* 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
|
|
||||||
* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
|
|
||||||
* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
|
|
||||||
* 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
|
|
||||||
* 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* NAND flash configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_NAND_BASE 0xef800000
|
|
||||||
#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
|
|
||||||
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
|
|
||||||
CONFIG_SYS_NAND_BASE2}
|
|
||||||
#define CONFIG_SYS_MAX_NAND_DEVICE 2
|
|
||||||
#define CONFIG_NAND_FSL_ELBC
|
|
||||||
|
|
||||||
/*
|
|
||||||
* NOR flash configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_FLASH_BASE 0xf8000000
|
|
||||||
#define CONFIG_SYS_FLASH_BASE2 0xf0000000
|
|
||||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
|
||||||
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
|
|
||||||
{0xf7f40000, 0xc0000} }
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Chip select configuration
|
|
||||||
*/
|
|
||||||
/* NOR Flash 0 on CS0 */
|
|
||||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
|
|
||||||
BR_PS_16 | \
|
|
||||||
BR_V)
|
|
||||||
#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
|
|
||||||
OR_GPCM_CSNT | \
|
|
||||||
OR_GPCM_XACS | \
|
|
||||||
OR_GPCM_ACS_DIV2 | \
|
|
||||||
OR_GPCM_SCY_8 | \
|
|
||||||
OR_GPCM_TRLX | \
|
|
||||||
OR_GPCM_EHTR | \
|
|
||||||
OR_GPCM_EAD)
|
|
||||||
|
|
||||||
/* NOR Flash 1 on CS1 */
|
|
||||||
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
|
|
||||||
BR_PS_16 | \
|
|
||||||
BR_V)
|
|
||||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
|
|
||||||
|
|
||||||
/* NAND flash on CS2 */
|
|
||||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
|
|
||||||
(2<<BR_DECC_SHIFT) | \
|
|
||||||
BR_PS_8 | \
|
|
||||||
BR_MS_FCM | \
|
|
||||||
BR_V)
|
|
||||||
|
|
||||||
/* NAND flash on CS2 */
|
|
||||||
#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
|
|
||||||
OR_FCM_PGS | \
|
|
||||||
OR_FCM_CSCT | \
|
|
||||||
OR_FCM_CST | \
|
|
||||||
OR_FCM_CHT | \
|
|
||||||
OR_FCM_SCY_1 | \
|
|
||||||
OR_FCM_TRLX | \
|
|
||||||
OR_FCM_EHTR)
|
|
||||||
|
|
||||||
/* NAND flash on CS3 */
|
|
||||||
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
|
|
||||||
(2<<BR_DECC_SHIFT) | \
|
|
||||||
BR_PS_8 | \
|
|
||||||
BR_MS_FCM | \
|
|
||||||
BR_V)
|
|
||||||
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Use L1 as initial stack
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
|
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
|
|
||||||
|
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
|
|
||||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Serial Port
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_NS16550_SERIAL
|
|
||||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
|
||||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
|
||||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
|
||||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
|
||||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
|
||||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* I2C
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_I2C
|
|
||||||
#define CONFIG_SYS_I2C_FSL
|
|
||||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
|
||||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
|
||||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
|
||||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
|
||||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
|
||||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
|
||||||
|
|
||||||
/* I2C DS7505 temperature sensor */
|
|
||||||
#define CONFIG_SYS_I2C_LM75_ADDR 0x48
|
|
||||||
|
|
||||||
/* I2C ADT7461 temperature sensor */
|
|
||||||
#define CONFIG_SYS_I2C_LM90_ADDR 0x4C
|
|
||||||
|
|
||||||
/* I2C EEPROM - AT24C128B */
|
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
|
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
|
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
|
|
||||||
|
|
||||||
/* I2C RTC */
|
|
||||||
#define CONFIG_RTC_M41T11 1
|
|
||||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
|
||||||
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
|
|
||||||
|
|
||||||
/* GPIO */
|
|
||||||
#define CONFIG_PCA953X
|
|
||||||
#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
|
|
||||||
#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
|
|
||||||
#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
|
|
||||||
#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
|
|
||||||
#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
|
|
||||||
|
|
||||||
/*
|
|
||||||
* GPIO pin definitions, PU = pulled high, PD = pulled low
|
|
||||||
*/
|
|
||||||
/* PCA9557 @ 0x18*/
|
|
||||||
#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
|
|
||||||
#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
|
|
||||||
#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
|
|
||||||
#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
|
|
||||||
#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
|
|
||||||
#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */
|
|
||||||
|
|
||||||
/* PCA9557 @ 0x1e*/
|
|
||||||
#define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */
|
|
||||||
#define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */
|
|
||||||
#define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */
|
|
||||||
#define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */
|
|
||||||
#define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */
|
|
||||||
#define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */
|
|
||||||
#define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */
|
|
||||||
|
|
||||||
/* PCA9557 @ 0x1f */
|
|
||||||
#define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */
|
|
||||||
#define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */
|
|
||||||
#define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */
|
|
||||||
#define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */
|
|
||||||
#define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */
|
|
||||||
#define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */
|
|
||||||
#define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */
|
|
||||||
#define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* General PCI
|
|
||||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* controller 1 - PEX8112 or XMC, depending on build option */
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
|
|
||||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
|
||||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
|
|
||||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Networking options
|
|
||||||
*/
|
|
||||||
#define CONFIG_TSEC_TBI
|
|
||||||
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
|
|
||||||
#define CONFIG_ETHPRIME "eTSEC2"
|
|
||||||
|
|
||||||
/*
|
|
||||||
* In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
|
|
||||||
* 1000mbps SGMII link
|
|
||||||
*/
|
|
||||||
#define CONFIG_TSEC_TBICR_SETTINGS ( \
|
|
||||||
TBICR_PHY_RESET \
|
|
||||||
| TBICR_FULL_DUPLEX \
|
|
||||||
| TBICR_SPEED1_SET \
|
|
||||||
)
|
|
||||||
|
|
||||||
#define CONFIG_TSEC1 1
|
|
||||||
#define CONFIG_TSEC1_NAME "eTSEC1"
|
|
||||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
||||||
#define TSEC1_PHY_ADDR 1
|
|
||||||
#define TSEC1_PHYIDX 0
|
|
||||||
#define CONFIG_HAS_ETH0
|
|
||||||
|
|
||||||
#define CONFIG_TSEC2 1
|
|
||||||
#define CONFIG_TSEC2_NAME "eTSEC2"
|
|
||||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
||||||
#define TSEC2_PHY_ADDR 2
|
|
||||||
#define TSEC2_PHYIDX 0
|
|
||||||
#define CONFIG_HAS_ETH1
|
|
||||||
|
|
||||||
#define CONFIG_TSEC3 1
|
|
||||||
#define CONFIG_TSEC3_NAME "eTSEC3"
|
|
||||||
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
||||||
#define TSEC3_PHY_ADDR 3
|
|
||||||
#define TSEC3_PHYIDX 0
|
|
||||||
#define CONFIG_HAS_ETH2
|
|
||||||
|
|
||||||
/*
|
|
||||||
* USB
|
|
||||||
*/
|
|
||||||
#define CONFIG_USB_EHCI_FSL
|
|
||||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
|
||||||
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
|
|
||||||
#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data
|
|
||||||
* have to be in the first 16 MB of memory, since this is
|
|
||||||
* the maximum mapped by the Linux kernel during initialization.
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
|
|
||||||
#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment Configuration
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Flash memory map:
|
|
||||||
* fff80000 - ffffffff Pri U-Boot (512 KB)
|
|
||||||
* fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
|
|
||||||
* fff00000 - fff3ffff Pri FDT (256KB)
|
|
||||||
* fef00000 - ffefffff Pri OS image (16MB)
|
|
||||||
* f8000000 - feefffff Pri OS Use/Filesystem (111MB)
|
|
||||||
*
|
|
||||||
* f7f80000 - f7ffffff Sec U-Boot (512 KB)
|
|
||||||
* f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
|
|
||||||
* f7f00000 - f7f3ffff Sec FDT (256KB)
|
|
||||||
* f6f00000 - f7efffff Sec OS image (16MB)
|
|
||||||
* f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
|
|
||||||
*/
|
|
||||||
#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
|
|
||||||
#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
|
|
||||||
#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
|
|
||||||
#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
|
|
||||||
#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
|
|
||||||
#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
|
|
||||||
|
|
||||||
#define CONFIG_PROG_UBOOT1 \
|
|
||||||
"$download_cmd $loadaddr $ubootfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
|
|
||||||
"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
|
|
||||||
"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
|
|
||||||
"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
|
|
||||||
"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_UBOOT2 \
|
|
||||||
"$download_cmd $loadaddr $ubootfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
|
|
||||||
"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
|
|
||||||
"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
|
|
||||||
"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
|
|
||||||
"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_BOOT_OS_NET \
|
|
||||||
"$download_cmd $osaddr $osfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"if test -n $fdtaddr; then " \
|
|
||||||
"$download_cmd $fdtaddr $fdtfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"bootm $osaddr - $fdtaddr; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT DOWNLOAD FAILED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"bootm $osaddr; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_OS1 \
|
|
||||||
"$download_cmd $osaddr $osfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
|
|
||||||
"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
|
|
||||||
"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo OS PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_OS2 \
|
|
||||||
"$download_cmd $osaddr $osfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
|
|
||||||
"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
|
|
||||||
"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo OS PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo OS DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_FDT1 \
|
|
||||||
"$download_cmd $fdtaddr $fdtfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
|
|
||||||
"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
|
|
||||||
"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo FDT PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_PROG_FDT2 \
|
|
||||||
"$download_cmd $fdtaddr $fdtfile; " \
|
|
||||||
"if test $? -eq 0; then " \
|
|
||||||
"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
|
|
||||||
"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
|
|
||||||
"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
|
|
||||||
"if test $? -ne 0; then " \
|
|
||||||
"echo FDT PROGRAM FAILED; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT PROGRAM SUCCEEDED; " \
|
|
||||||
"fi; " \
|
|
||||||
"else; " \
|
|
||||||
"echo FDT DOWNLOAD FAILED; " \
|
|
||||||
"fi;"
|
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
||||||
"autoload=yes\0" \
|
|
||||||
"download_cmd=tftp\0" \
|
|
||||||
"console_args=console=ttyS0,115200\0" \
|
|
||||||
"root_args=root=/dev/nfs rw\0" \
|
|
||||||
"misc_args=ip=on\0" \
|
|
||||||
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
|
|
||||||
"bootfile=/home/user/file\0" \
|
|
||||||
"osfile=/home/user/board.uImage\0" \
|
|
||||||
"fdtfile=/home/user/board.dtb\0" \
|
|
||||||
"ubootfile=/home/user/u-boot.bin\0" \
|
|
||||||
"fdtaddr=0x1e00000\0" \
|
|
||||||
"osaddr=0x1000000\0" \
|
|
||||||
"loadaddr=0x1000000\0" \
|
|
||||||
"prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
|
|
||||||
"prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
|
|
||||||
"prog_os1="CONFIG_PROG_OS1"\0" \
|
|
||||||
"prog_os2="CONFIG_PROG_OS2"\0" \
|
|
||||||
"prog_fdt1="CONFIG_PROG_FDT1"\0" \
|
|
||||||
"prog_fdt2="CONFIG_PROG_FDT2"\0" \
|
|
||||||
"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
|
|
||||||
"bootcmd_flash1=run set_bootargs; " \
|
|
||||||
"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
|
|
||||||
"bootcmd_flash2=run set_bootargs; " \
|
|
||||||
"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
|
|
||||||
"bootcmd=run bootcmd_flash1\0"
|
|
||||||
#endif /* __CONFIG_H */
|
|
Loading…
Reference in a new issue