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https://github.com/AsahiLinux/u-boot
synced 2025-01-25 11:25:17 +00:00
ppc/85xx: Clean up mpc8572DS PCI setup code
Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
Tom Rix
parent
aaf38ec306
commit
ed18c1913b
1 changed files with 70 additions and 154 deletions
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@ -160,189 +160,105 @@ static struct pci_controller pcie2_hose;
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static struct pci_controller pcie3_hose;
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#endif
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int first_free_busno=0;
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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uint devdisr = gur->devdisr;
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uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
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struct fsl_pci_info pci_info[3];
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u32 devdisr, pordevsr, io_sel, host_agent, temp32;
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int first_free_busno = 0;
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int num = 0;
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int pcie_ep, pcie_configured;
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devdisr = in_be32(&gur->devdisr);
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pordevsr = in_be32(&gur->pordevsr);
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io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
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debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
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devdisr, io_sel, host_agent);
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
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if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
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printf (" eTSEC1 is in sgmii mode.\n");
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
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if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
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printf (" eTSEC2 is in sgmii mode.\n");
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
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if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
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printf (" eTSEC3 is in sgmii mode.\n");
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if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
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if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
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printf (" eTSEC4 is in sgmii mode.\n");
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puts("\n");
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#ifdef CONFIG_PCIE3
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
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struct pci_controller *hose = &pcie3_hose;
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int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
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int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
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struct pci_region *r = hose->regions;
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u32 temp32;
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pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
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pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
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printf ("\n PCIE3 connected to ULI as %s (base address %x)",
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pcie_ep ? "End Point" : "Root Complex",
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(uint)pci);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
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}
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printf ("\n");
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE3_MEM_BUS,
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CONFIG_SYS_PCIE3_MEM_PHYS,
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CONFIG_SYS_PCIE3_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCIE3_IO_BUS,
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CONFIG_SYS_PCIE3_IO_PHYS,
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CONFIG_SYS_PCIE3_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = r - hose->regions;
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hose->first_busno=first_free_busno;
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fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
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first_free_busno=hose->last_busno+1;
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printf (" PCIE3 on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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/*
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* Activate ULI1575 legacy chip by performing a fake
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* memory access. Needed to make ULI RTC work.
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* Device 1d has the first on-board memory BAR.
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*/
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pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
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PCI_BASE_ADDRESS_1, &temp32);
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if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
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void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
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temp32, 4, 0);
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debug(" uli1572 read to %p\n", p);
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in_be32(p);
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}
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} else {
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printf (" PCIE3: disabled\n");
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
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SET_STD_PCIE_INFO(pci_info[num], 3);
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printf (" PCIE3 connected to ULI as %s (base addr %lx)\n",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie3_hose, first_free_busno);
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/*
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* Activate ULI1575 legacy chip by performing a fake
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* memory access. Needed to make ULI RTC work.
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* Device 1d has the first on-board memory BAR.
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*/
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pci_hose_read_config_dword(&pcie3_hose, PCI_BDF(2, 0x1d, 0),
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PCI_BASE_ADDRESS_1, &temp32);
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if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
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void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
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temp32, 4, 0);
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debug(" uli1572 read to %p\n", p);
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in_be32(p);
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}
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} else {
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printf (" PCIE3: disabled\n");
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}
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puts("\n");
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
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#endif
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#ifdef CONFIG_PCIE2
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
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struct pci_controller *hose = &pcie2_hose;
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int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
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int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
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struct pci_region *r = hose->regions;
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
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printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
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pcie_ep ? "End Point" : "Root Complex",
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(uint)pci);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
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}
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printf ("\n");
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE2_MEM_BUS,
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CONFIG_SYS_PCIE2_MEM_PHYS,
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CONFIG_SYS_PCIE2_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCIE2_IO_BUS,
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CONFIG_SYS_PCIE2_IO_PHYS,
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CONFIG_SYS_PCIE2_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = r - hose->regions;
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hose->first_busno=first_free_busno;
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fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
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first_free_busno=hose->last_busno+1;
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printf (" PCIE2 on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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} else {
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printf (" PCIE2: disabled\n");
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}
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pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
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pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
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SET_STD_PCIE_INFO(pci_info[num], 2);
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printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie2_hose, first_free_busno);
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} else {
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printf (" PCIE2: disabled\n");
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}
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puts("\n");
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
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#endif
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#ifdef CONFIG_PCIE1
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
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struct pci_controller *hose = &pcie1_hose;
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int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
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int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
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struct pci_region *r = hose->regions;
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)",
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pcie_ep ? "End Point" : "Root Complex",
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(uint)pci);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
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}
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printf ("\n");
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_MEM_BUS,
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CONFIG_SYS_PCIE1_MEM_PHYS,
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CONFIG_SYS_PCIE1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_IO_BUS,
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CONFIG_SYS_PCIE1_IO_PHYS,
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CONFIG_SYS_PCIE1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = r - hose->regions;
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hose->first_busno=first_free_busno;
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fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
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first_free_busno=hose->last_busno+1;
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printf(" PCIE1 on bus %02x - %02x\n",
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hose->first_busno,hose->last_busno);
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} else {
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printf (" PCIE1: disabled\n");
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}
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pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
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pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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SET_STD_PCIE_INFO(pci_info[num], 1);
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printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
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pcie_ep ? "End Point" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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} else {
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printf (" PCIE1: disabled\n");
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}
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puts("\n");
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
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#endif
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}
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#endif
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