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Xilinx changes for v2021.10-rc4

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doc:
 - Fix uefi documentation
 
 spi:
 - Fix gqspi driver for single configuration
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Merge tag 'xilinx-for-v2021.10-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2021.10-rc4

doc:
- Fix uefi documentation

spi:
- Fix gqspi driver for single configuration
This commit is contained in:
Tom Rini 2021-09-03 13:17:43 -04:00
commit ecd6e0ce5a
2 changed files with 14 additions and 17 deletions
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1
doc/develop/uefi/uefi.rst
View file

@ -392,7 +392,6 @@ settings::
CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT=y
CONFIG_EFI_CAPSULE_FIRMWARE=y
CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_EFI_CAPSULE_FMP_HEADER=y
In addition, the following config needs to be disabled(QEMU ARM specific)::

30
drivers/spi/zynqmp_gqspi.c
View file

@ -77,6 +77,7 @@
#define GQSPI_GFIFO_SELECT BIT(0)
#define GQSPI_FIFO_THRESHOLD 1
#define GQSPI_GENFIFO_THRESHOLD 31
#define SPI_XFER_ON_BOTH 0
#define SPI_XFER_ON_LOWER 1
@ -197,14 +198,15 @@ static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->idisr);
writel(GQSPI_FIFO_THRESHOLD, &regs->txftr);
writel(GQSPI_FIFO_THRESHOLD, &regs->rxftr);
writel(GQSPI_GENFIFO_THRESHOLD, &regs->gqfthr);
writel(GQSPI_GFIFO_ALL_INT_MASK, &regs->isr);
writel(~GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
config_reg = readl(&regs->confr);
config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK |
GQSPI_CONFIG_MODE_EN_MASK);
config_reg |= GQSPI_CONFIG_DMA_MODE |
GQSPI_GFIFO_WP_HOLD |
GQSPI_DFLT_BAUD_RATE_DIV;
config_reg |= GQSPI_CONFIG_DMA_MODE | GQSPI_GFIFO_WP_HOLD |
GQSPI_DFLT_BAUD_RATE_DIV | GQSPI_GFIFO_STRT_MODE_MASK;
writel(config_reg, &regs->confr);
writel(GQSPI_ENABLE_ENABLE_MASK, &regs->enbr);
@ -242,6 +244,8 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
u32 config_reg, ier;
int ret = 0;
writel(gqspi_fifo_reg, &regs->genfifo);
config_reg = readl(&regs->confr);
/* Manual start if needed */
config_reg |= GQSPI_STRT_GEN_FIFO;
@ -249,16 +253,15 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
/* Enable interrupts */
ier = readl(&regs->ier);
ier |= GQSPI_IXR_GFNFULL_MASK;
ier |= GQSPI_IXR_GFEMTY_MASK;
writel(ier, &regs->ier);
/* Wait until the fifo is not full to write the new command */
ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFNFULL_MASK, 1,
/* Wait until the gen fifo is empty to write the new command */
ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFEMTY_MASK, 1,
GQSPI_TIMEOUT, 1);
if (ret)
printf("%s Timeout\n", __func__);
writel(gqspi_fifo_reg, &regs->genfifo);
}
static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
@ -572,25 +575,20 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
u32 gen_fifo_cmd, u32 *buf)
{
u32 addr;
u32 size, len;
u32 size;
u32 actuallen = priv->len;
int ret = 0;
struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
writel((unsigned long)buf, &dma_regs->dmadst);
writel(roundup(priv->len, ARCH_DMA_MINALIGN), &dma_regs->dmasize);
writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize);
writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
addr = (unsigned long)buf;
size = roundup(priv->len, ARCH_DMA_MINALIGN);
size = roundup(priv->len, GQSPI_DMA_ALIGN);
flush_dcache_range(addr, addr + size);
while (priv->len) {
len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
if (!(gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) &&
(len % ARCH_DMA_MINALIGN)) {
gen_fifo_cmd &= ~GENMASK(7, 0);
gen_fifo_cmd |= roundup(len, ARCH_DMA_MINALIGN);
}
zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);