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ARM: dts: renesas: Synchronize RZ R7S72100 RZ/A1 DTs with Linux 6.5.3

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Synchronize RZ R7S72100 RZ/A1 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut 2023-09-17 16:13:14 +02:00
parent 90e6730808
commit ec2faaab65
2 changed files with 45 additions and 14 deletions
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3
arch/arm/dts/r7s72100-gr-peach.dts
View file

@ -41,6 +41,9 @@
bank-width = <4>; bank-width = <4>;
device-width = <1>; device-width = <1>;
clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>;
power-domains = <&cpg_clocks>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;

56
arch/arm/dts/r7s72100.dtsi
View file

@ -313,9 +313,9 @@
mmcif: mmc@e804c800 { mmcif: mmc@e804c800 {
compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif"; compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
reg = <0xe804c800 0x80>; reg = <0xe804c800 0x80>;
interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R7S72100_CLK_MMCIF>; clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
reg-io-width = <4>; reg-io-width = <4>;
@ -323,12 +323,12 @@
status = "disabled"; status = "disabled";
}; };
sdhi0: sd@e804e000 { sdhi0: mmc@e804e000 {
compatible = "renesas,sdhi-r7s72100"; compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e000 0x100>; reg = <0xe804e000 0x100>;
interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
<&mstp12_clks R7S72100_CLK_SDHI01>; <&mstp12_clks R7S72100_CLK_SDHI01>;
@ -339,12 +339,12 @@
status = "disabled"; status = "disabled";
}; };
sdhi1: sd@e804e800 { sdhi1: mmc@e804e800 {
compatible = "renesas,sdhi-r7s72100"; compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e800 0x100>; reg = <0xe804e800 0x100>;
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp12_clks R7S72100_CLK_SDHI10>, clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
<&mstp12_clks R7S72100_CLK_SDHI11>; <&mstp12_clks R7S72100_CLK_SDHI11>;
@ -467,11 +467,12 @@
#clock-cells = <1>; #clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0438 4>; reg = <0xfcfe0438 4>;
clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>; clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>;
clock-indices = < clock-indices = <
R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1
>; >;
clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3"; clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1";
}; };
mstp10_clks: mstp10_clks@fcfe043c { mstp10_clks: mstp10_clks@fcfe043c {
@ -498,7 +499,7 @@
clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
}; };
pinctrl: pin-controller@fcfe3000 { pinctrl: pinctrl@fcfe3000 {
compatible = "renesas,r7s72100-ports"; compatible = "renesas,r7s72100-ports";
reg = <0xfcfe3000 0x4230>; reg = <0xfcfe3000 0x4230>;
@ -607,6 +608,8 @@
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&mstp9_clks R7S72100_CLK_I2C0>; clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
clock-frequency = <100000>; clock-frequency = <100000>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
@ -626,6 +629,8 @@
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&mstp9_clks R7S72100_CLK_I2C1>; clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
clock-frequency = <100000>; clock-frequency = <100000>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
@ -645,6 +650,8 @@
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&mstp9_clks R7S72100_CLK_I2C2>; clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
clock-frequency = <100000>; clock-frequency = <100000>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
@ -664,12 +671,33 @@
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&mstp9_clks R7S72100_CLK_I2C3>; clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
clock-frequency = <100000>; clock-frequency = <100000>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
irqc: interrupt-controller@fcfef800 {
compatible = "renesas,r7s72100-irqc",
"renesas,rza1-irqc";
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
reg = <0xfcfef800 0x6>;
interrupt-map =
<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <7 0>;
};
mtu2: timer@fcff0000 { mtu2: timer@fcff0000 {
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
reg = <0xfcff0000 0x400>; reg = <0xfcff0000 0x400>;