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[PATCH] Remove testing 4xx enet PHY setup

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Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2006-11-27 14:46:06 +01:00
parent 1c2ce22620
commit ec0c2ec725
2 changed files with 2 additions and 17 deletions
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17
cpu/ppc4xx/4xx_enet.c
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@ -560,22 +560,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
* otherwise, just check the speeds & feeds
*/
if (hw_p->first_init == 0) {
#if defined(CONFIG_88E1111_CLK_DELAY)
/*
* On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs
* the "RGMII transmit timing control" and "RGMII receive
* timing control" bits set, so that Gbit communication works
* without problems.
* Also set the "Transmitter disable" to 1 to enable the
* transmitter.
* After setting these bits a soft-reset must occur for this
* change to become active.
*/
miiphy_read (dev->name, reg, 0x14, &reg_short);
reg_short |= (1 << 7) | (1 << 1) | (1 << 0);
miiphy_write (dev->name, reg, 0x14, reg_short);
#endif
#if defined(CONFIG_M88E1111_PHY) /* test-only: merge with CONFIG_88E1111_CLK_DELAY !!! */
#if defined(CONFIG_M88E1111_PHY)
miiphy_write (dev->name, reg, 0x14, 0x0ce3);
miiphy_write (dev->name, reg, 0x18, 0x4101);
miiphy_write (dev->name, reg, 0x09, 0x0e00);

2
include/configs/alpr.h
View file

@ -187,7 +187,7 @@
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_88E1111_CLK_DELAY 1 /* set CLK delay on ALPR */
#define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */