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https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
Move ICS CLK chip frequency calculation code into a common board library
We have several boards that use the same ICS307 CLK chip to drive the System clock and DDR clock. Move the code into a common location so we share it. Convert the P2020DS board as the first to use the new common ICS307 code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Timur Tabi <timur@freescale.com>
This commit is contained in:
Kumar Gala
parent
b4a60e521c
commit
ebf9d5261e
5 changed files with 124 additions and 160 deletions
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@ -42,6 +42,7 @@ COBJS-$(CONFIG_MPC8541CDS) += cds_pci_ft.o
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COBJS-$(CONFIG_MPC8548CDS) += cds_pci_ft.o
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COBJS-$(CONFIG_MPC8555CDS) += cds_pci_ft.o
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COBJS-$(CONFIG_P2020DS) += ics307_clk.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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88
board/freescale/common/ics307_clk.c
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88
board/freescale/common/ics307_clk.c
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@ -0,0 +1,88 @@
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/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include "ics307_clk.h"
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#ifdef CONFIG_FSL_NGPIXIS
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#include "ngpixis.h"
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#else
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#include "pixis.h"
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#endif
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/* decode S[0-2] to Output Divider (OD) */
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static u8 ics307_s_to_od[] = {
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10, 2, 8, 4, 5, 7, 3, 6
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};
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/*
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* Calculate frequency being generated by ICS307-02 clock chip based upon
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* the control bytes being programmed into it.
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*/
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static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2)
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{
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const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
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unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
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unsigned long rdw = cw2 & 0x7F;
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unsigned long od = ics307_s_to_od[cw0 & 0x7];
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unsigned long freq;
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/*
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* CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)
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*
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* cw0: C1 C0 TTL F1 F0 S2 S1 S0
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* cw1: V8 V7 V6 V5 V4 V3 V2 V1
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* cw2: V0 R6 R5 R4 R3 R2 R1 R0
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*
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* R6:R0 = Reference Divider Word (RDW)
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* V8:V0 = VCO Divider Word (VDW)
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* S2:S0 = Output Divider Select (OD)
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* F1:F0 = Function of CLK2 Output
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* TTL = duty cycle
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* C1:C0 = internal load capacitance for cyrstal
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*
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*/
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freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);
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debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
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freq);
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return freq;
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}
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unsigned long get_board_sys_clk(void)
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{
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return ics307_clk_freq(
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in_8(&pixis->sclk[0]),
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in_8(&pixis->sclk[1]),
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in_8(&pixis->sclk[2]));
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}
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unsigned long get_board_ddr_clk(void)
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{
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return ics307_clk_freq(
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in_8(&pixis->dclk[0]),
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in_8(&pixis->dclk[1]),
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in_8(&pixis->dclk[2]));
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}
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30
board/freescale/common/ics307_clk.h
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30
board/freescale/common/ics307_clk.h
Normal file
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@ -0,0 +1,30 @@
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/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ICS_CLK_H_
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#define __ICS_CLK_H_ 1
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#ifndef __ASSEMBLY__
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extern unsigned long get_board_sys_clk(void);
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extern unsigned long get_board_ddr_clk(void);
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#endif
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#endif /* __ICS_CLK_H_ */
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@ -313,155 +313,6 @@ int board_early_init_r(void)
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return 0;
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}
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#ifdef CONFIG_GET_CLK_FROM_ICS307
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/* decode S[0-2] to Output Divider (OD) */
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static unsigned char ics307_S_to_OD[] = {
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10, 2, 8, 4, 5, 7, 3, 6
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};
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/* Calculate frequency being generated by ICS307-02 clock chip based upon
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* the control bytes being programmed into it. */
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/* XXX: This function should probably go into a common library */
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static unsigned long
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ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2)
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{
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const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
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unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
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unsigned long RDW = cw2 & 0x7F;
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unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
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unsigned long freq;
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/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
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/* cw0: C1 C0 TTL F1 F0 S2 S1 S0
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* cw1: V8 V7 V6 V5 V4 V3 V2 V1
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* cw2: V0 R6 R5 R4 R3 R2 R1 R0
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*
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* R6:R0 = Reference Divider Word (RDW)
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* V8:V0 = VCO Divider Word (VDW)
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* S2:S0 = Output Divider Select (OD)
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* F1:F0 = Function of CLK2 Output
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* TTL = duty cycle
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* C1:C0 = internal load capacitance for cyrstal
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*/
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/* Adding 1 to get a "nicely" rounded number, but this needs
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* more tweaking to get a "properly" rounded number. */
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freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
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debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
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freq);
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return freq;
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}
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unsigned long get_board_sys_clk(ulong dummy)
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{
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return gd->bus_clk;
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}
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unsigned long get_board_ddr_clk(ulong dummy)
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{
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return gd->mem_clk;
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}
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unsigned long calculate_board_sys_clk(ulong dummy)
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{
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ulong val;
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val = ics307_clk_freq(in_8(&pixis->sclk[0]), in_8(&pixis->sclk[1]),
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in_8(&pixis->sclk[2]));
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debug("sysclk val = %lu\n", val);
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return val;
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}
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unsigned long calculate_board_ddr_clk(ulong dummy)
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{
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ulong val;
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val = ics307_clk_freq(in_8(&pixis->dclk[0]), in_8(&pixis->dclk[1]),
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in_8(&pixis->dclk[2]));
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debug("ddrclk val = %lu\n", val);
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return val;
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}
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#else
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unsigned long get_board_sys_clk(ulong dummy)
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{
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u8 i;
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ulong val = 0;
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i = in_8(&pixis->spd);
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i &= 0x07;
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switch (i) {
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case 0:
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val = 33333333;
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break;
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case 1:
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val = 40000000;
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break;
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case 2:
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val = 50000000;
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break;
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case 3:
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val = 66666666;
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break;
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case 4:
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val = 83333333;
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break;
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case 5:
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val = 100000000;
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break;
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case 6:
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val = 133333333;
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break;
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case 7:
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val = 166666666;
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break;
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}
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return val;
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}
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unsigned long get_board_ddr_clk(ulong dummy)
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{
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u8 i;
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ulong val = 0;
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i = in_8(&pixis->spd);
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i &= 0x38;
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i >>= 3;
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switch (i) {
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case 0:
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val = 33333333;
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break;
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case 1:
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val = 40000000;
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break;
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case 2:
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val = 50000000;
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break;
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case 3:
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val = 66666666;
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break;
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case 4:
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val = 83333333;
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break;
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case 5:
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val = 100000000;
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break;
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case 6:
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val = 133333333;
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break;
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case 7:
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val = 166666666;
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break;
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}
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return val;
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}
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#endif
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#ifdef CONFIG_TSEC_ENET
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int board_eth_init(bd_t *bis)
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{
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@ -1,5 +1,5 @@
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/*
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* Copyright 2007-2009 Freescale Semiconductor, Inc.
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* Copyright 2007-2010 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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@ -27,6 +27,8 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include "../board/freescale/common/ics307_clk.h"
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#ifdef CONFIG_MK_36BIT
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#define CONFIG_PHYS_64BIT
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#endif
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@ -54,17 +56,9 @@
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#ifndef __ASSEMBLY__
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extern unsigned long calculate_board_sys_clk(unsigned long dummy);
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extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
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/* extern unsigned long get_board_sys_clk(unsigned long dummy); */
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/* extern unsigned long get_board_ddr_clk(unsigned long dummy); */
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#endif
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#define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0) /* sysclk for MPC85xx */
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#define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
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#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
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#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
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#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
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from ICS307 instead of switches */
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/*
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* These can be toggled for performance analysis, otherwise use default.
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