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https://github.com/AsahiLinux/u-boot
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ppc4xx: Cleanup PPC4xx I2C infrastructure
This patch cleans up the PPC4xx I2C intrastructure: - Use C struct to describe the I2C registers instead of defines - Coding style cleanup (braces, whitespace, comments, line length) - Extract common code from i2c_read() and i2c_write() - Remove unneeded IIC defines from ppc405.h & ppc440.h Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
b2f618f215
commit
eb5eb2b0f7
4 changed files with 118 additions and 157 deletions
199
cpu/ppc4xx/i2c.c
199
cpu/ppc4xx/i2c.c
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@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2007
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* (C) Copyright 2007-2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr>
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@ -37,7 +37,8 @@
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_I2C_MULTI_BUS)
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/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
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/*
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* Initialize the bus pointer to whatever one the SPD EEPROM is on.
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* Default is bus 0. This is necessary because the DDR initialization
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* runs from ROM, and we can't switch buses because we can't modify
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* the global variables.
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@ -45,59 +46,63 @@ DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_SYS_SPD_BUS_NUM
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#endif
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static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM;
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static unsigned int i2c_bus_num __attribute__ ((section (".data"))) =
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CONFIG_SYS_SPD_BUS_NUM;
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#endif /* CONFIG_I2C_MULTI_BUS */
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static void _i2c_bus_reset(void)
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{
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struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
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int i;
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u8 dc;
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/* Reset status register */
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/* write 1 in SCMP and IRQA to clear these fields */
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out_8((u8 *)IIC_STS, 0x0A);
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out_8(&i2c->sts, 0x0A);
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/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
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out_8((u8 *)IIC_EXTSTS, 0x8F);
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out_8(&i2c->extsts, 0x8F);
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/* Place chip in the reset state */
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out_8((u8 *)IIC_XTCNTLSS, IIC_XTCNTLSS_SRST);
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out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST);
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/* Check if bus is free */
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dc = in_8((u8 *)IIC_DIRECTCNTL);
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dc = in_8(&i2c->directcntl);
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if (!DIRCTNL_FREE(dc)){
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/* Try to set bus free state */
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out_8((u8 *)IIC_DIRECTCNTL, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC);
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out_8(&i2c->directcntl, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC);
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/* Wait until we regain bus control */
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for (i = 0; i < 100; ++i) {
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dc = in_8((u8 *)IIC_DIRECTCNTL);
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dc = in_8(&i2c->directcntl);
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if (DIRCTNL_FREE(dc))
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break;
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/* Toggle SCL line */
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dc ^= IIC_DIRCNTL_SCC;
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out_8((u8 *)IIC_DIRECTCNTL, dc);
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out_8(&i2c->directcntl, dc);
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udelay(10);
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dc ^= IIC_DIRCNTL_SCC;
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out_8((u8 *)IIC_DIRECTCNTL, dc);
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out_8(&i2c->directcntl, dc);
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}
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}
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/* Remove reset */
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out_8((u8 *)IIC_XTCNTLSS, 0);
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out_8(&i2c->xtcntlss, 0);
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}
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void i2c_init(int speed, int slaveadd)
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void i2c_init(int speed, int slaveaddr)
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{
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unsigned long freqOPB;
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struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
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int val, divisor;
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int bus;
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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/* call board specific i2c bus reset routine before accessing the */
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/* environment, which might be in a chip on that bus. For details */
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/* about this problem see doc/I2C_Edge_Conditions. */
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/*
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* Call board specific i2c bus reset routine before accessing the
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* environment, which might be in a chip on that bus. For details
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* about this problem see doc/I2C_Edge_Conditions.
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*/
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i2c_init_board();
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#endif
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@ -109,54 +114,52 @@ void i2c_init(int speed, int slaveadd)
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_i2c_bus_reset();
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/* clear lo master address */
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out_8((u8 *)IIC_LMADR, 0);
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out_8(&i2c->lmadr, 0);
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/* clear hi master address */
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out_8((u8 *)IIC_HMADR, 0);
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out_8(&i2c->hmadr, 0);
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/* clear lo slave address */
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out_8((u8 *)IIC_LSADR, 0);
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out_8(&i2c->lsadr, 0);
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/* clear hi slave address */
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out_8((u8 *)IIC_HSADR, 0);
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out_8(&i2c->hsadr, 0);
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/* Clock divide Register */
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/* get OPB frequency */
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freqOPB = get_OPB_freq();
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/* set divisor according to freqOPB */
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divisor = (freqOPB - 1) / 10000000;
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/* set divisor according to freq_opb */
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divisor = (get_OPB_freq() - 1) / 10000000;
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if (divisor == 0)
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divisor = 1;
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out_8((u8 *)IIC_CLKDIV, divisor);
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out_8(&i2c->clkdiv, divisor);
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/* no interrupts */
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out_8((u8 *)IIC_INTRMSK, 0);
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out_8(&i2c->intrmsk, 0);
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/* clear transfer count */
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out_8((u8 *)IIC_XFRCNT, 0);
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out_8(&i2c->xfrcnt, 0);
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/* clear extended control & stat */
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/* write 1 in SRC SRS SWC SWS to clear these fields */
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out_8((u8 *)IIC_XTCNTLSS, 0xF0);
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out_8(&i2c->xtcntlss, 0xF0);
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/* Mode Control Register
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Flush Slave/Master data buffer */
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out_8((u8 *)IIC_MDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
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out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
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val = in_8((u8 *)IIC_MDCNTL);
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val = in_8(&i2c->mdcntl);
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/* Ignore General Call, slave transfers are ignored,
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* disable interrupts, exit unknown bus state, enable hold
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* SCL 100kHz normaly or FastMode for 400kHz and above
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*/
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val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
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val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL;
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if (speed >= 400000)
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val |= IIC_MDCNTL_FSM;
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out_8((u8 *)IIC_MDCNTL, val);
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out_8(&i2c->mdcntl, val);
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/* clear control reg */
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out_8((u8 *)IIC_CNTL, 0x00);
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out_8(&i2c->cntl, 0x00);
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}
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/* set to SPD bus as default bus upon powerup */
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@ -195,13 +198,14 @@ static int i2c_transfer(unsigned char cmd_type,
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unsigned char data[],
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unsigned short data_len)
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{
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unsigned char* ptr;
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struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
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u8 *ptr;
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int reading;
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int tran,cnt;
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int tran, cnt;
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int result;
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int status;
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int i;
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uchar creg;
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u8 creg;
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if (data == 0 || data_len == 0) {
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/* Don't support data transfer of no length or to address 0 */
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@ -219,12 +223,13 @@ static int i2c_transfer(unsigned char cmd_type,
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}
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/* Clear Stop Complete Bit */
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out_8((u8 *)IIC_STS, IIC_STS_SCMP);
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out_8(&i2c->sts, IIC_STS_SCMP);
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/* Check init */
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i = 10;
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do {
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/* Get status */
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status = in_8((u8 *)IIC_STS);
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status = in_8(&i2c->sts);
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i--;
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} while ((status & IIC_STS_PT) && (i > 0));
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@ -232,13 +237,16 @@ static int i2c_transfer(unsigned char cmd_type,
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result = IIC_NOK_TOUT;
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return(result);
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}
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/* flush the Master/Slave Databuffers */
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out_8((u8 *)IIC_MDCNTL, ((in_8((u8 *)IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
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out_8(&i2c->mdcntl, in_8(&i2c->mdcntl) |
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IIC_MDCNTL_FMDB | IIC_MDCNTL_FSDB);
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/* need to wait 4 OPB clocks? code below should take that long */
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/* 7-bit adressing */
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out_8((u8 *)IIC_HMADR, 0);
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out_8((u8 *)IIC_LMADR, chip);
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out_8(&i2c->hmadr, 0);
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out_8(&i2c->lmadr, chip);
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tran = 0;
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result = IIC_OK;
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@ -247,9 +255,10 @@ static int i2c_transfer(unsigned char cmd_type,
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while (tran != cnt && (result == IIC_OK)) {
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int bc,j;
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/* Control register =
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* Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
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* Transfer is a sequence of transfers
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/*
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* Control register =
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* Normal transfer, 7-bits adressing, Transfer up to
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* bc bytes, Normal start, Transfer is a sequence of transfers
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*/
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creg |= IIC_CNTL_PT;
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@ -259,32 +268,36 @@ static int i2c_transfer(unsigned char cmd_type,
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if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt))
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creg |= IIC_CNTL_CHT;
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if (reading)
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if (reading) {
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creg |= IIC_CNTL_READ;
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else
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for(j=0; j < bc; j++)
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} else {
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for(j = 0; j < bc; j++) {
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/* Set buffer */
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out_8((u8 *)IIC_MDBUF, ptr[tran+j]);
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out_8((u8 *)IIC_CNTL, creg);
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out_8(&i2c->mdbuf, ptr[tran + j]);
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}
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}
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out_8(&i2c->cntl, creg);
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/* Transfer is in progress
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/*
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* Transfer is in progress
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* we have to wait for upto 5 bytes of data
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* 1 byte chip address+r/w bit then bc bytes
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* of data.
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* udelay(10) is 1 bit time at 100khz
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* Doubled for slop. 20 is too small.
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*/
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i = 2*5*8;
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i = 2 * 5 * 8;
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do {
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/* Get status */
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status = in_8((u8 *)IIC_STS);
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status = in_8(&i2c->sts);
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udelay(10);
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i--;
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} while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) && (i > 0));
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} while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) &&
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(i > 0));
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if (status & IIC_STS_ERR) {
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result = IIC_NOK;
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status = in_8((u8 *)IIC_EXTSTS);
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status = in_8(&i2c->extsts);
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/* Lost arbitration? */
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if (status & IIC_EXTSTS_LA)
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result = IIC_NOK_LA;
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@ -297,19 +310,21 @@ static int i2c_transfer(unsigned char cmd_type,
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} else if ( status & IIC_STS_PT) {
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result = IIC_NOK_TOUT;
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}
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/* Command is reading => get buffer */
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if ((reading) && (result == IIC_OK)) {
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/* Are there data in buffer */
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if (status & IIC_STS_MDBS) {
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/*
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* even if we have data we have to wait 4OPB clocks
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* for it to hit the front of the FIFO, after that
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* we can just read. We should check XFCNT here and
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* if the FIFO is full there is no need to wait.
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* even if we have data we have to wait 4OPB
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* clocks for it to hit the front of the FIFO,
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* after that we can just read. We should check
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* XFCNT here and if the FIFO is full there is
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* no need to wait.
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*/
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udelay(1);
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for (j=0; j<bc; j++)
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ptr[tran+j] = in_8((u8 *)IIC_MDBUF);
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for (j = 0; j < bc; j++)
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ptr[tran + j] = in_8(&i2c->mdbuf);
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} else
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result = IIC_NOK_DATA;
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}
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@ -324,7 +339,7 @@ static int i2c_transfer(unsigned char cmd_type,
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creg = IIC_CNTL_RPST;
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}
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}
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return (result);
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return result;
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}
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int i2c_probe(uchar chip)
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@ -338,17 +353,17 @@ int i2c_probe(uchar chip)
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* address was <ACK>ed (i.e. there was a chip at that address which
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* drove the data line low).
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*/
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return (i2c_transfer(1, chip << 1, 0,0, buf, 1) != 0);
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return (i2c_transfer(1, chip << 1, 0, 0, buf, 1) != 0);
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}
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int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
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static int ppc4xx_i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer,
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int len, int read)
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{
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uchar xaddr[4];
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int ret;
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if (alen > 4) {
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printf ("I2C read: addr len %d not supported\n", alen);
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printf("I2C: addr len %d not supported\n", alen);
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return 1;
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}
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@ -373,50 +388,30 @@ int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
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* hidden in the chip address.
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*/
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if (alen > 0)
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chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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chip |= ((addr >> (alen * 8)) &
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CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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#endif
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if ((ret = i2c_transfer(1, chip<<1, &xaddr[4-alen], alen, buffer, len)) != 0) {
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if (gd->have_console)
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printf( "I2c read: failed %d\n", ret);
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if ((ret = i2c_transfer(read, chip << 1, &xaddr[4 - alen], alen,
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buffer, len)) != 0) {
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if (gd->have_console) {
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printf("I2C %s: failed %d\n",
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read ? "read" : "write", ret);
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}
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return 1;
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}
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return 0;
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}
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int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
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{
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return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 1);
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}
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int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
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{
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uchar xaddr[4];
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if (alen > 4) {
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printf ("I2C write: addr len %d not supported\n", alen);
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return 1;
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}
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if (alen > 0) {
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xaddr[0] = (addr >> 24) & 0xFF;
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xaddr[1] = (addr >> 16) & 0xFF;
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xaddr[2] = (addr >> 8) & 0xFF;
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xaddr[3] = addr & 0xFF;
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}
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#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
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/*
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* EEPROM chips that implement "address overflow" are ones
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* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
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* address and the extra bits end up in the "chip address"
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* bit slots. This makes a 24WC08 (1Kbyte) chip look like
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* four 256 byte chips.
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*
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* Note that we consider the length of the address field to
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* still be one byte because the extra address bits are
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* hidden in the chip address.
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*/
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if (alen > 0)
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chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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#endif
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return (i2c_transfer(0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
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return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 0);
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}
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#if defined(CONFIG_I2C_MULTI_BUS)
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@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2007
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* (C) Copyright 2007-2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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@ -52,22 +52,26 @@
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#define I2C_BASE_ADDR (0xEF600500 + I2C_BUS_OFFS)
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#endif
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#define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR
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#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
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#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
|
||||
#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
|
||||
#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
|
||||
#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
|
||||
#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
|
||||
#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS)
|
||||
#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
|
||||
#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
|
||||
#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
|
||||
#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IIC0_CLKDIV)
|
||||
#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
|
||||
#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
|
||||
#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
|
||||
#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
|
||||
struct ppc4xx_i2c {
|
||||
u8 mdbuf;
|
||||
u8 res1;
|
||||
u8 sdbuf;
|
||||
u8 res2;
|
||||
u8 lmadr;
|
||||
u8 hmadr;
|
||||
u8 cntl;
|
||||
u8 mdcntl;
|
||||
u8 sts;
|
||||
u8 extsts;
|
||||
u8 lsadr;
|
||||
u8 hsadr;
|
||||
u8 clkdiv;
|
||||
u8 intrmsk;
|
||||
u8 xfrcnt;
|
||||
u8 xtcntlss;
|
||||
u8 directcntl;
|
||||
u8 intr;
|
||||
};
|
||||
|
||||
/* MDCNTL Register Bit definition */
|
||||
#define IIC_MDCNTL_HSCL 0x01
|
||||
|
|
|
|||
|
|
@ -565,25 +565,6 @@
|
|||
#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */
|
||||
#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
| IIC Register Offsets
|
||||
'----------------------------------------------------------------------------*/
|
||||
#define IICMDBUF 0x00
|
||||
#define IICSDBUF 0x02
|
||||
#define IICLMADR 0x04
|
||||
#define IICHMADR 0x05
|
||||
#define IICCNTL 0x06
|
||||
#define IICMDCNTL 0x07
|
||||
#define IICSTS 0x08
|
||||
#define IICEXTSTS 0x09
|
||||
#define IICLSADR 0x0A
|
||||
#define IICHSADR 0x0B
|
||||
#define IIC0_CLKDIV 0x0C
|
||||
#define IICINTRMSK 0x0D
|
||||
#define IICXFRCNT 0x0E
|
||||
#define IICXTCNTLSS 0x0F
|
||||
#define IICDIRECTCNTL 0x10
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
| UART Register Offsets
|
||||
'----------------------------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1713,25 +1713,6 @@
|
|||
#define CPR0_PERD_PERDV0_MASK 0x07000000
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
| IIC Register Offsets
|
||||
'----------------------------------------------------------------------------*/
|
||||
#define IICMDBUF 0x00
|
||||
#define IICSDBUF 0x02
|
||||
#define IICLMADR 0x04
|
||||
#define IICHMADR 0x05
|
||||
#define IICCNTL 0x06
|
||||
#define IICMDCNTL 0x07
|
||||
#define IICSTS 0x08
|
||||
#define IICEXTSTS 0x09
|
||||
#define IICLSADR 0x0A
|
||||
#define IICHSADR 0x0B
|
||||
#define IIC0_CLKDIV 0x0C
|
||||
#define IICINTRMSK 0x0D
|
||||
#define IICXFRCNT 0x0E
|
||||
#define IICXTCNTLSS 0x0F
|
||||
#define IICDIRECTCNTL 0x10
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
| PCI Internal Registers et. al. (accessed via plb)
|
||||
+----------------------------------------------------------------------------*/
|
||||
|
|
|
|||
Loading…
Reference in a new issue