Merge tag 'fsl-qoirq-2023-5-5' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq

fsl-ls1088a device tree update
enable DM_SERIAL for ten64
check for crypto node first in fdt_fixup_remove_jr

arch/arm/cpu/armv8/fsl-layerscape/fdt.c

@@ -387,6 +387,10 @@ void fdt_fixup_remove_jr(void *blob)
 	u64 jr_offset, used_jr;
 	fdt32_t *reg;
 
+	/* Return if crypto node not found */
+	if (crypto_node < 0)
+		return;
+
 	used_jr = sec_firmware_used_jobring_offset();
 	fdt_support_default_count_cells(blob, crypto_node, &addr_cells, NULL);
 

arch/arm/dts/fsl-ls1088a-qds-u-boot.dtsi

@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <config.h>
+
+#include "fsl-ls1088a-u-boot.dtsi"
+

arch/arm/dts/fsl-ls1088a-rdb-u-boot.dtsi

@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <config.h>
+
+#include "fsl-ls1088a-u-boot.dtsi"
+

arch/arm/dts/fsl-ls1088a-ten64-u-boot.dtsi

@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <config.h>
+
+#include "fsl-ls1088a-u-boot.dtsi"
+
+/{
+	aliases {
+		spi0 = &qspi;
+	};
+};
+
+&i2c0 {
+	uc: board-controller@7e {
+		compatible = "traverse,ten64-controller";
+		reg = <0x7e>;
+	};
+};
+

arch/arm/dts/fsl-ls1088a-ten64.dts

@@ -1,9 +1,10 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
- * Device Tree file for Travese Ten64 (LS1088) board
+ * Device Tree file for Traverse Technologies Ten64
+ * (LS1088A) board
  * Based on fsl-ls1088a-rdb.dts
  * Copyright 2017-2020 NXP
- * Copyright 2019-2021 Traverse Technologies
+ * Copyright 2019-2023 Traverse Technologies
  *
  * Author: Mathew McBride <matt@traverse.com.au>
  */
@@ -22,7 +23,6 @@
 	aliases {
 		serial0 = &duart0;
 		serial1 = &duart1;
-		spi0 = &qspi;
 	};
 
 	chosen {
@@ -36,18 +36,16 @@
 		 * external power off (e.g ATX Power Button)
 		 * asserted
 		 */
-		powerdn {
+		button-powerdn {
 			label = "External Power Down";
 			gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
-			interrupts = <&gpio1 17 IRQ_TYPE_EDGE_FALLING>;
 			linux,code = <KEY_POWER>;
 		};
 
 		/* Rear Panel 'ADMIN' button (GPIO_H) */
-		admin {
+		button-admin {
 			label = "ADMIN button";
 			gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
-			interrupts = <&gpio3 8 IRQ_TYPE_EDGE_RISING>;
 			linux,code = <KEY_WPS_BUTTON>;
 		};
 	};
@@ -55,17 +53,17 @@
 	leds {
 		compatible = "gpio-leds";
 
-		sfp1down {
+		led-0 {
 			label = "ten64:green:sfp1:down";
 			gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
 		};
 
-		sfp2up {
+		led-1 {
 			label = "ten64:green:sfp2:up";
 			gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
 		};
 
-		admin {
+		led-2 {
 			label = "ten64:admin";
 			gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>;
 		};
@@ -95,17 +93,17 @@
 /* XG1 - Upper SFP */
 &dpmac1 {
 	sfp = <&sfp_xg1>;
+	pcs-handle = <&pcs1>;
 	phy-connection-type = "10gbase-r";
 	managed = "in-band-status";
-	status = "okay";
 };
 
 /* XG0 - Lower SFP */
 &dpmac2 {
 	sfp = <&sfp_xg0>;
+	pcs-handle = <&pcs2>;
 	phy-connection-type = "10gbase-r";
 	managed = "in-band-status";
-	status = "okay";
 };
 
 /* DPMAC3..6 is GE4 to GE8 */
@@ -113,28 +111,28 @@
 	phy-handle = <&mdio1_phy5>;
 	phy-connection-type = "qsgmii";
 	managed = "in-band-status";
-	status = "okay";
+	pcs-handle = <&pcs3_0>;
 };
 
 &dpmac4 {
 	phy-handle = <&mdio1_phy6>;
 	phy-connection-type = "qsgmii";
 	managed = "in-band-status";
-	status = "okay";
+	pcs-handle = <&pcs3_1>;
 };
 
 &dpmac5 {
 	phy-handle = <&mdio1_phy7>;
 	phy-connection-type = "qsgmii";
 	managed = "in-band-status";
-	status = "okay";
+	pcs-handle = <&pcs3_2>;
 };
 
 &dpmac6 {
 	phy-handle = <&mdio1_phy8>;
 	phy-connection-type = "qsgmii";
 	managed = "in-band-status";
-	status = "okay";
+	pcs-handle = <&pcs3_3>;
 };
 
 /* DPMAC7..10 is GE0 to GE3 */
@@ -142,28 +140,28 @@
 	phy-handle = <&mdio1_phy1>;
 	phy-connection-type = "qsgmii";
 	managed = "in-band-status";
-	status = "okay";
+	pcs-handle = <&pcs7_0>;
 };
 
 &dpmac8 {
 	phy-handle = <&mdio1_phy2>;
 	phy-connection-type = "qsgmii";
 	managed = "in-band-status";
-	status = "okay";
+	pcs-handle = <&pcs7_1>;
 };
 
 &dpmac9 {
 	phy-handle = <&mdio1_phy3>;
 	phy-connection-type = "qsgmii";
 	managed = "in-band-status";
-	status = "okay";
+	pcs-handle = <&pcs7_2>;
 };
 
 &dpmac10 {
 	phy-handle = <&mdio1_phy4>;
 	phy-connection-type = "qsgmii";
 	managed = "in-band-status";
-	status = "okay";
+	pcs-handle = <&pcs7_3>;
 };
 
 &duart0 {
@@ -234,11 +232,6 @@
 		compatible = "atmel,at97sc3204t";
 		reg = <0x29>;
 	};
-
-	uc: board-controller@7e {
-		compatible = "traverse,ten64-controller";
-		reg = <0x7e>;
-	};
 };
 
 &i2c2 {
@@ -253,7 +246,7 @@
 &i2c3 {
 	status = "okay";
 
-	i2c-switch@70 {
+	i2c-mux@70 {
 		compatible = "nxp,pca9540";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -273,6 +266,22 @@
 	};
 };
 
+&pcs_mdio1 {
+	status = "okay";
+};
+
+&pcs_mdio2 {
+	status = "okay";
+};
+
+&pcs_mdio3 {
+	status = "okay";
+};
+
+&pcs_mdio7 {
+	status = "okay";
+};
+
 &qspi {
 	status = "okay";
 

arch/arm/dts/fsl-ls1088a-u-boot.dtsi

@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+
+#include <config.h>
+
+/{
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000 0 0x80000000>;
+		      /* DRAM space - 1, size : 2 GB DRAM */
+	};
+};
+
+&duart0 {
+	bootph-all;
+};
+
+&duart1 {
+	bootph-all;
+};
+
+/* MDIO controllers - U-Boot uses a different
+ * driver for the DPAA2 (LS/LX2) family,
+ * so must match fsl,ls-mdio first.
+ */
+&emdio1 {
+	compatible = "fsl,ls-mdio", "fsl,fman-memac-mdio";
+};
+
+&emdio2 {
+	compatible = "fsl,ls-mdio", "fsl,fman-memac-mdio";
+};
+
+/* DPAA2 Management Complex (MC)
+ * "simple-mfd" compatible used by U-Boot only,
+ * to allow driver model functionality.
+ */
+&fsl_mc {
+	compatible = "fsl,qoriq-mc", "simple-mfd";
+
+	dpmacs {
+		compatible = "simple-mfd";
+	};
+};
+
+&pcie1 {
+	status = "okay";
+};
+
+&pcie2 {
+	status = "okay";
+};
+
+&pcie3 {
+	status = "okay";
+};
+
+&usb0 {
+	compatible = "fsl,layerscape-dwc3", "snps,dwc3";
+};
+
+&usb1 {
+	compatible = "fsl,layerscape-dwc3", "snps,dwc3";
+};
+

configs/ten64_tfa_defconfig

@@ -81,7 +81,9 @@ CONFIG_PCIE_LAYERSCAPE_RC=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_RX8025=y
 CONFIG_DM_SCSI=y
-CONFIG_SYS_NS16550_SERIAL=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

drivers/pci/pcie_layerscape_rc.c

@@ -403,6 +403,7 @@ static const struct ls_pcie_drvdata ls1028a_drvdata = {
 static const struct udevice_id ls_pcie_ids[] = {
 	{ .compatible = "fsl,ls-pcie" },
 	{ .compatible = "fsl,ls1028a-pcie", .data = (ulong)&ls1028a_drvdata },
+	{ .compatible = "fsl,ls1088a-pcie", .data = (ulong)&ls1028a_drvdata },
 	{ }
 };