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https://github.com/AsahiLinux/u-boot
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Added I2C support
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
This commit is contained in:
TsiChungLiew
Stefan Roese
parent
99c03c175d
commit
eaf9e447be
2 changed files with 117 additions and 21 deletions
86
include/asm-m68k/fsl_i2c.h
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86
include/asm-m68k/fsl_i2c.h
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/*
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* Freescale I2C Controller
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*
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* Copyright 2006 Freescale Semiconductor, Inc.
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*
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* Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
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* Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
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* and Jeff Brown.
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* Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _ASM_FSL_I2C_H_
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#define _ASM_FSL_I2C_H_
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#include <asm/types.h>
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typedef struct fsl_i2c {
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u8 adr; /* I2C slave address */
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u8 res0[3];
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#define I2C_ADR 0xFE
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#define I2C_ADR_SHIFT 1
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#define I2C_ADR_RES ~(I2C_ADR)
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u8 fdr; /* I2C frequency divider register */
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u8 res1[3];
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#define IC2_FDR 0x3F
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#define IC2_FDR_SHIFT 0
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#define IC2_FDR_RES ~(IC2_FDR)
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u8 cr; /* I2C control redister */
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u8 res2[3];
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#define I2C_CR_MEN 0x80
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#define I2C_CR_MIEN 0x40
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#define I2C_CR_MSTA 0x20
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#define I2C_CR_MTX 0x10
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#define I2C_CR_TXAK 0x08
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#define I2C_CR_RSTA 0x04
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#define I2C_CR_BCST 0x01
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u8 sr; /* I2C status register */
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u8 res3[3];
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#define I2C_SR_MCF 0x80
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#define I2C_SR_MAAS 0x40
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#define I2C_SR_MBB 0x20
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#define I2C_SR_MAL 0x10
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#define I2C_SR_BCSTM 0x08
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#define I2C_SR_SRW 0x04
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#define I2C_SR_MIF 0x02
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#define I2C_SR_RXAK 0x01
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u8 dr; /* I2C data register */
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u8 res4[3];
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#define I2C_DR 0xFF
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#define I2C_DR_SHIFT 0
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#define I2C_DR_RES ~(I2C_DR)
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u8 dfsrr; /* I2C digital filter sampling rate register */
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u8 res5[3];
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#define I2C_DFSRR 0x3F
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#define I2C_DFSRR_SHIFT 0
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#define I2C_DFSRR_RES ~(I2C_DR)
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/* Fill out the reserved block */
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u8 res6[0xE8];
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} fsl_i2c_t;
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#endif /* _ASM_I2C_H_ */
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@ -52,6 +52,7 @@
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CFG_CMD_DATE | \
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CFG_CMD_ELF | \
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CFG_CMD_FLASH | \
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CFG_CMD_I2C | \
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(CFG_CMD_LOADB | CFG_CMD_LOADS) | \
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CFG_CMD_MEMORY | \
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CFG_CMD_MISC | \
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@ -65,15 +66,15 @@
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#define CONFIG_MCFFEC
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#ifdef CONFIG_MCFFEC
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# define CONFIG_NET_MULTI 1
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# define CONFIG_NET_MULTI 1
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# define CONFIG_MII 1
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# define CFG_DISCOVER_PHY
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# define CFG_RX_ETH_BUFFER 8
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# define CFG_FAULT_ECHO_LINK_DOWN
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# define CFG_FEC0_PINMUX 0
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# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
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# define MCFFEC_TOUT_LOOP 50000
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# define CFG_FEC0_PINMUX 0
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# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
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# define MCFFEC_TOUT_LOOP 50000
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/* If CFG_DISCOVER_PHY is not defined - hardcoded */
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# ifndef CFG_DISCOVER_PHY
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# define FECDUPLEX FULL
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@ -92,14 +93,23 @@
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#define CONFIG_MCFTMR
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#undef CONFIG_MCFPIT
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/* I2C */
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#define CONFIG_FSL_I2C
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#define CONFIG_HARD_I2C /* I2C with hw support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 80000
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_OFFSET 0x58000
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#define CFG_IMMR CFG_MBAR
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
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#ifdef CONFIG_MCFFEC
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# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
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# define CONFIG_IPADDR 192.162.1.2
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# define CONFIG_NETMASK 255.255.255.0
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# define CONFIG_SERVERIP 192.162.1.1
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# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
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# define CONFIG_IPADDR 192.162.1.2
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# define CONFIG_NETMASK 255.255.255.0
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# define CONFIG_SERVERIP 192.162.1.1
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# define CONFIG_GATEWAYIP 192.162.1.1
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# define CONFIG_OVERWRITE_ETHADDR_ONCE
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#endif /* FEC_ENET */
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@ -117,26 +127,26 @@
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"save\0" \
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""
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#define CONFIG_PRAM 512 /* 512 KB */
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#define CFG_PROMPT "-> "
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#define CONFIG_PRAM 512 /* 512 KB */
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#define CFG_PROMPT "-> "
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#define CFG_LONGHELP /* undef to save memory */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_LOAD_ADDR 0x40010000
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#define CFG_HZ 1000
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#define CFG_CLK 80000000
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#define CFG_CPU_CLK CFG_CLK * 3
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#define CFG_HZ 1000
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#define CFG_CLK 80000000
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#define CFG_CPU_CLK CFG_CLK * 3
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#define CFG_MBAR 0xFC000000
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#define CFG_MBAR 0xFC000000
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/*
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* Low Level Configuration Settings
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@ -190,13 +200,13 @@
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# define CFG_FLASH_CFI_DRIVER 1
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# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
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# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
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# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
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# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
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#endif
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#define CFG_FLASH_BASE 0
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#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
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#define CFG_FLASH_BASE 0
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#define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
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/* Configuration for environment
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* Environment is embedded in u-boot in the second sector of the flash
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