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Merge patch series "ARM: renesas: Rename R-Mobile to Renesas"

Browse source 
Marek Vasut <marek.vasut+renesas@mailbox.org> says:

Rename R-Mobile to Renesas all over the place because the chips are
made by Renesas, while only a subset of them is from the R-Mobile line.
This commit is contained in:
Tom Rini 2024-03-02 14:30:25 -05:00
commit eac52e4be4
147 changed files with 439 additions and 4355 deletions
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2
MAINTAINERS
View file

@ -497,7 +497,7 @@ M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
M: Marek Vasut <marek.vasut+renesas@mailbox.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-sh.git
F: arch/arm/mach-rmobile/
F: arch/arm/mach-renesas/
F: drivers/clk/renesas/
F: drivers/gpio/gpio-rcar.c
F: drivers/i2c/rcar_*

2
Makefile
View file

@ -1266,7 +1266,7 @@ spl/u-boot-spl.srec: spl/u-boot-spl FORCE
$(call if_changed,objcopy)
%.scif: %.srec
$(Q)$(MAKE) $(build)=arch/arm/mach-rmobile $@
$(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@
OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \

4
arch/arm/Kconfig
View file

@ -1071,7 +1071,7 @@ config ARCH_QEMU
imply USB_KEYBOARD
imply CMD_USB
config ARCH_RMOBILE
config ARCH_RENESAS
bool "Renesas ARM SoCs"
select DM
select DM_SERIAL
@ -2269,7 +2269,7 @@ source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/mach-owl/Kconfig"
source "arch/arm/mach-rmobile/Kconfig"
source "arch/arm/mach-renesas/Kconfig"
source "arch/arm/mach-meson/Kconfig"

2
arch/arm/Makefile
View file

@ -75,7 +75,7 @@ machine-$(CONFIG_ARCH_NPCM) += npcm
machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
machine-$(CONFIG_ARCH_ORION5X) += orion5x
machine-$(CONFIG_ARCH_OWL) += owl
machine-$(CONFIG_ARCH_RMOBILE) += rmobile
machine-$(CONFIG_ARCH_RENESAS) += renesas
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon

14
arch/arm/mach-rmobile/Kconfig → arch/arm/mach-renesas/Kconfig
View file

@ -1,4 +1,4 @@
if ARCH_RMOBILE
if ARCH_RENESAS
# Renesas ARM SoCs R-Car Gen3/Gen4 (64bit)
config RCAR_64
@ -89,12 +89,12 @@ config RZG2L
endchoice
config SYS_SOC
default "rmobile" if ARCH_RMOBILE
default "renesas" if ARCH_RENESAS
source "arch/arm/mach-rmobile/Kconfig.32"
source "arch/arm/mach-rmobile/Kconfig.64"
source "arch/arm/mach-rmobile/Kconfig.rza1"
source "arch/arm/mach-rmobile/Kconfig.rzn1"
source "arch/arm/mach-rmobile/Kconfig.rzg2l"
source "arch/arm/mach-renesas/Kconfig.32"
source "arch/arm/mach-renesas/Kconfig.64"
source "arch/arm/mach-renesas/Kconfig.rza1"
source "arch/arm/mach-renesas/Kconfig.rzn1"
source "arch/arm/mach-renesas/Kconfig.rzg2l"
endif

7
arch/arm/mach-rmobile/Kconfig.32 → arch/arm/mach-renesas/Kconfig.32
View file

@ -1,6 +1,6 @@
if RCAR_32
config ARCH_RMOBILE_BOARD_STRING
config ARCH_RENESAS_BOARD_STRING
string "Renesas RCar Gen2 board name"
default "Board"
@ -10,9 +10,6 @@ config RCAR_GEN2
select PHY_RCAR_GEN2
select TMU_TIMER
config R8A7740
bool "Renesas SoC R8A7740"
config R8A7790
bool "Renesas SoC R8A7790"
select RCAR_GEN2
@ -125,7 +122,7 @@ endchoice
config TMU_TIMER
bool
config RMOBILE_EXTRAM_BOOT
config RENESAS_EXTRAM_BOOT
bool "Enable boot from RAM"
depends on TARGET_ALT || TARGET_BLANCHE || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT

4
arch/arm/mach-rmobile/Kconfig.64 → arch/arm/mach-renesas/Kconfig.64
View file

@ -6,7 +6,7 @@ config SYS_MALLOC_F_LEN
config OF_LIBFDT_OVERLAY
default y if RCAR_64
source "arch/arm/mach-rmobile/Kconfig.rcar3"
source "arch/arm/mach-rmobile/Kconfig.rcar4"
source "arch/arm/mach-renesas/Kconfig.rcar3"
source "arch/arm/mach-renesas/Kconfig.rcar4"
endif

0
arch/arm/mach-rmobile/Kconfig.rcar3 → arch/arm/mach-renesas/Kconfig.rcar3
View file

0
arch/arm/mach-rmobile/Kconfig.rcar4 → arch/arm/mach-renesas/Kconfig.rcar4
View file

0
arch/arm/mach-rmobile/Kconfig.rza1 → arch/arm/mach-renesas/Kconfig.rza1
View file

0
arch/arm/mach-rmobile/Kconfig.rzg2l → arch/arm/mach-renesas/Kconfig.rzg2l
View file

0
arch/arm/mach-rmobile/Kconfig.rzn1 → arch/arm/mach-renesas/Kconfig.rzn1
View file

1
arch/arm/mach-rmobile/Makefile → arch/arm/mach-renesas/Makefile
View file

@ -8,7 +8,6 @@ obj-y += emac.o
obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o
obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o memmap-gen3.o

4
arch/arm/mach-rmobile/board.c → arch/arm/mach-renesas/board.c
View file

@ -7,10 +7,10 @@
#include <init.h>
#include <asm/io.h>
#ifdef CONFIG_ARCH_RMOBILE_BOARD_STRING
#ifdef CONFIG_ARCH_RENESAS_BOARD_STRING
int checkboard(void)
{
printf("Board: %s\n", CONFIG_ARCH_RMOBILE_BOARD_STRING);
printf("Board: %s\n", CONFIG_ARCH_RENESAS_BOARD_STRING);
return 0;
}
#endif

16
arch/arm/mach-rmobile/cpu_info-rcar.c → arch/arm/mach-renesas/cpu_info-rcar.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
* arch/arm/mach-renesas/cpu_info-rcar.c
*
* Copyright (C) 2013,2014 Renesas Electronics Corporation
*/
@ -13,7 +13,7 @@
#define R8A7796_REV_1_3 0x5211
#define R8A77995_REV_1_1 0x5810
static u32 rmobile_get_prr(void)
static u32 renesas_get_prr(void)
{
if (IS_ENABLED(CONFIG_RCAR_64))
return readl(0xFFF00044);
@ -21,14 +21,14 @@ static u32 rmobile_get_prr(void)
return readl(0xFF000044);
}
u32 rmobile_get_cpu_type(void)
u32 renesas_get_cpu_type(void)
{
return (rmobile_get_prr() & 0x00007F00) >> 8;
return (renesas_get_prr() & 0x00007F00) >> 8;
}
u32 rmobile_get_cpu_rev_integer(void)
u32 renesas_get_cpu_rev_integer(void)
{
const u32 prr = rmobile_get_prr();
const u32 prr = renesas_get_prr();
const u32 rev = prr & PRR_MASK;
if (rev == R8A7796_REV_1_1 || rev == R8A7796_REV_1_3 ||
@ -38,9 +38,9 @@ u32 rmobile_get_cpu_rev_integer(void)
return ((prr & 0x000000F0) >> 4) + 1;
}
u32 rmobile_get_cpu_rev_fraction(void)
u32 renesas_get_cpu_rev_fraction(void)
{
const u32 prr = rmobile_get_prr();
const u32 prr = renesas_get_prr();
const u32 rev = prr & PRR_MASK;
if (rev == R8A7796_REV_1_1 || rev == R8A77995_REV_1_1)

0
arch/arm/mach-rmobile/cpu_info-rzg.c → arch/arm/mach-renesas/cpu_info-rzg.c
View file

10
arch/arm/mach-rmobile/cpu_info-rzg2l.c → arch/arm/mach-renesas/cpu_info-rzg2l.c
View file

@ -4,7 +4,7 @@
*
*/
#include <mach/rmobile.h>
#include <mach/renesas.h>
#include <asm/io.h>
#include <linux/libfdt.h>
@ -21,7 +21,7 @@ struct tfa_info {
};
static const struct tfa_info tfa_info[] = {
{ "renesas,r9a07g044l2", "R9A07G044L", RMOBILE_CPU_TYPE_R9A07G044L },
{ "renesas,r9a07g044l2", "R9A07G044L", RENESAS_CPU_TYPE_R9A07G044L },
};
static const struct tfa_info invalid_tfa_info = { NULL, "(invalid)", 0 };
@ -47,17 +47,17 @@ const u8 *rzg_get_cpu_name(void)
return get_tfa_info()->cpu_name;
}
u32 rmobile_get_cpu_type(void)
u32 renesas_get_cpu_type(void)
{
return get_tfa_info()->cpu_type;
}
u32 rmobile_get_cpu_rev_integer(void)
u32 renesas_get_cpu_rev_integer(void)
{
return (readl(SYSC_LSI_DEVID) >> 28) + 1;
}
u32 rmobile_get_cpu_rev_fraction(void)
u32 renesas_get_cpu_rev_fraction(void)
{
return 0;
}

144
arch/arm/mach-renesas/cpu_info.c Normal file
View file

@ -0,0 +1,144 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012-2021 Renesas Solutions Corp.
*/
#include <cpu_func.h>
#include <asm/cache.h>
#include <init.h>
#include <asm/io.h>
#include <env.h>
#include <linux/ctype.h>
#ifdef CONFIG_ARCH_CPU_INIT
int arch_cpu_init(void)
{
icache_enable();
return 0;
}
#endif
/* R-Car Gen3 and Gen4 D-cache is enabled in memmap-gen3.c */
#ifndef CONFIG_RCAR_64
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
dcache_enable();
}
#endif
#endif
#ifdef CONFIG_DISPLAY_CPUINFO
#if !defined(CONFIG_RZA1) && !defined(CONFIG_RZN1)
__weak const u8 *rzg_get_cpu_name(void)
{
return 0;
}
__weak u32 renesas_get_cpu_type(void)
{
return 0x0;
}
__weak u32 renesas_get_cpu_rev_integer(void)
{
return 0;
}
__weak u32 renesas_get_cpu_rev_fraction(void)
{
return 0;
}
/* CPU information table */
static const struct {
u16 cpu_type;
u8 cpu_name[10];
} renesas_cpuinfo[] = {
{ RENESAS_CPU_TYPE_R8A7790, "R8A7790" },
{ RENESAS_CPU_TYPE_R8A7791, "R8A7791" },
{ RENESAS_CPU_TYPE_R8A7792, "R8A7792" },
{ RENESAS_CPU_TYPE_R8A7793, "R8A7793" },
{ RENESAS_CPU_TYPE_R8A7794, "R8A7794" },
{ RENESAS_CPU_TYPE_R8A7795, "R8A7795" },
{ RENESAS_CPU_TYPE_R8A7796, "R8A7796" },
{ RENESAS_CPU_TYPE_R8A77965, "R8A77965" },
{ RENESAS_CPU_TYPE_R8A77970, "R8A77970" },
{ RENESAS_CPU_TYPE_R8A77980, "R8A77980" },
{ RENESAS_CPU_TYPE_R8A77990, "R8A77990" },
{ RENESAS_CPU_TYPE_R8A77995, "R8A77995" },
{ RENESAS_CPU_TYPE_R8A779A0, "R8A779A0" },
{ RENESAS_CPU_TYPE_R8A779F0, "R8A779F0" },
{ RENESAS_CPU_TYPE_R8A779G0, "R8A779G0" },
{ RENESAS_CPU_TYPE_R8A779H0, "R8A779H0" },
{ 0x0, "CPU" },
};
static int renesas_cpuinfo_idx(void)
{
u32 cpu_type = renesas_get_cpu_type();
int i;
for (i = 0; i < ARRAY_SIZE(renesas_cpuinfo) - 1; i++)
if (renesas_cpuinfo[i].cpu_type == cpu_type)
return i;
/* Unknown "CPU" entry */
return ARRAY_SIZE(renesas_cpuinfo) - 1;
}
static const u8 *get_cpu_name(int idx)
{
const u8 *cpu_name = rzg_get_cpu_name();
return cpu_name ? cpu_name : renesas_cpuinfo[idx].cpu_name;
}
#ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
{
int i, idx = renesas_cpuinfo_idx();
const u8 *cpu_name = get_cpu_name(idx);
char cpu[10] = { 0 };
for (i = 0; i < sizeof(cpu); i++)
cpu[i] = tolower(cpu_name[i]);
env_set("platform", cpu);
return 0;
}
#endif
int print_cpuinfo(void)
{
int i = renesas_cpuinfo_idx();
if (renesas_cpuinfo[i].cpu_type == RENESAS_CPU_TYPE_R8A7796 &&
renesas_get_cpu_rev_integer() == 1 &&
renesas_get_cpu_rev_fraction() == 1) {
printf("CPU: Renesas Electronics %s rev 1.1/1.2\n", get_cpu_name(i));
return 0;
}
printf("CPU: Renesas Electronics %s rev %d.%d\n",
get_cpu_name(i), renesas_get_cpu_rev_integer(),
renesas_get_cpu_rev_fraction());
return 0;
}
#elif defined(CONFIG_RZA1)
int print_cpuinfo(void)
{
printf("CPU: Renesas Electronics RZ/A1\n");
return 0;
}
#else /* CONFIG_RZN1 */
int print_cpuinfo(void)
{
printf("CPU: Renesas Electronics RZ/N1\n");
return 0;
}
#endif
#endif /* CONFIG_DISPLAY_CPUINFO */

2
arch/arm/mach-rmobile/emac.c → arch/arm/mach-renesas/emac.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* RMOBILE EtherMAC initialization.
* Renesas EtherMAC initialization.
*
* Copyright (C) 2012 Renesas Solutions Corp.
* Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>

0
arch/arm/mach-rmobile/include/mach/boot0.h → arch/arm/mach-renesas/include/mach/boot0.h
View file

4
arch/arm/mach-renesas/include/mach/gpio.h Normal file
View file

@ -0,0 +1,4 @@
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H
#endif /* __ASM_ARCH_GPIO_H */

0
arch/arm/mach-rmobile/include/mach/irqs.h → arch/arm/mach-renesas/include/mach/irqs.h
View file

4
arch/arm/mach-rmobile/include/mach/r8a7790.h → arch/arm/mach-renesas/include/mach/r8a7790.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/include/asm/arch-rmobile/r8a7790.h
* arch/arm/include/asm/arch-renesas/r8a7790.h
*
* Copyright (C) 2013,2014 Renesas Electronics Corporation
*/
@ -28,6 +28,6 @@
#define R8A7790_CUT_ES2X 2
#define IS_R8A7790_ES2() \
(rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
(renesas_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
#endif /* __ASM_ARCH_R8A7790_H */

4
arch/arm/mach-rmobile/include/mach/r8a7791.h → arch/arm/mach-renesas/include/mach/r8a7791.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/include/asm/arch-rmobile/r8a7791.h
* arch/arm/include/asm/arch-renesas/r8a7791.h
*
* Copyright (C) 2013,2014 Renesas Electronics Corporation
*/
@ -65,6 +65,6 @@
#define R8A7791_CUT_ES2X 2
#define IS_R8A7791_ES2() \
(rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
(renesas_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
#endif /* __ASM_ARCH_R8A7791_H */

2
arch/arm/mach-rmobile/include/mach/r8a7792.h → arch/arm/mach-renesas/include/mach/r8a7792.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/include/asm/arch-rmobile/r8a7792.h
* arch/arm/include/asm/arch-renesas/r8a7792.h
*
* Copyright (C) 2016 Renesas Electronics Corporation
*/

4
arch/arm/mach-rmobile/include/mach/r8a7793.h → arch/arm/mach-renesas/include/mach/r8a7793.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/include/asm/arch-rmobile/r8a7793.h
* arch/arm/include/asm/arch-renesas/r8a7793.h
*
* Copyright (C) 2014 Renesas Electronics Corporation
*/
@ -71,6 +71,6 @@
#define R8A7793_CUT_ES2X 2
#define IS_R8A7793_ES2() \
(rmobile_get_cpu_rev_integer() == R8A7793_CUT_ES2X)
(renesas_get_cpu_rev_integer() == R8A7793_CUT_ES2X)
#endif /* __ASM_ARCH_R8A7793_H */

4
arch/arm/mach-rmobile/include/mach/r8a7794.h → arch/arm/mach-renesas/include/mach/r8a7794.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/include/asm/arch-rmobile/r8a7794.h
* arch/arm/include/asm/arch-renesas/r8a7794.h
*
* Copyright (C) 2014 Renesas Electronics Corporation
*/
@ -28,6 +28,6 @@
#define R8A7794_CUT_ES2 2
#define IS_R8A7794_ES2() \
(rmobile_get_cpu_rev_integer() == R8A7794_CUT_ES2)
(renesas_get_cpu_rev_integer() == R8A7794_CUT_ES2)
#endif /* __ASM_ARCH_R8A7794_H */

2
arch/arm/mach-rmobile/include/mach/rcar-base.h → arch/arm/mach-renesas/include/mach/rcar-base.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/include/asm/arch-rmobile/rcar-base.h
* arch/arm/include/asm/arch-renesas/rcar-base.h
*
* Copyright (C) 2013,2014 Renesas Electronics Corporation
*/

2
arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h → arch/arm/mach-renesas/include/mach/rcar-gen3-base.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* ./arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
* ./arch/arm/mach-renesas/include/mach/rcar-gen3-base.h
*
* Copyright (C) 2015 Renesas Electronics Corporation
*/

2
arch/arm/mach-rmobile/include/mach/rcar-gen4-base.h → arch/arm/mach-renesas/include/mach/rcar-gen4-base.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* ./arch/arm/mach-rmobile/include/mach/rcar-gen4-base.h
* ./arch/arm/mach-renesas/include/mach/rcar-gen4-base.h
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/

2
arch/arm/mach-rmobile/include/mach/rcar-mstp.h → arch/arm/mach-renesas/include/mach/rcar-mstp.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/include/asm/arch-rmobile/rcar-mstp.h
* arch/arm/include/asm/arch-renesas/rcar-mstp.h
*
* Copyright (C) 2013, 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* Copyright (C) 2013, 2014 Renesas Electronics Corporation

56
arch/arm/mach-renesas/include/mach/renesas.h Normal file
View file

@ -0,0 +1,56 @@
#ifndef __ASM_ARCH_RENESAS_H
#define __ASM_ARCH_RENESAS_H
#if defined(CONFIG_ARCH_RENESAS)
#if defined(CONFIG_R8A7790)
#include <asm/arch/r8a7790.h>
#elif defined(CONFIG_R8A7791)
#include <asm/arch/r8a7791.h>
#elif defined(CONFIG_R8A7792)
#include <asm/arch/r8a7792.h>
#elif defined(CONFIG_R8A7793)
#include <asm/arch/r8a7793.h>
#elif defined(CONFIG_R8A7794)
#include <asm/arch/r8a7794.h>
#elif defined(CONFIG_RCAR_GEN3)
#include <asm/arch/rcar-gen3-base.h>
#elif defined(CONFIG_RCAR_GEN4)
#include <asm/arch/rcar-gen4-base.h>
#elif defined(CONFIG_R7S72100)
#elif defined(CONFIG_RZG2L)
#include <asm/arch/rzg2l.h>
#else
#error "SOC Name not defined"
#endif
#endif /* CONFIG_ARCH_RENESAS */
/* PRR CPU IDs */
#define RENESAS_CPU_TYPE_R8A7740 0x40
#define RENESAS_CPU_TYPE_R8A7790 0x45
#define RENESAS_CPU_TYPE_R8A7791 0x47
#define RENESAS_CPU_TYPE_R8A7792 0x4A
#define RENESAS_CPU_TYPE_R8A7793 0x4B
#define RENESAS_CPU_TYPE_R8A7794 0x4C
#define RENESAS_CPU_TYPE_R8A7795 0x4F
#define RENESAS_CPU_TYPE_R8A7796 0x52
#define RENESAS_CPU_TYPE_R8A77965 0x55
#define RENESAS_CPU_TYPE_R8A77970 0x54
#define RENESAS_CPU_TYPE_R8A77980 0x56
#define RENESAS_CPU_TYPE_R8A77990 0x57
#define RENESAS_CPU_TYPE_R8A77995 0x58
#define RENESAS_CPU_TYPE_R8A779A0 0x59
#define RENESAS_CPU_TYPE_R8A779F0 0x5A
#define RENESAS_CPU_TYPE_R8A779G0 0x5C
#define RENESAS_CPU_TYPE_R8A779H0 0x5D
#define RENESAS_CPU_TYPE_R9A07G044L 0x9A070440
#ifndef __ASSEMBLY__
#include <asm/types.h>
const u8 *rzg_get_cpu_name(void);
u32 renesas_get_cpu_type(void);
u32 renesas_get_cpu_rev_integer(void);
u32 renesas_get_cpu_rev_fraction(void);
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_RENESAS_H */

0
arch/arm/mach-rmobile/include/mach/rzg2l.h → arch/arm/mach-renesas/include/mach/rzg2l.h
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0
arch/arm/mach-rmobile/include/mach/sys_proto.h → arch/arm/mach-renesas/include/mach/sys_proto.h
View file

2
arch/arm/mach-rmobile/lowlevel_init_ca15.S → arch/arm/mach-renesas/lowlevel_init_ca15.S
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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
* arch/arm/mach-renesas/lowlevel_init_ca15.S
* This file is lager low level initialize.
*
* Copyright (C) 2013, 2014 Renesas Electronics Corporation

0
arch/arm/mach-rmobile/lowlevel_init_gen3.S → arch/arm/mach-renesas/lowlevel_init_gen3.S
View file

0
arch/arm/mach-rmobile/memmap-gen3.c → arch/arm/mach-renesas/memmap-gen3.c
View file

0
arch/arm/mach-rmobile/memmap-rzg2l.c → arch/arm/mach-renesas/memmap-rzg2l.c
View file

0
arch/arm/mach-rmobile/psci-r8a779a0.c → arch/arm/mach-renesas/psci-r8a779a0.c
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31
arch/arm/mach-rmobile/cpu_info-r8a7740.c
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@ -1,31 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012 Renesas Solutions Corp.
*/
#include <asm/io.h>
u32 rmobile_get_cpu_type(void)
{
u32 id;
u32 type;
struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE;
id = readl(hpb->cccr);
type = (id >> 8) & 0xFF;
return type;
}
u32 rmobile_get_cpu_rev(void)
{
u32 id;
u32 rev;
struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE;
id = readl(hpb->cccr);
rev = (id >> 4) & 0xF;
return rev;
}

151
arch/arm/mach-rmobile/cpu_info.c
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@ -1,151 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* (C) Copyright 2012-2021 Renesas Solutions Corp.
*/
#include <cpu_func.h>
#include <asm/cache.h>
#include <init.h>
#include <asm/io.h>
#include <env.h>
#include <linux/ctype.h>
#ifdef CONFIG_ARCH_CPU_INIT
int arch_cpu_init(void)
{
icache_enable();
return 0;
}
#endif
/* R-Car Gen3 and Gen4 D-cache is enabled in memmap-gen3.c */
#ifndef CONFIG_RCAR_64
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
dcache_enable();
}
#endif
#endif
#ifdef CONFIG_DISPLAY_CPUINFO
#if !defined(CONFIG_RZA1) && !defined(CONFIG_RZN1)
__weak const u8 *rzg_get_cpu_name(void)
{
return 0;
}
static u32 __rmobile_get_cpu_type(void)
{
return 0x0;
}
u32 rmobile_get_cpu_type(void)
__attribute__((weak, alias("__rmobile_get_cpu_type")));
static u32 __rmobile_get_cpu_rev_integer(void)
{
return 0;
}
u32 rmobile_get_cpu_rev_integer(void)
__attribute__((weak, alias("__rmobile_get_cpu_rev_integer")));
static u32 __rmobile_get_cpu_rev_fraction(void)
{
return 0;
}
u32 rmobile_get_cpu_rev_fraction(void)
__attribute__((weak, alias("__rmobile_get_cpu_rev_fraction")));
/* CPU information table */
static const struct {
u16 cpu_type;
u8 cpu_name[10];
} rmobile_cpuinfo[] = {
{ RMOBILE_CPU_TYPE_R8A7740, "R8A7740" },
{ RMOBILE_CPU_TYPE_R8A7790, "R8A7790" },
{ RMOBILE_CPU_TYPE_R8A7791, "R8A7791" },
{ RMOBILE_CPU_TYPE_R8A7792, "R8A7792" },
{ RMOBILE_CPU_TYPE_R8A7793, "R8A7793" },
{ RMOBILE_CPU_TYPE_R8A7794, "R8A7794" },
{ RMOBILE_CPU_TYPE_R8A7795, "R8A7795" },
{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
{ RMOBILE_CPU_TYPE_R8A77965, "R8A77965" },
{ RMOBILE_CPU_TYPE_R8A77970, "R8A77970" },
{ RMOBILE_CPU_TYPE_R8A77980, "R8A77980" },
{ RMOBILE_CPU_TYPE_R8A77990, "R8A77990" },
{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
{ RMOBILE_CPU_TYPE_R8A779A0, "R8A779A0" },
{ RMOBILE_CPU_TYPE_R8A779F0, "R8A779F0" },
{ RMOBILE_CPU_TYPE_R8A779G0, "R8A779G0" },
{ RMOBILE_CPU_TYPE_R8A779H0, "R8A779H0" },
{ 0x0, "CPU" },
};
static int rmobile_cpuinfo_idx(void)
{
u32 cpu_type = rmobile_get_cpu_type();
int i;
for (i = 0; i < ARRAY_SIZE(rmobile_cpuinfo) - 1; i++)
if (rmobile_cpuinfo[i].cpu_type == cpu_type)
return i;
/* Unknown "CPU" entry */
return ARRAY_SIZE(rmobile_cpuinfo) - 1;
}
static const u8 *get_cpu_name(int idx)
{
const u8 *cpu_name = rzg_get_cpu_name();
return cpu_name ? cpu_name : rmobile_cpuinfo[idx].cpu_name;
}
#ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
{
int i, idx = rmobile_cpuinfo_idx();
const u8 *cpu_name = get_cpu_name(idx);
char cpu[10] = { 0 };
for (i = 0; i < sizeof(cpu); i++)
cpu[i] = tolower(cpu_name[i]);
env_set("platform", cpu);
return 0;
}
#endif
int print_cpuinfo(void)
{
int i = rmobile_cpuinfo_idx();
if (rmobile_cpuinfo[i].cpu_type == RMOBILE_CPU_TYPE_R8A7796 &&
rmobile_get_cpu_rev_integer() == 1 &&
rmobile_get_cpu_rev_fraction() == 1) {
printf("CPU: Renesas Electronics %s rev 1.1/1.2\n", get_cpu_name(i));
return 0;
}
printf("CPU: Renesas Electronics %s rev %d.%d\n",
get_cpu_name(i), rmobile_get_cpu_rev_integer(),
rmobile_get_cpu_rev_fraction());
return 0;
}
#elif defined(CONFIG_RZA1)
int print_cpuinfo(void)
{
printf("CPU: Renesas Electronics RZ/A1\n");
return 0;
}
#else /* CONFIG_RZN1 */
int print_cpuinfo(void)
{
printf("CPU: Renesas Electronics RZ/N1\n");
return 0;
}
#endif
#endif /* CONFIG_DISPLAY_CPUINFO */

9
arch/arm/mach-rmobile/include/mach/gpio.h
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@ -1,9 +0,0 @@
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H
#if defined(CONFIG_R8A7740)
#include "r8a7740-gpio.h"
void r8a7740_pinmux_init(void);
#endif
#endif /* __ASM_ARCH_GPIO_H */

13
arch/arm/mach-rmobile/include/mach/mmc.h
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@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Renesas SuperH MMCIF driver.
*
* Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* Copyright (C) 2014 Renesas Electronics Corporation
*/
#ifndef _RMOBILE_MMC_H_
#define _RMOBILE_MMC_H_
int mmcif_mmc_init(void);
#endif /* _RMOBILE_MMC_H_ */

572
arch/arm/mach-rmobile/include/mach/r8a7740-gpio.h
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@ -1,572 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2011 Renesas Solutions Corp.
* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*/
#ifndef __ASM_R8A7740_H__
#define __ASM_R8A7740_H__
/*
* MD_CKx pin
*/
#define MD_CK2 (1 << 2)
#define MD_CK1 (1 << 1)
#define MD_CK0 (1 << 0)
/*
* Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function
* GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
*/
enum {
/* PORT */
GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
GPIO_PORT210, GPIO_PORT211,
/* IRQ */
GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13,
GPIO_FN_IRQ1,
GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12,
GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14,
GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172,
GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1,
GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173,
GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209,
GPIO_FN_IRQ8,
GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210,
GPIO_FN_IRQ10,
GPIO_FN_IRQ11,
GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97,
GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98,
GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99,
GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100,
GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211,
GPIO_FN_IRQ17,
GPIO_FN_IRQ18,
GPIO_FN_IRQ19,
GPIO_FN_IRQ20,
GPIO_FN_IRQ21,
GPIO_FN_IRQ22,
GPIO_FN_IRQ23,
GPIO_FN_IRQ24,
GPIO_FN_IRQ25,
GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81,
GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168,
GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169,
GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170,
GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171,
GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167,
/* Function */
/* DBGT */
GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0,
GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20,
GPIO_FN_DBGMD21,
/* FSI */
GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */
GPIO_FN_FSIAISLD_PORT5,
GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */
GPIO_FN_FSIASPDIF_PORT18,
GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2,
GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT,
GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC,
GPIO_FN_FSIACK, GPIO_FN_FSIAILR,
GPIO_FN_FSIAIBT,
/* FMSI */
GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
GPIO_FN_FMSISLD_PORT6,
GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT,
GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT,
GPIO_FN_FMSICK, GPIO_FN_FMSOILR,
GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR,
GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD,
GPIO_FN_FMSOCK,
/* SCIFA0 */
GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS,
GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD,
GPIO_FN_SCIFA0_TXD,
/* SCIFA1 */
GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK,
GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD,
GPIO_FN_SCIFA1_RTS,
/* SCIFA2 */
GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
GPIO_FN_SCIFA2_SCK_PORT199,
GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD,
GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS,
/* SCIFA3 */
GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
GPIO_FN_SCIFA3_SCK_PORT116,
GPIO_FN_SCIFA3_CTS_PORT117,
GPIO_FN_SCIFA3_RXD_PORT174,
GPIO_FN_SCIFA3_TXD_PORT175,
GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
GPIO_FN_SCIFA3_SCK_PORT158,
GPIO_FN_SCIFA3_CTS_PORT162,
GPIO_FN_SCIFA3_RXD_PORT159,
GPIO_FN_SCIFA3_TXD_PORT160,
/* SCIFA4 */
GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
GPIO_FN_SCIFA4_TXD_PORT13,
GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
GPIO_FN_SCIFA4_TXD_PORT203,
GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
GPIO_FN_SCIFA4_TXD_PORT93,
GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
GPIO_FN_SCIFA4_SCK_PORT205,
/* SCIFA5 */
GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
GPIO_FN_SCIFA5_RXD_PORT10,
GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
GPIO_FN_SCIFA5_TXD_PORT208,
GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
GPIO_FN_SCIFA5_RXD_PORT92,
GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
GPIO_FN_SCIFA5_SCK_PORT206,
/* SCIFA6 */
GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD,
/* SCIFA7 */
GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD,
/* SCIFAB */
GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
GPIO_FN_SCIFB_RXD_PORT191,
GPIO_FN_SCIFB_TXD_PORT192,
GPIO_FN_SCIFB_RTS_PORT186,
GPIO_FN_SCIFB_CTS_PORT187,
GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
GPIO_FN_SCIFB_RXD_PORT3,
GPIO_FN_SCIFB_TXD_PORT4,
GPIO_FN_SCIFB_RTS_PORT172,
GPIO_FN_SCIFB_CTS_PORT173,
/* LCD0 */
GPIO_FN_LCDC0_SELECT,
GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2,
GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5,
GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8,
GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11,
GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14,
GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17,
GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC,
GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */
GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */
GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */
GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */
GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162,
GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158,
GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159,
GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */
GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4,
GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2,
GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1,
GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */
/* LCD1 */
GPIO_FN_LCDC1_SELECT,
GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2,
GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5,
GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8,
GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11,
GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14,
GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17,
GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20,
GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23,
GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC,
GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC,
GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */
GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */
GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */
GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */
/* RSPI */
GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A,
GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A,
GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A,
GPIO_FN_RSPI_CK_A,
/* VIO CKO */
GPIO_FN_VIO_CKO1,
GPIO_FN_VIO_CKO2,
GPIO_FN_VIO_CKO_1,
GPIO_FN_VIO_CKO,
/* VIO0 */
GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2,
GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5,
GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8,
GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11,
GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD,
GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD,
GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
GPIO_FN_VIO0_D14_PORT25,
GPIO_FN_VIO0_D15_PORT24,
GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
GPIO_FN_VIO0_D14_PORT95,
GPIO_FN_VIO0_D15_PORT96,
/* VIO1 */
GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2,
GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5,
GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD,
GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD,
/* TPU0 */
GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1,
GPIO_FN_TPU0TO3,
GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
GPIO_FN_TPU0TO2_PORT202,
/* SSP1 0 */
GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2,
GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5,
GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN,
GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC,
/* SSP1 1 */
GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3,
GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6,
GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC,
GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
GPIO_FN_STP1_IPEN_PORT187,
GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
GPIO_FN_STP1_IPEN_PORT193,
/* SIM */
GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK,
GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */
GPIO_FN_SIM_D_PORT199,
/* SDHI0 */
GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2,
GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP,
GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK,
/* SDHI1 */
GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2,
GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP,
GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK,
/* SDHI2 */
GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2,
GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD,
GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
GPIO_FN_SDHI2_WP_PORT25,
GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
GPIO_FN_SDHI2_CD_PORT202,
/* MSIOF2 */
GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK,
GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1,
GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC,
GPIO_FN_MSIOF2_RSCK,
/* KEYSC */
GPIO_FN_KEYIN4, GPIO_FN_KEYIN5,
GPIO_FN_KEYIN6, GPIO_FN_KEYIN7,
GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2,
GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5,
GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7,
GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
GPIO_FN_KEYIN1_PORT44,
GPIO_FN_KEYIN2_PORT45,
GPIO_FN_KEYIN3_PORT46,
GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
GPIO_FN_KEYIN1_PORT57,
GPIO_FN_KEYIN2_PORT56,
GPIO_FN_KEYIN3_PORT55,
/* VOU */
GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3,
GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7,
GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11,
GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15,
GPIO_FN_DV_CLK,
GPIO_FN_DV_VSYNC,
GPIO_FN_DV_HSYNC,
/* MEMC */
GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2,
GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5,
GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8,
GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11,
GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14,
GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT,
GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE,
GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
GPIO_FN_MEMC_ADV,
GPIO_FN_MEMC_WAIT,
GPIO_FN_MEMC_BUSCLK,
GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
GPIO_FN_MEMC_DREQ0,
GPIO_FN_MEMC_DREQ1,
GPIO_FN_MEMC_A0,
/* MMC */
GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69,
GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71,
GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73,
GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75,
GPIO_FN_MMC0_CLK_PORT66,
GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */
GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148,
GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146,
GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144,
GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142,
GPIO_FN_MMC1_CLK_PORT103,
GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */
/* MSIOF0 */
GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1,
GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK,
GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC,
/* MSIOF1 */
GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC,
GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117,
GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119,
GPIO_FN_MSIOF1_TSYNC_PORT120,
GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */
GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72,
GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74,
GPIO_FN_MSIOF1_RXD_PORT75,
GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */
/* GPIO */
GPIO_FN_GPO0, GPIO_FN_GPI0,
GPIO_FN_GPO1, GPIO_FN_GPI1,
/* USB0 */
GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS,
/* USB1 */
GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON,
/* BBIF1 */
GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC,
GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC,
GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N,
/* BBIF2 */
GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
GPIO_FN_BBIF2_RXD2_PORT60,
GPIO_FN_BBIF2_TSYNC2_PORT6,
GPIO_FN_BBIF2_TSCK2_PORT59,
GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
GPIO_FN_BBIF2_TXD2_PORT183,
GPIO_FN_BBIF2_TSCK2_PORT89,
GPIO_FN_BBIF2_TSYNC2_PORT184,
/* BSC / FLCTL / PCMCIA */
GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4,
GPIO_FN_CS5B, GPIO_FN_CS6A,
GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
GPIO_FN_CS5A_PORT19,
GPIO_FN_IOIS16, /* ? */
GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3,
GPIO_FN_A4_FOE, /* share with FLCTL */
GPIO_FN_A5_FCDE, /* share with FLCTL */
GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9,
GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13,
GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17,
GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21,
GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25,
GPIO_FN_A26,
GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */
GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */
GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */
GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */
GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */
GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */
GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */
GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */
GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19,
GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23,
GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27,
GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31,
GPIO_FN_WE0_FWE, /* share with FLCTL */
GPIO_FN_WE1,
GPIO_FN_WE2_ICIORD, /* share with PCMCIA */
GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */
GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR,
GPIO_FN_RD_FSC, /* share with FLCTL */
GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */
GPIO_FN_WAIT_PORT90,
GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */
/* IRDA */
GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT,
/* ATAPI */
GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2,
GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5,
GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8,
GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11,
GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14,
GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1,
GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1,
GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY,
GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION,
GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ,
/* RMII */
GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0,
GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0,
GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO,
GPIO_FN_RMII_REF50CK, /* for RMII */
GPIO_FN_RMII_REF125CK, /* for GMII */
/* GEther */
GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0,
GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3,
GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */
GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */
GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER,
GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV,
GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1,
GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3,
GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */
GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */
GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS,
GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO,
GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT,
GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK,
/* DMA0 */
GPIO_FN_DREQ0, GPIO_FN_DACK0,
/* DMA1 */
GPIO_FN_DREQ1, GPIO_FN_DACK1,
/* SYSC */
GPIO_FN_RESETOUTS,
GPIO_FN_RESETP_PULLUP,
GPIO_FN_RESETP_PLAIN,
/* SDENC */
GPIO_FN_SDENC_CPG,
GPIO_FN_SDENC_DV_CLKI,
/* IRREM */
GPIO_FN_IROUT,
/* DEBUG */
GPIO_FN_EDEBGREQ_PULLDOWN,
GPIO_FN_EDEBGREQ_PULLUP,
GPIO_FN_TRACEAUD_FROM_VIO,
GPIO_FN_TRACEAUD_FROM_LCDC0,
GPIO_FN_TRACEAUD_FROM_MEMC,
};
#endif /* __ASM_R8A7740_H__ */

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arch/arm/mach-rmobile/include/mach/r8a7740.h
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@ -1,274 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2012 Renesas Solutions Corp.
*/
#ifndef __ASM_ARCH_R8A7740_H
#define __ASM_ARCH_R8A7740_H
/*
* R8A7740 I/O Addresses
*/
#define MERAM_BASE 0xE5580000
#define DDRP_BASE 0xC12A0000
#define HPB_BASE 0xE6000000
#define RWDT0_BASE 0xE6020000
#define RWDT1_BASE 0xE6030000
#define GPIO_BASE 0xE6050000
#define CMT1_BASE 0xE6138000
#define CPG_BASE 0xE6150000
#define SYSC_BASE 0xE6180000
#define SDHI0_BASE 0xE6850000
#define SDHI1_BASE 0xE6860000
#define MMCIF_BASE 0xE6BD0000
#define SCIF5_BASE 0xE6CB0000
#define SCIF6_BASE 0xE6CC0000
#define DBSC_BASE 0xFE400000
#define BSC_BASE 0xFEC10000
#define I2C0_BASE 0xFFF20000
#define I2C1_BASE 0xE6C20000
#define TMU_BASE 0xFFF80000
#ifndef __ASSEMBLY__
#include <asm/types.h>
/* RWDT */
struct r8a7740_rwdt {
u16 rwtcnt0; /* 0x00 */
u16 dummy0; /* 0x02 */
u16 rwtcsra0; /* 0x04 */
u16 dummy1; /* 0x06 */
u16 rwtcsrb0; /* 0x08 */
u16 dummy2; /* 0x0A */
};
/* HPB Semaphore Control Registers */
struct r8a7740_hpb {
u32 hpbctrl0;
u32 hpbctrl1;
u32 hpbctrl2;
u32 cccr;
u32 dummy0; /* 0x20 */
u32 hpbctrl4;
u32 hpbctrl5;
};
/* CPG */
struct r8a7740_cpg {
u32 frqcra;
u32 frqcrb;
u32 vclkcr1;
u32 vclkcr2;
u32 fmsickcr;
u32 fmsockcr;
u32 fsiackcr;
u32 dummy0; /* 0x1c */
u32 rtstbcr;
u32 systbcr;
u32 pllc01cr;
u32 pllc2cr;
u32 mstpsr0;
u32 dummy1; /* 0x34 */
u32 mstpsr1;
u32 mstpsr5;
u32 mstpsr2;
u32 dummy2; /* 0x44 */
u32 mstpsr3;
u32 mstpsr4;
u32 dummy3; /* 0x50 */
u32 astat;
u32 dummy4[4]; /* 0x58 .. 0x64 */
u32 ztrckcr;
u32 dummy5[5]; /* 0x6c .. 0x7c */
u32 subckcr;
u32 spuckcr;
u32 vouckcr;
u32 usbckcr;
u32 dummy6[3]; /* 0x90 .. 0x98 */
u32 stprckcr;
u32 srcr0;
u32 dummy7; /* 0xa4 */
u32 srcr1;
u32 dummy8; /* 0xac */
u32 srcr2;
u32 dummy9; /* 0xb4 */
u32 srcr3;
u32 srcr4;
u32 dummy10; /* 0xc0 */
u32 srcr5;
u32 pllc01stpcr;
u32 dummy11[5]; /* 0xcc .. 0xdc */
u32 frqcrc;
u32 frqcrd;
u32 dummy12[10]; /* 0xe8 .. 0x10c */
u32 rmstpcr0;
u32 rmstpcr1;
u32 rmstpcr2;
u32 rmstpcr3;
u32 rmstpcr4;
u32 rmstpcr5;
u32 dummy13[2]; /* 0x128 .. 0x12c */
u32 smstpcr0;
u32 smstpcr1;
u32 smstpcr2;
u32 smstpcr3;
u32 smstpcr4;
u32 smstpcr5;
};
/* BSC */
struct r8a7740_bsc {
u32 cmncr;
u32 cs0bcr;
u32 cs2bcr;
u32 dummy0; /* 0x0c */
u32 cs4bcr;
u32 cs5abcr;
u32 cs5bbcr;
u32 cs6abcr;
u32 dummy1; /* 0x20 */
u32 cs0wcr;
u32 cs2wcr;
u32 dummy2; /* 0x2c */
u32 cs4wcr;
u32 cs5awcr;
u32 cs5bwcr;
u32 cs6awcr;
u32 dummy3[5]; /* 0x40 .. 0x50 */
u32 rbwtcnt;
u32 busycr;
u32 dummy4[5]; /* 0x5c .. 0x6c */
u32 bromtimcr;
u32 dummy5[7]; /* 0x74 .. 0x8c */
u32 bptcr00;
u32 bptcr01;
u32 bptcr02;
u32 bptcr03;
u32 bptcr04;
u32 bptcr05;
u32 bptcr06;
u32 bptcr07;
u32 bptcr08;
u32 bptcr09;
u32 bptcr10;
u32 bptcr11;
u32 bptcr12;
u32 bptcr13;
u32 bptcr14;
u32 bptcr15;
u32 bptcr16;
u32 bptcr17;
u32 bptcr18;
u32 bptcr19;
u32 bptcr20;
u32 bptcr21;
u32 bptcr22;
u32 bptcr23;
u32 bptcr24;
u32 bptcr25;
u32 bptcr26;
u32 bptcr27;
u32 bptcr28;
u32 bptcr29;
u32 bptcr30;
u32 bptcr31;
u32 bswcr;
u32 dummy6[68]; /* 0x114 .. 0x220 */
u32 cs0wcr2;
u32 cs2wcr2;
u32 dummy7; /* 0x22c */
u32 cs4wcr2;
};
#define CS0WCR2 0xFEC10224
#define CS2WCR2 0xFEC10228
#define CS4WCR2 0xFEC10230
/* DDRP */
struct r8a7740_ddrp {
u32 funcctrl;
u32 dllctrl;
u32 zqcalctrl;
u32 zqodtctrl;
u32 rdctrl;
u32 rdtmg;
u32 fifoinit;
u32 outctrl;
u32 dummy0[50]; /* 0x20 .. 0xe4 */
u32 dqcalofs1;
u32 dqcalofs2;
u32 dummy1[2]; /* 0xf0 .. 0xf4 */
u32 dqcalexp;
};
#define DDRPNCNT 0xE605803C
#define DDRVREFCNT 0xE61500EC
/* DBSC */
struct r8a7740_dbsc {
u32 dummy0;
u32 dbsvcr;
u32 dbstate0;
u32 dbstate1;
u32 dbacen;
u32 dbrfen;
u32 dbcmd;
u32 dbwait;
u32 dbkind;
u32 dbconf0;
u32 dummy1[2]; /* 0x28 .. 0x2c */
u32 dbphytype;
u32 dummy2[3]; /* 0x34 .. 0x3c */
u32 dbtr0;
u32 dbtr1;
u32 dbtr2;
u32 dummy3; /* 0x4c */
u32 dbtr3;
u32 dbtr4;
u32 dbtr5;
u32 dbtr6;
u32 dbtr7;
u32 dbtr8;
u32 dbtr9;
u32 dbtr10;
u32 dbtr11;
u32 dbtr12;
u32 dbtr13;
u32 dbtr14;
u32 dbtr15;
u32 dbtr16;
u32 dbtr17;
u32 dbtr18;
u32 dbtr19;
u32 dummy4[7]; /* 0x94 .. 0xac */
u32 dbbl;
u32 dummy5[3]; /* 0xb4 .. 0xbc */
u32 dbadj0;
u32 dbadj1;
u32 dbadj2;
u32 dummy6[5]; /* 0xcc .. 0xdc */
u32 dbrfcnf0;
u32 dbrfcnf1;
u32 dbrfcnf2;
u32 dbrfcnf3;
u32 dummy7; /* 0xf0 */
u32 dbcalcnf;
u32 dbcaltr;
u32 dummy8; /* 0xfc */;
u32 dbrnk0;
u32 dummy9[31]; /* 0x104 .. 0x17C */
u32 dbpdncnf;
u32 dummy10[7]; /* 0x184 .. 0x19C */
u32 dbmrrdr;
u32 dummy11[39]; /* 0x1A4 .. 0x23C */
u32 dbdfistat;
u32 dbdficnt;
u32 dummy12[46]; /* 0x248 .. 0x2FC */
u32 dbbs0cnt0;
u32 dbbs0cnt1;
};
#endif
#endif /* __ASM_ARCH_R8A7740_H */

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arch/arm/mach-rmobile/include/mach/rmobile.h
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#ifndef __ASM_ARCH_RMOBILE_H
#define __ASM_ARCH_RMOBILE_H
#if defined(CONFIG_ARCH_RMOBILE)
#if defined(CONFIG_R8A7740)
#include <asm/arch/r8a7740.h>
#elif defined(CONFIG_R8A7790)
#include <asm/arch/r8a7790.h>
#elif defined(CONFIG_R8A7791)
#include <asm/arch/r8a7791.h>
#elif defined(CONFIG_R8A7792)
#include <asm/arch/r8a7792.h>
#elif defined(CONFIG_R8A7793)
#include <asm/arch/r8a7793.h>
#elif defined(CONFIG_R8A7794)
#include <asm/arch/r8a7794.h>
#elif defined(CONFIG_RCAR_GEN3)
#include <asm/arch/rcar-gen3-base.h>
#elif defined(CONFIG_RCAR_GEN4)
#include <asm/arch/rcar-gen4-base.h>
#elif defined(CONFIG_R7S72100)
#elif defined(CONFIG_RZG2L)
#include <asm/arch/rzg2l.h>
#else
#error "SOC Name not defined"
#endif
#endif /* CONFIG_ARCH_RMOBILE */
/* PRR CPU IDs */
#define RMOBILE_CPU_TYPE_R8A7740 0x40
#define RMOBILE_CPU_TYPE_R8A7790 0x45
#define RMOBILE_CPU_TYPE_R8A7791 0x47
#define RMOBILE_CPU_TYPE_R8A7792 0x4A
#define RMOBILE_CPU_TYPE_R8A7793 0x4B
#define RMOBILE_CPU_TYPE_R8A7794 0x4C
#define RMOBILE_CPU_TYPE_R8A7795 0x4F
#define RMOBILE_CPU_TYPE_R8A7796 0x52
#define RMOBILE_CPU_TYPE_R8A77965 0x55
#define RMOBILE_CPU_TYPE_R8A77970 0x54
#define RMOBILE_CPU_TYPE_R8A77980 0x56
#define RMOBILE_CPU_TYPE_R8A77990 0x57
#define RMOBILE_CPU_TYPE_R8A77995 0x58
#define RMOBILE_CPU_TYPE_R8A779A0 0x59
#define RMOBILE_CPU_TYPE_R8A779F0 0x5A
#define RMOBILE_CPU_TYPE_R8A779G0 0x5C
#define RMOBILE_CPU_TYPE_R8A779H0 0x5D
#define RMOBILE_CPU_TYPE_R9A07G044L 0x9A070440
#ifndef __ASSEMBLY__
#include <asm/types.h>
const u8 *rzg_get_cpu_name(void);
u32 rmobile_get_cpu_type(void);
u32 rmobile_get_cpu_rev_integer(void);
u32 rmobile_get_cpu_rev_fraction(void);
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_RMOBILE_H */

170
arch/arm/mach-rmobile/include/mach/sh_sdhi.h
View file

@ -1,170 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* drivers/mmc/sh-sdhi.h
*
* SD/MMC driver for Renesas rmobile ARM SoCs
*
* Copyright (C) 2013-2017 Renesas Electronics Corporation
* Copyright (C) 2008-2009 Renesas Solutions Corp.
*/
#ifndef _SH_SDHI_H
#define _SH_SDHI_H
#include <linux/bitops.h>
#define SDHI_CMD (0x0000 >> 1)
#define SDHI_PORTSEL (0x0004 >> 1)
#define SDHI_ARG0 (0x0008 >> 1)
#define SDHI_ARG1 (0x000C >> 1)
#define SDHI_STOP (0x0010 >> 1)
#define SDHI_SECCNT (0x0014 >> 1)
#define SDHI_RSP00 (0x0018 >> 1)
#define SDHI_RSP01 (0x001C >> 1)
#define SDHI_RSP02 (0x0020 >> 1)
#define SDHI_RSP03 (0x0024 >> 1)
#define SDHI_RSP04 (0x0028 >> 1)
#define SDHI_RSP05 (0x002C >> 1)
#define SDHI_RSP06 (0x0030 >> 1)
#define SDHI_RSP07 (0x0034 >> 1)
#define SDHI_INFO1 (0x0038 >> 1)
#define SDHI_INFO2 (0x003C >> 1)
#define SDHI_INFO1_MASK (0x0040 >> 1)
#define SDHI_INFO2_MASK (0x0044 >> 1)
#define SDHI_CLK_CTRL (0x0048 >> 1)
#define SDHI_SIZE (0x004C >> 1)
#define SDHI_OPTION (0x0050 >> 1)
#define SDHI_ERR_STS1 (0x0058 >> 1)
#define SDHI_ERR_STS2 (0x005C >> 1)
#define SDHI_BUF0 (0x0060 >> 1)
#define SDHI_SDIO_MODE (0x0068 >> 1)
#define SDHI_SDIO_INFO1 (0x006C >> 1)
#define SDHI_SDIO_INFO1_MASK (0x0070 >> 1)
#define SDHI_CC_EXT_MODE (0x01B0 >> 1)
#define SDHI_SOFT_RST (0x01C0 >> 1)
#define SDHI_VERSION (0x01C4 >> 1)
#define SDHI_HOST_MODE (0x01C8 >> 1)
#define SDHI_SDIF_MODE (0x01CC >> 1)
#define SDHI_EXT_SWAP (0x01E0 >> 1)
#define SDHI_SD_DMACR (0x0324 >> 1)
/* SDHI CMD VALUE */
#define CMD_MASK 0x0000ffff
/* SDHI_PORTSEL */
#define USE_1PORT (1 << 8) /* 1 port */
/* SDHI_ARG */
#define ARG0_MASK 0x0000ffff
#define ARG1_MASK 0x0000ffff
/* SDHI_STOP */
#define STOP_SEC_ENABLE (1 << 8)
/* SDHI_INFO1 */
#define INFO1_RESP_END (1 << 0)
#define INFO1_ACCESS_END (1 << 2)
#define INFO1_CARD_RE (1 << 3)
#define INFO1_CARD_IN (1 << 4)
#define INFO1_ISD0CD (1 << 5)
#define INFO1_WRITE_PRO (1 << 7)
#define INFO1_DATA3_CARD_RE (1 << 8)
#define INFO1_DATA3_CARD_IN (1 << 9)
#define INFO1_DATA3 (1 << 10)
/* SDHI_INFO2 */
#define INFO2_CMD_ERROR (1 << 0)
#define INFO2_CRC_ERROR (1 << 1)
#define INFO2_END_ERROR (1 << 2)
#define INFO2_TIMEOUT (1 << 3)
#define INFO2_BUF_ILL_WRITE (1 << 4)
#define INFO2_BUF_ILL_READ (1 << 5)
#define INFO2_RESP_TIMEOUT (1 << 6)
#define INFO2_SDDAT0 (1 << 7)
#define INFO2_BRE_ENABLE (1 << 8)
#define INFO2_BWE_ENABLE (1 << 9)
#define INFO2_CBUSY (1 << 14)
#define INFO2_ILA (1 << 15)
#define INFO2_ALL_ERR (0x807f)
/* SDHI_INFO1_MASK */
#define INFO1M_RESP_END (1 << 0)
#define INFO1M_ACCESS_END (1 << 2)
#define INFO1M_CARD_RE (1 << 3)
#define INFO1M_CARD_IN (1 << 4)
#define INFO1M_DATA3_CARD_RE (1 << 8)
#define INFO1M_DATA3_CARD_IN (1 << 9)
#define INFO1M_ALL (0xffff)
#define INFO1M_SET (INFO1M_RESP_END | \
INFO1M_ACCESS_END | \
INFO1M_DATA3_CARD_RE | \
INFO1M_DATA3_CARD_IN)
/* SDHI_INFO2_MASK */
#define INFO2M_CMD_ERROR (1 << 0)
#define INFO2M_CRC_ERROR (1 << 1)
#define INFO2M_END_ERROR (1 << 2)
#define INFO2M_TIMEOUT (1 << 3)
#define INFO2M_BUF_ILL_WRITE (1 << 4)
#define INFO2M_BUF_ILL_READ (1 << 5)
#define INFO2M_RESP_TIMEOUT (1 << 6)
#define INFO2M_BRE_ENABLE (1 << 8)
#define INFO2M_BWE_ENABLE (1 << 9)
#define INFO2M_ILA (1 << 15)
#define INFO2M_ALL (0xffff)
#define INFO2M_ALL_ERR (0x807f)
/* SDHI_CLK_CTRL */
#define CLK_ENABLE (1 << 8)
/* SDHI_OPTION */
#define OPT_BUS_WIDTH_M (5 << 13) /* 101b (15-13bit) */
#define OPT_BUS_WIDTH_1 (4 << 13) /* bus width = 1 bit */
#define OPT_BUS_WIDTH_4 (0 << 13) /* bus width = 4 bit */
#define OPT_BUS_WIDTH_8 (1 << 13) /* bus width = 8 bit */
/* SDHI_ERR_STS1 */
#define ERR_STS1_CRC_ERROR ((1 << 11) | (1 << 10) | (1 << 9) | \
(1 << 8) | (1 << 5))
#define ERR_STS1_CMD_ERROR ((1 << 4) | (1 << 3) | (1 << 2) | \
(1 << 1) | (1 << 0))
/* SDHI_ERR_STS2 */
#define ERR_STS2_RES_TIMEOUT (1 << 0)
#define ERR_STS2_RES_STOP_TIMEOUT ((1 << 0) | (1 << 1))
#define ERR_STS2_SYS_ERROR ((1 << 6) | (1 << 5) | (1 << 4) | \
(1 << 3) | (1 << 2) | (1 << 1) | \
(1 << 0))
/* SDHI_SDIO_MODE */
#define SDIO_MODE_ON (1 << 0)
#define SDIO_MODE_OFF (0 << 0)
/* SDHI_SDIO_INFO1 */
#define SDIO_INFO1_IOIRQ (1 << 0)
#define SDIO_INFO1_EXPUB52 (1 << 14)
#define SDIO_INFO1_EXWT (1 << 15)
/* SDHI_SDIO_INFO1_MASK */
#define SDIO_INFO1M_CLEAR ((1 << 1) | (1 << 2))
#define SDIO_INFO1M_ON ((1 << 15) | (1 << 14) | (1 << 2) | \
(1 << 1) | (1 << 0))
/* SDHI_EXT_SWAP */
#define SET_SWAP ((1 << 6) | (1 << 7)) /* SWAP */
/* SDHI_SOFT_RST */
#define SOFT_RST_ON (0 << 0)
#define SOFT_RST_OFF (1 << 0)
#define CLKDEV_SD_DATA 25000000 /* 25 MHz */
#define CLKDEV_HS_DATA 50000000 /* 50 MHz */
#define CLKDEV_MMC_DATA 20000000 /* 20MHz */
#define CLKDEV_INIT 400000 /* 100 - 400 KHz */
/* For quirk */
#define SH_SDHI_QUIRK_16BIT_BUF BIT(0)
#define SH_SDHI_QUIRK_64BIT_BUF BIT(1)
int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks);
#endif /* _SH_SDHI_H */

72
arch/arm/mach-rmobile/lowlevel_init.S
View file

@ -1,72 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com>
* Copyright (C) 2012 Renesas Solutions Corp.
*/
#include <config.h>
#include <linux/linkage.h>
#include <system-constants.h>
ENTRY(lowlevel_init)
ldr r0, =MERAM_BASE
mov r1, #0x0
str r1, [r0]
mrc p15, 0, r0, c0, c0, 5
ands r0, r0, #0xF
beq lowlevel_init__
b wait_interrupt
.pool
.align 4
wait_interrupt:
#ifdef ICCICR
ldr r1, =ICCICR
mov r2, #0x0
str r2, [r1]
mov r2, #0xF0
adds r1, r1, #4 /* ICCPMR */
str r2, [r1]
ldr r1, =ICCICR
mov r2, #0x1
str r2, [r1]
#endif
wait_loop:
.long 0xE320F003 /* wfi */
ldr r2, [r1, #0xC]
str r2, [r1, #0x10]
ldr r0, =MERAM_BASE
ldr r2, [r0]
cmp r2, #0
movne pc, r2
b wait_loop
wait_loop_end:
.pool
.align 4
lowlevel_init__:
mov r0, #0x200000
loop0:
subs r0, r0, #1
bne loop0
ldr sp, MERAM_STACK
b s_init
.pool
.align 4
ENDPROC(lowlevel_init)
.ltorg
MERAM_STACK:
.word LOW_LEVEL_MERAM_STACK

2612
arch/arm/mach-rmobile/pfc-r8a7740.c
View file

File diff suppressed because it is too large Load diff

139
arch/arm/mach-rmobile/pfc-r8a7790.h
View file

@ -1,139 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
*
* Copyright (C) 2013 Renesas Electronics Corporation
*/
#ifndef __PFC_R8A7790_H__
#define __PFC_R8A7790_H__
#include <sh_pfc.h>
#include <asm/gpio.h>
#define CPU_32_PORT(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
PORT_1(fn, pfx##31, sfx)
#define CPU_32_PORT2(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_10(fn, pfx##2, sfx)
#if defined(CONFIG_R8A7790)
#define CPU_32_PORT1(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_10(fn, pfx##2, sfx) \
/* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */
#define CPU_ALL_PORT(fn, pfx, sfx) \
CPU_32_PORT(fn, pfx##_0_, sfx), \
CPU_32_PORT1(fn, pfx##_1_, sfx), \
CPU_32_PORT2(fn, pfx##_2_, sfx), \
CPU_32_PORT(fn, pfx##_3_, sfx), \
CPU_32_PORT(fn, pfx##_4_, sfx), \
CPU_32_PORT(fn, pfx##_5_, sfx)
#elif defined(CONFIG_R8A7791)
#define CPU_32_PORT1(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
/*
* GP_0_0_DATA -> GP_7_25_DATA
* (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31]
* GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31])
*/
#define CPU_ALL_PORT(fn, pfx, sfx) \
CPU_32_PORT(fn, pfx##_0_, sfx), \
CPU_32_PORT1(fn, pfx##_1_, sfx), \
CPU_32_PORT(fn, pfx##_2_, sfx), \
CPU_32_PORT(fn, pfx##_3_, sfx), \
CPU_32_PORT(fn, pfx##_4_, sfx), \
CPU_32_PORT(fn, pfx##_5_, sfx), \
CPU_32_PORT(fn, pfx##_6_, sfx), \
CPU_32_PORT1(fn, pfx##_7_, sfx)
#elif defined(CONFIG_R8A7792)
/*
* GP_0_0_DATA -> GP_11_29_DATA
* (except for GP0[29..31],GP1[23..31],GP3[28..31],GP4[17..31],GP5[17..31]
* GP6[17..31],GP7[17..31],GP8[17..31],GP9[17..31],GP11[30..31])
*/
#define CPU_32_PORT0_28(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx), \
PORT_1(fn, pfx##28, sfx)
#define CPU_32_PORT0_22(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
PORT_1(fn, pfx##22, sfx)
#define CPU_32_PORT0_27(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
#define CPU_32_PORT0_16(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), \
PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx), \
PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx), \
PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx), \
PORT_1(fn, pfx##16, sfx)
#define CPU_ALL_PORT(fn, pfx, sfx) \
CPU_32_PORT0_28(fn, pfx##_0_, sfx), \
CPU_32_PORT0_22(fn, pfx##_1_, sfx), \
CPU_32_PORT(fn, pfx##_2_, sfx), \
CPU_32_PORT0_27(fn, pfx##_3_, sfx), \
CPU_32_PORT0_16(fn, pfx##_4_, sfx), \
CPU_32_PORT0_16(fn, pfx##_5_, sfx), \
CPU_32_PORT0_16(fn, pfx##_6_, sfx), \
CPU_32_PORT0_16(fn, pfx##_7_, sfx), \
CPU_32_PORT0_16(fn, pfx##_8_, sfx), \
CPU_32_PORT0_16(fn, pfx##_9_, sfx), \
CPU_32_PORT(fn, pfx##_10_, sfx), \
CPU_32_PORT2(fn, pfx##_11_, sfx)
#else
#error "NO support"
#endif
#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
GP##pfx##_IN, GP##pfx##_OUT)
#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
#define PORT_10_REV(fn, pfx, sfx) \
PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
#define CPU_32_PORT_REV(fn, pfx, sfx) \
PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
PORT_10_REV(fn, pfx, sfx)
#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
FN_##ipsr, FN_##fn)
#endif /* __PFC_R8A7790_H__ */

2
arch/sh/lib/time.c
View file

@ -16,7 +16,7 @@
#include <asm/io.h>
#include <linux/bitops.h>
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE)
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RENESAS)
#define TSTR 0x4
#define TCR0 0x10
#endif /* CONFIG_CPU_SH4 */

2
board/beacon/beacon-rzg2m/Kconfig
View file

@ -1,7 +1,7 @@
if TARGET_BEACON_RZG2M
config SYS_SOC
default "rmobile"
default "renesas"
config SYS_BOARD
default "beacon-rzg2m"

2
board/hoperun/hihope-rzg2/Kconfig
View file

@ -1,7 +1,7 @@
if TARGET_HIHOPE_RZG2
config SYS_SOC
default "rmobile"
default "renesas"
config SYS_BOARD
default "hihope-rzg2"

2
board/hoperun/hihope-rzg2/hihope-rzg2.c
View file

@ -10,7 +10,7 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <linux/bitops.h>
#include <linux/delay.h>

4
board/renesas/alt/alt.c
View file

@ -22,10 +22,8 @@
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/mmc.h>
#include <asm/arch/sh_sdhi.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>

2
board/renesas/alt/alt_spl.c
View file

@ -16,7 +16,7 @@
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <spl.h>

8
board/renesas/alt/qos.c
View file

@ -9,9 +9,9 @@
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#if defined(CONFIG_RENESAS_EXTRAM_BOOT)
/* QoS version 0.311 for ES1 and version 0.321 for ES2 */
enum {
@ -991,8 +991,8 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
}
#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
#else /* CONFIG_RENESAS_EXTRAM_BOOT */
void qos_init(void)
{
}
#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
#endif /* CONFIG_RENESAS_EXTRAM_BOOT */

6
board/renesas/blanche/blanche.c
View file

@ -9,10 +9,8 @@
#include <cpu_func.h>
#include <init.h>
#include <net.h>
#include <asm/arch/mmc.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/sh_sdhi.h>
#include <asm/arch/renesas.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
@ -51,7 +49,7 @@ static void blanche_init_sys(void)
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
u32 cpu_type;
cpu_type = rmobile_get_cpu_type();
cpu_type = renesas_get_cpu_type();
if (cpu_type == 0x4A) {
writel(0x4D000000, CPG_PLL1CR);
writel(0x4F000000, CPG_PLL3CR);

8
board/renesas/blanche/qos.c
View file

@ -8,9 +8,9 @@
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
#if defined(CONFIG_RENESAS_EXTRAM_BOOT)
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
@ -1357,8 +1357,8 @@ void qos_init(void)
writel(0x0000F700, CCI_AXI_AX2ADDRMASK);
}
#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
#else /* CONFIG_RENESAS_EXTRAM_BOOT */
void qos_init(void)
{
}
#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
#endif /* CONFIG_RENESAS_EXTRAM_BOOT */

2
board/renesas/condor/Kconfig
View file

@ -1,7 +1,7 @@
if TARGET_CONDOR
config SYS_SOC
default "rmobile"
default "renesas"
config SYS_BOARD
default "condor"

2
board/renesas/draak/Kconfig
View file

@ -1,7 +1,7 @@
if TARGET_DRAAK
config SYS_SOC
default "rmobile"
default "renesas"
config SYS_BOARD
default "draak"

3
board/renesas/draak/draak.c
View file

@ -22,9 +22,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/sh_sdhi.h>
#include <i2c.h>
#include <mmc.h>

2
board/renesas/eagle/Kconfig
View file

@ -1,7 +1,7 @@
if TARGET_EAGLE
config SYS_SOC
default "rmobile"
default "renesas"
config SYS_BOARD
default "eagle"

2
board/renesas/ebisu/Kconfig
View file

@ -1,7 +1,7 @@
if TARGET_EBISU
config SYS_SOC
default "rmobile"
default "renesas"
config SYS_BOARD
default "ebisu"

2
board/renesas/falcon/Kconfig
View file

@ -1,7 +1,7 @@
if TARGET_FALCON
config SYS_SOC
default "rmobile"
default "renesas"
config SYS_BOARD
default "falcon"

2
board/renesas/falcon/falcon.c
View file

@ -6,7 +6,7 @@
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/io.h>

3
board/renesas/gose/gose.c
View file

@ -23,9 +23,8 @@
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/sh_sdhi.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>

2
board/renesas/gose/gose_spl.c
View file

@ -16,7 +16,7 @@
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <spl.h>

8
board/renesas/gose/qos.c
View file

@ -9,9 +9,9 @@
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#if defined(CONFIG_RENESAS_EXTRAM_BOOT)
/* QoS version 0.311 */
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
@ -1194,8 +1194,8 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
}
#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
#else /* CONFIG_RENESAS_EXTRAM_BOOT */
void qos_init(void)
{
}
#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
#endif /* CONFIG_RENESAS_EXTRAM_BOOT */

2
board/renesas/grayhawk/Kconfig
View file

@ -1,7 +1,7 @@
if TARGET_GRAYHAWK
config SYS_SOC
default "rmobile"
default "renesas"
config SYS_BOARD
default "grayhawk"

2
board/renesas/grayhawk/grayhawk.c
View file

@ -6,7 +6,7 @@
* Copyright (C) 2023 Renesas Electronics Corp.
*/
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/io.h>

3
board/renesas/koelsch/koelsch.c
View file

@ -24,9 +24,8 @@
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/sh_sdhi.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>

2
board/renesas/koelsch/koelsch_spl.c
View file

@ -16,7 +16,7 @@
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <spl.h>

8
board/renesas/koelsch/qos.c
View file

@ -9,10 +9,10 @@
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
/* QoS version 0.240 for ES1 and version 0.411 for ES2 */
#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#if defined(CONFIG_RENESAS_EXTRAM_BOOT)
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
@ -1382,8 +1382,8 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
}
#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
#else /* CONFIG_RENESAS_EXTRAM_BOOT */
void qos_init(void)
{
}
#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
#endif /* CONFIG_RENESAS_EXTRAM_BOOT */

6
board/renesas/lager/lager.c
View file

@ -26,10 +26,8 @@
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/mmc.h>
#include <asm/arch/sh_sdhi.h>
#include <miiphy.h>
#include <i2c.h>
#include <mmc.h>
@ -48,7 +46,7 @@ void s_init(void)
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 1.4GHz */
if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
if (renesas_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
u32 stat = 0;
u32 stc = ((1400 / CLK2MHZ(get_board_sys_clk())) - 1)
<< PLL0_STC_BIT;

2
board/renesas/lager/lager_spl.c
View file

@ -16,7 +16,7 @@
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <spl.h>

10
board/renesas/lager/qos.c
View file

@ -8,10 +8,10 @@
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
/* QoS version 0.955 for ES1 and version 0.973 for ES2 */
#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#if defined(CONFIG_RENESAS_EXTRAM_BOOT)
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
@ -2419,13 +2419,13 @@ static void qos_init_es2(void)
void qos_init(void)
{
if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X)
if (renesas_get_cpu_rev_integer() >= R8A7790_CUT_ES2X)
qos_init_es2();
else
qos_init_es1();
}
#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
#else /* CONFIG_RENESAS_EXTRAM_BOOT */
void qos_init(void)
{
}
#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
#endif /* CONFIG_RENESAS_EXTRAM_BOOT */

3
board/renesas/porter/porter.c
View file

@ -24,9 +24,8 @@
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/sh_sdhi.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>

2
board/renesas/porter/porter_spl.c
View file

@ -16,7 +16,7 @@
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <spl.h>

8
board/renesas/porter/qos.c
View file

@ -10,10 +10,10 @@
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
/* QoS version 0.240 for ES1 and version 0.334 for ES2 */
#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#if defined(CONFIG_RENESAS_EXTRAM_BOOT)
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
@ -1303,8 +1303,8 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
}
#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
#else /* CONFIG_RENESAS_EXTRAM_BOOT */
void qos_init(void)
{
}
#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
#endif /* CONFIG_RENESAS_EXTRAM_BOOT */

2
board/renesas/rcar-common/common.c
View file

@ -14,7 +14,7 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <dm/uclass-internal.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <linux/libfdt.h>
#ifdef CONFIG_RCAR_64

2
board/renesas/rcar-common/v3-common.c
View file

@ -4,7 +4,7 @@
*/
#include <clock_legacy.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/io.h>
#define CPGWPR 0xE6150900

2
board/renesas/rzg2l/Kconfig
View file

@ -4,7 +4,7 @@
if TARGET_RZG2L_SMARC_EVK
config SYS_SOC
default "rmobile"
default "renesas"
config SYS_BOARD
default "rzg2l"

2
board/renesas/salvator-x/Kconfig
View file

@ -1,7 +1,7 @@
if TARGET_SALVATOR_X
config SYS_SOC
default "rmobile"
default "renesas"
config SYS_BOARD
default "salvator-x"

11
board/renesas/salvator-x/salvator-x.c
View file

@ -23,9 +23,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/sh_sdhi.h>
#include <i2c.h>
#include <mmc.h>
@ -77,17 +76,17 @@ void reset_cpu(void)
int board_fit_config_name_match(const char *name)
{
/* PRR driver is not available yet */
u32 cpu_type = rmobile_get_cpu_type();
u32 cpu_type = renesas_get_cpu_type();
if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) &&
if ((cpu_type == RENESAS_CPU_TYPE_R8A7795) &&
!strcmp(name, "r8a77950-salvator-x-u-boot"))
return 0;
if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) &&
if ((cpu_type == RENESAS_CPU_TYPE_R8A7796) &&
!strcmp(name, "r8a77960-salvator-x-u-boot"))
return 0;
if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) &&
if ((cpu_type == RENESAS_CPU_TYPE_R8A77965) &&
!strcmp(name, "r8a77965-salvator-x-u-boot"))
return 0;

8
board/renesas/silk/qos.c
View file

@ -10,9 +10,9 @@
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#if defined(CONFIG_RENESAS_EXTRAM_BOOT)
/* QoS version 0.11 */
enum {
@ -942,8 +942,8 @@ void qos_init(void)
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
}
#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
#else /* CONFIG_RENESAS_EXTRAM_BOOT */
void qos_init(void)
{
}
#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
#endif /* CONFIG_RENESAS_EXTRAM_BOOT */

4
board/renesas/silk/silk.c
View file

@ -23,10 +23,8 @@
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/mmc.h>
#include <asm/arch/sh_sdhi.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>

2
board/renesas/silk/silk_spl.c
View file

@ -16,7 +16,7 @@
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <spl.h>

2
board/renesas/spider/Kconfig
View file

@ -1,7 +1,7 @@
if TARGET_SPIDER
config SYS_SOC
default "rmobile"
default "renesas"
config SYS_BOARD
default "spider"

2
board/renesas/spider/spider.c
View file

@ -6,7 +6,7 @@
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/io.h>

10
board/renesas/stout/qos.c
View file

@ -10,10 +10,10 @@
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
/* QoS version 0.955 for ES1 and version 0.973 for ES2 */
#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#if defined(CONFIG_RENESAS_EXTRAM_BOOT)
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
@ -2421,13 +2421,13 @@ static void qos_init_es2(void)
void qos_init(void)
{
if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X)
if (renesas_get_cpu_rev_integer() >= R8A7790_CUT_ES2X)
qos_init_es2();
else
qos_init_es1();
}
#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
#else /* CONFIG_RENESAS_EXTRAM_BOOT */
void qos_init(void)
{
}
#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
#endif /* CONFIG_RENESAS_EXTRAM_BOOT */

6
board/renesas/stout/stout.c
View file

@ -25,10 +25,8 @@
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/mmc.h>
#include <asm/arch/sh_sdhi.h>
#include <miiphy.h>
#include <i2c.h>
#include <mmc.h>
@ -48,7 +46,7 @@ void s_init(void)
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 1.4GHz */
if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
if (renesas_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
u32 stat = 0;
u32 stc = ((1400 / CLK2MHZ(get_board_sys_clk())) - 1)
<< PLL0_STC_BIT;

2
board/renesas/stout/stout_spl.c
View file

@ -16,7 +16,7 @@
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <spl.h>

2
board/renesas/ulcb/Kconfig
View file

@ -1,7 +1,7 @@
if TARGET_ULCB
config SYS_SOC
default "rmobile"
default "renesas"
config SYS_BOARD
default "ulcb"

11
board/renesas/ulcb/ulcb.c
View file

@ -21,9 +21,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/sh_sdhi.h>
#include <i2c.h>
#include <mmc.h>
@ -68,17 +67,17 @@ int board_init(void)
int board_fit_config_name_match(const char *name)
{
/* PRR driver is not available yet */
u32 cpu_type = rmobile_get_cpu_type();
u32 cpu_type = renesas_get_cpu_type();
if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) &&
if ((cpu_type == RENESAS_CPU_TYPE_R8A7795) &&
!strcmp(name, "r8a77950-ulcb-u-boot"))
return 0;
if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) &&
if ((cpu_type == RENESAS_CPU_TYPE_R8A7796) &&
!strcmp(name, "r8a77960-ulcb-u-boot"))
return 0;
if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) &&
if ((cpu_type == RENESAS_CPU_TYPE_R8A77965) &&
!strcmp(name, "r8a77965-ulcb-u-boot"))
return 0;

2
board/renesas/v3hsk/Kconfig
View file

@ -1,7 +1,7 @@
if TARGET_V3HSK
config SYS_SOC
default "rmobile"
default "renesas"
config SYS_BOARD
default "v3hsk"

2
board/renesas/v3msk/Kconfig
View file

@ -1,7 +1,7 @@
if TARGET_V3MSK
config SYS_SOC
default "rmobile"
default "renesas"
config SYS_BOARD
default "v3msk"

2
board/renesas/whitehawk/Kconfig
View file

@ -1,7 +1,7 @@
if TARGET_WHITEHAWK
config SYS_SOC
default "rmobile"
default "renesas"
config SYS_BOARD
default "whitehawk"

2
board/renesas/whitehawk/whitehawk.c
View file

@ -6,7 +6,7 @@
* Copyright (C) 2021 Renesas Electronics Corp.
*/
#include <asm/arch/rmobile.h>
#include <asm/arch/renesas.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/io.h>

2
board/silinux/ek874/Kconfig
View file

@ -1,7 +1,7 @@
if TARGET_SILINUX_EK874
config SYS_SOC
default "rmobile"
default "renesas"
config SYS_BOARD
default "ek874"

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