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lpc32xx: devkit3250: add spl build support
The change adds SPL build support to Timll DevKit3250 board, the generated SPL image can be uploaded over UART5, JTAG or stored on NAND. SPL is designed to load U-boot image from NAND. All new NAND chip defines in board configuration are needed by SPL NAND "simple" framework, the framework is used to reduce potentially duplicated code from LPC32xx SLC NAND driver. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
This commit is contained in:
Vladimir Zapolskiy
Tom Rini
parent
768ddeeecf
commit
e9b3ce3f7e
5 changed files with 124 additions and 0 deletions
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@ -121,6 +121,7 @@ config TARGET_MAXBCM
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config TARGET_DEVKIT3250
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bool "Support devkit3250"
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select CPU_ARM926EJS
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select SUPPORT_SPL
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config TARGET_WORK_92105
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bool "Support work_92105"
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@ -6,3 +6,4 @@
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#
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obj-y := devkit3250.o
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obj-$(CONFIG_SPL_BUILD) += devkit3250_spl.o
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68
board/timll/devkit3250/devkit3250_spl.c
Normal file
68
board/timll/devkit3250/devkit3250_spl.c
Normal file
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@ -0,0 +1,68 @@
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/*
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* Timll DevKit3250 board support, SPL board configuration
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*
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* (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/emc.h>
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#include <asm/arch-lpc32xx/gpio.h>
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#include <spl.h>
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static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
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/*
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* SDRAM K4S561632N-LC60 settings are selected in assumption that
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* SDRAM clock may be set up to 166 MHz, however at the moment
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* it is 104 MHz. Most delay values are converted to be a multiple of
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* base clock, and precise pinned values are not needed here.
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*/
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struct emc_dram_settings dram_64mb = {
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.cmddelay = 0x0001C000,
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.config0 = 0x00005682,
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.rascas0 = 0x00000302,
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.rdconfig = 0x00000011, /* undocumented but crucial value */
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.trp = 83333333,
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.tras = 23809524,
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.tsrex = 12500000,
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.twr = 83000000, /* tWR = tRDL = 2 CLK */
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.trc = 15384616,
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.trfc = 15384616,
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.txsr = 12500000,
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.trrd = 1,
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.tmrd = 1,
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.tcdlr = 0,
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.refresh = 130000, /* 800 clock cycles */
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.mode = 0x00018000,
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.emode = 0x02000000,
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};
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void spl_board_init(void)
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{
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/* First of all silence buzzer controlled by GPO_20 */
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writel((1 << 20), &gpio->p3_outp_clr);
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lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
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preloader_console_init();
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ddr_init(&dram_64mb);
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/*
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* NAND initialization is done by nand_init(),
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* here just enable NAND SLC clocks
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*/
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lpc32xx_slc_nand_init();
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}
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_NAND;
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}
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@ -1,5 +1,6 @@
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CONFIG_ARM=y
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CONFIG_TARGET_DEVKIT3250=y
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CONFIG_SPL=y
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# CONFIG_CMD_FPGA is not set
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_DM=y
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@ -21,7 +21,9 @@
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#define CONFIG_SYS_ICACHE_OFF
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#define CONFIG_SYS_DCACHE_OFF
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#if !defined(CONFIG_SPL_BUILD)
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#endif
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#define CONFIG_BOARD_EARLY_INIT_F
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/*
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@ -173,6 +175,57 @@
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#define CONFIG_BOOTARGS "console=ttyS0,115200n8"
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#define CONFIG_LOADADDR 0x80008000
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/*
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* SPL specific defines
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*/
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/* SPL will be executed at offset 0 */
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#define CONFIG_SPL_TEXT_BASE 0x00000000
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/* SPL will use SRAM as stack */
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#define CONFIG_SPL_STACK 0x0000FFF8
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#define CONFIG_SPL_BOARD_INIT
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/* Use the framework and generic lib */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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/* SPL will use serial */
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#define CONFIG_SPL_SERIAL_SUPPORT
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/* SPL loads an image from NAND */
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_NAND_RAW_ONLY
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
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#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
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#define CONFIG_SYS_NAND_ECCSIZE 0x100
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
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48, 49, 50, 51, 52, 53, 54, 55, \
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56, 57, 58, 59, 60, 61, 62, 63, }
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SPL_NAND_ECC
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#define CONFIG_SPL_NAND_SOFTECC
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#define CONFIG_SPL_MAX_SIZE 0x20000
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#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
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/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
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/* See common/spl/spl.c spl_set_header_raw_uboot() */
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#define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE
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/*
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* Include SoC specific configuration
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*/
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