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powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2

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CHASSIS2 architecture never defines type of L2 cache present in SoC.
 it is dependent upon the core present in the SoC.
 for example,
    - e6500 core has L2 cluster (Kibo)
    - e5500 core has Backside L2 Cache

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
This commit is contained in:
Prabhakar Kushwaha 2013-08-29 13:10:38 +05:30 committed by York Sun
parent 0e61077b21
commit e982746844
3 changed files with 5 additions and 5 deletions
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6
arch/powerpc/cpu/mpc85xx/cpu_init.c
View file

@ -284,7 +284,7 @@ static void __fsl_serdes__init(void)
} }
__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
int enable_cluster_l2(void) int enable_cluster_l2(void)
{ {
int i = 0; int i = 0;
@ -350,7 +350,7 @@ int cpu_init_r(void)
#endif #endif
#ifdef CONFIG_L2_CACHE #ifdef CONFIG_L2_CACHE
ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
#endif #endif
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
@ -533,7 +533,7 @@ int cpu_init_r(void)
} }
skip_l2: skip_l2:
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
if (l2cache->l2csr0 & L2CSR0_L2E) if (l2cache->l2csr0 & L2CSR0_L2E)
print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
" enabled\n"); " enabled\n");

2
arch/powerpc/cpu/mpc85xx/fdt.c
View file

@ -273,7 +273,7 @@ static inline void ft_fixup_l2cache(void *blob)
if (has_l2) { if (has_l2) {
#ifdef CONFIG_SYS_CACHE_STASHING #ifdef CONFIG_SYS_CACHE_STASHING
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
/* Only initialize every eighth thread */ /* Only initialize every eighth thread */
if (reg && !((*reg) % 8)) if (reg && !((*reg) % 8))
#else #else

2
arch/powerpc/cpu/mpc85xx/start.S
View file

@ -699,7 +699,7 @@ delete_temp_tlbs:
#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
create_ccsr_l2_tlb: create_ccsr_l2_tlb:
/* /*
* Create a TLB for the MMR location of CCSR * Create a TLB for the MMR location of CCSR