mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
Clean up the TQM8xx_YYMHz configurations; allow to use the same
binary image for all clock frequencies. Implement run-time optimization of flash access timing based on the actual bus frequency.
This commit is contained in:
wdenk
parent
5cf91d6bdc
commit
e9132ea94c
16 changed files with 141 additions and 399 deletions
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@ -2,6 +2,11 @@
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Changes for U-Boot 1.1.1:
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======================================================================
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* Clean up the TQM8xx_YYMHz configurations; allow to use the same
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binary image for all clok frequencies. Implement run-time
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optimization of flash access timing based on the actual bus
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frequency.
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* Modify KUP4X board configuration to use SL811 driver for USB memory
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sticks (including FAT / VFAT filesystem support)
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46
Makefile
46
Makefile
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@ -486,66 +486,26 @@ TOP860_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc8xx top860 emk
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# Play some tricks for configuration selection
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# All boards can come with 50 MHz (default), 66MHz, 80MHz or 100 MHz clock,
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# but only 855 and 860 boards may come with FEC
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# and 823 boards may have LCD support
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xtract_8xx = $(subst _66MHz,,$(subst _80MHz,,$(subst _100MHz,,$(subst _133MHz,,$(subst _LCD,,$(subst _config,,$1))))))
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# Only 855 and 860 boards may come with FEC
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# and only 823 boards may have LCD support
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xtract_8xx = $(subst _LCD,,$(subst _config,,$1))
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FPS850L_config \
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FPS860L_config \
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NSCU_config \
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TQM823L_config \
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TQM823L_66MHz_config \
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TQM823L_80MHz_config \
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TQM823L_LCD_config \
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TQM823L_LCD_66MHz_config \
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TQM823L_LCD_80MHz_config \
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TQM850L_config \
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TQM850L_66MHz_config \
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TQM850L_80MHz_config \
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TQM855L_config \
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TQM855L_66MHz_config \
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TQM855L_80MHz_config \
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TQM860L_config \
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TQM860L_66MHz_config \
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TQM860L_80MHz_config \
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TQM862L_config \
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TQM862L_66MHz_config \
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TQM862L_80MHz_config \
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TQM823M_config \
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TQM823M_66MHz_config \
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TQM823M_80MHz_config \
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TQM850M_config \
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TQM850M_66MHz_config \
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TQM850M_80MHz_config \
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TQM855M_config \
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TQM855M_66MHz_config \
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TQM855M_80MHz_config \
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TQM860M_config \
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TQM860M_66MHz_config \
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TQM860M_80MHz_config \
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TQM862M_config \
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TQM862M_66MHz_config \
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TQM862M_80MHz_config \
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TQM862M_100MHz_config \
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TQM866M_config: unconfig
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@ >include/config.h
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@[ -z "$(findstring _66MHz,$@)" ] || \
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{ echo "#define CONFIG_66MHz" >>include/config.h ; \
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echo "... with 66MHz system clock" ; \
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}
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@[ -z "$(findstring _80MHz,$@)" ] || \
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{ echo "#define CONFIG_80MHz" >>include/config.h ; \
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echo "... with 80MHz system clock" ; \
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}
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@[ -z "$(findstring _100MHz,$@)" ] || \
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{ echo "#define CONFIG_100MHz" >>include/config.h ; \
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echo "... with 100MHz system clock" ; \
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}
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@[ -z "$(findstring _133MHz,$@)" ] || \
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{ echo "#define CONFIG_133MHz" >>include/config.h ; \
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echo "... with 133MHz system clock" ; \
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}
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@[ -z "$(findstring _LCD,$@)" ] || \
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{ echo "#define CONFIG_LCD" >>include/config.h ; \
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echo "#define CONFIG_NEC_NL6448BC20" >>include/config.h ; \
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@ -29,6 +29,15 @@
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#include <mpc8xx.h>
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#include <environment.h>
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#include <asm/processor.h>
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#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
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# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
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# define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
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OR_SCY_2_CLK | OR_EHTR | OR_BI)
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# endif
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#endif /* CONFIG_TQM8xxL/M, !TQM866M */
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#ifndef CFG_ENV_ADDR
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#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
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#endif
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@ -51,6 +60,50 @@ unsigned long flash_init (void)
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unsigned long size_b0, size_b1;
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int i;
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#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ
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int scy, trlx, flash_or_timing, clk_diff;
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DECLARE_GLOBAL_DATA_PTR;
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scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
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if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
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trlx = OR_TRLX;
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scy *= 2;
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} else
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trlx = 0;
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/* We assume that each 10MHz of bus clock require 1-clk SCY
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* adjustment.
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*/
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clk_diff = (gd->bus_clk / 1000000) - 50;
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/* We need proper rounding here. This is what the "+5" and "-5"
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* are here for.
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*/
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if (clk_diff >= 0)
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scy += (clk_diff + 5) / 10;
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else
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scy += (clk_diff - 5) / 10;
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/* For bus frequencies above 50MHz, we want to use relaxed timing
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* (OR_TRLX).
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*/
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if (gd->bus_clk >= 50000000)
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trlx = OR_TRLX;
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else
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trlx = 0;
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if (trlx)
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scy /= 2;
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if (scy > 0xf)
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scy = 0xf;
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if (scy < 1)
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scy = 1;
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flash_or_timing = (scy << 4) | trlx |
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(CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
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#endif
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/* Init: no FLASHes known */
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for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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@ -95,7 +148,11 @@ unsigned long flash_init (void)
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memctl->memc_br1, memctl->memc_or1);
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/* Remap FLASH according to real size */
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#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
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memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
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#else
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memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK);
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#endif
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memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
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debug ("## BR0: 0x%08x OR0: 0x%08x\n",
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@ -146,7 +203,11 @@ unsigned long flash_init (void)
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#endif
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if (size_b1) {
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#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
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memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
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#else
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memctl->memc_or1 = flash_or_timing | (-size_b1 & 0xFFFF8000);
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#endif
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memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
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BR_MS_GPCM | BR_V;
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@ -347,4 +347,32 @@ static long init_pll_866 (long clk)
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#endif /* CONFIG_MPC866_et_al */
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#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
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/*
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* Adjust sdram refresh rate to actual CPU clock
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* and set timebase source according to actual CPU clock
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*/
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int adjust_sdram_tbs_8xx (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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long mamr;
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long sccr;
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mamr = immr->im_memctl.memc_mamr;
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mamr &= ~MAMR_PTA_MSK;
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mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT);
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immr->im_memctl.memc_mamr = mamr;
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if (gd->cpu_clk < 67000000) {
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sccr = immr->im_clkrst.car_sccr;
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sccr |= SCCR_TBS;
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immr->im_clkrst.car_sccr = sccr;
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}
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return (0);
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}
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#endif /* CONFIG_TQM8xxL/M, !TQM866M */
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/* ------------------------------------------------------------------------- */
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@ -372,6 +372,7 @@ int serial_tstc (void);
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int get_clocks (void);
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int get_clocks_866 (void);
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int sdram_adjust_866 (void);
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int adjust_sdram_tbs_8xx (void);
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#if defined(CONFIG_8260)
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int prt_8260_clks (void);
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#endif
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@ -262,15 +262,8 @@
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit
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*
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* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
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*/
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#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
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#define CFG_PLPRCR \
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( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
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#else /* up to 66 MHz we use a 1:1 clock */
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#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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#endif /* CONFIG_80MHz */
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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@ -279,17 +272,9 @@
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
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#define CFG_SCCR (/* SCCR_TBS | */ \
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00)
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#else /* up to 66 MHz we use a 1:1 clock */
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#define CFG_SCCR (SCCR_TBS | \
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00)
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#endif /* CONFIG_80MHz */
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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@ -358,19 +343,8 @@
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/*
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* FLASH timing:
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*/
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#if defined(CONFIG_80MHz)
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/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
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#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
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OR_SCY_3_CLK | OR_EHTR | OR_BI)
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#elif defined(CONFIG_66MHz)
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/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
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#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
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OR_SCY_3_CLK | OR_EHTR | OR_BI)
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#else /* 50 MHz */
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/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
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#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
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OR_SCY_2_CLK | OR_EHTR | OR_BI)
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#endif /*CONFIG_??MHz */
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#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
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@ -431,13 +405,9 @@
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* 66 Mhz => 66.000.000 / Divider = 129
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* 80 Mhz => 80.000.000 / Divider = 156
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*/
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#if defined(CONFIG_80MHz)
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#define CFG_MAMR_PTA 156
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#elif defined(CONFIG_66MHz)
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#define CFG_MAMR_PTA 129
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#else /* 50 MHz */
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#define CFG_MAMR_PTA 98
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#endif /*CONFIG_??MHz */
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#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
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#define CFG_MAMR_PTA 98
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/*
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* For 16 MBit, refresh rates could be 31.3 us
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@ -254,15 +254,8 @@
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit
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*
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* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
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*/
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#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
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#define CFG_PLPRCR \
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( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
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#else /* up to 66 MHz we use a 1:1 clock */
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#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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#endif /* CONFIG_80MHz */
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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@ -271,17 +264,9 @@
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
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#define CFG_SCCR (/* SCCR_TBS | */ \
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00)
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#else /* up to 66 MHz we use a 1:1 clock */
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#define CFG_SCCR (SCCR_TBS | \
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00)
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#endif /* CONFIG_80MHz */
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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@ -350,19 +335,8 @@
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/*
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* FLASH timing:
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*/
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#if defined(CONFIG_80MHz)
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/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
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#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
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OR_SCY_3_CLK | OR_EHTR | OR_BI)
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#elif defined(CONFIG_66MHz)
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/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
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#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
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OR_SCY_3_CLK | OR_EHTR | OR_BI)
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#else /* 50 MHz */
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/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
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#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
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OR_SCY_2_CLK | OR_EHTR | OR_BI)
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#endif /*CONFIG_??MHz */
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#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
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@ -423,13 +397,9 @@
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* 66 Mhz => 66.000.000 / Divider = 129
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* 80 Mhz => 80.000.000 / Divider = 156
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*/
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#if defined(CONFIG_80MHz)
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#define CFG_MAMR_PTA 156
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#elif defined(CONFIG_66MHz)
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#define CFG_MAMR_PTA 129
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#else /* 50 MHz */
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#define CFG_MAMR_PTA 98
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#endif /*CONFIG_??MHz */
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#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
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#define CFG_MAMR_PTA 98
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/*
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* For 16 MBit, refresh rates could be 31.3 us
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@ -245,15 +245,8 @@
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit
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*
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* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
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*/
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#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
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#define CFG_PLPRCR \
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( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
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#else /* up to 66 MHz we use a 1:1 clock */
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#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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#endif /* CONFIG_80MHz */
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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@ -262,17 +255,9 @@
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
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#define CFG_SCCR (/* SCCR_TBS | */ \
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||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
|
|
@ -341,19 +326,8 @@
|
|||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
|
|
@ -414,13 +388,9 @@
|
|||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
|
|
|||
|
|
@ -244,15 +244,8 @@
|
|||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
||||
*/
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
|
|
@ -261,17 +254,9 @@
|
|||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
|
|
@ -340,19 +325,8 @@
|
|||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
|
|
@ -413,13 +387,9 @@
|
|||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
|
|
|||
|
|
@ -248,15 +248,8 @@
|
|||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
||||
*/
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
|
|
@ -265,17 +258,9 @@
|
|||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
|
|
@ -344,19 +329,8 @@
|
|||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
|
|
@ -417,13 +391,9 @@
|
|||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
|
|
|||
|
|
@ -283,15 +283,8 @@
|
|||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
||||
*/
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
|
|
@ -300,17 +293,9 @@
|
|||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
|
|
@ -379,19 +364,8 @@
|
|||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
|
|
@ -452,13 +426,9 @@
|
|||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
|
|
|||
|
|
@ -249,15 +249,8 @@
|
|||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
||||
*/
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
|
|
@ -266,17 +259,9 @@
|
|||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
|
|
@ -345,19 +330,8 @@
|
|||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
|
|
@ -418,13 +392,9 @@
|
|||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
|
|
|||
|
|
@ -250,15 +250,8 @@
|
|||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
||||
*/
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
|
|
@ -267,17 +260,9 @@
|
|||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
|
|
@ -346,19 +331,8 @@
|
|||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
|
|
@ -419,13 +393,9 @@
|
|||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
#if defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
|
|
|||
|
|
@ -252,16 +252,8 @@
|
|||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz or 100 MHz CPU,
|
||||
* set PLL multiplication factor to 5 (5 * 16 = 80, 5 * 20 = 100)
|
||||
*/
|
||||
#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz)
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz | CONFIG_100MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
|
|
@ -270,17 +262,9 @@
|
|||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) /* use 16/20 MHz * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz | CONFIG_100MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
|
|
@ -349,24 +333,8 @@
|
|||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_100MHz)
|
||||
/* 100 MHz CPU - 50 MHz bus:
|
||||
* ACS = 01, TRLX = 0, CSNT = 0, SCY = 7, EHTR = 0 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV4 | OR_SCY_7_CLK | OR_BI)
|
||||
#elif defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus:
|
||||
* ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
|
|
@ -428,15 +396,9 @@
|
|||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
* 100 Mhz => 100.000.000 / Divider = 195
|
||||
*/
|
||||
#if defined(CONFIG_100MHz)
|
||||
#define CFG_MAMR_PTA 195
|
||||
#elif defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
|
|
|||
|
|
@ -253,16 +253,8 @@
|
|||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz or 100 MHz CPU,
|
||||
* set PLL multiplication factor to 5 (5 * 16 = 80, 5 * 20 = 100)
|
||||
*/
|
||||
#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz)
|
||||
#define CFG_PLPRCR \
|
||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
#endif /* CONFIG_80MHz | CONFIG_100MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
|
|
@ -271,17 +263,9 @@
|
|||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#if defined(CONFIG_80MHz) || defined(CONFIG_100MHz) /* use 16/20 MHz * 5 */
|
||||
#define CFG_SCCR (/* SCCR_TBS | */ \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#else /* up to 66 MHz we use a 1:1 clock */
|
||||
#define CFG_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
#endif /* CONFIG_80MHz | CONFIG_100MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
|
|
@ -350,24 +334,8 @@
|
|||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#if defined(CONFIG_100MHz)
|
||||
/* 100 MHz CPU - 50 MHz bus:
|
||||
* ACS = 01, TRLX = 0, CSNT = 0, SCY = 7, EHTR = 0 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV4 | OR_SCY_7_CLK | OR_BI)
|
||||
#elif defined(CONFIG_80MHz)
|
||||
/* 80 MHz CPU - 40 MHz bus:
|
||||
* ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#elif defined(CONFIG_66MHz)
|
||||
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
#else /* 50 MHz */
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
|
|
@ -429,15 +397,9 @@
|
|||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
* 100 Mhz => 100.000.000 / Divider = 195
|
||||
*/
|
||||
#if defined(CONFIG_100MHz)
|
||||
#define CFG_MAMR_PTA 195
|
||||
#elif defined(CONFIG_80MHz)
|
||||
#define CFG_MAMR_PTA 156
|
||||
#elif defined(CONFIG_66MHz)
|
||||
#define CFG_MAMR_PTA 129
|
||||
#else /* 50 MHz */
|
||||
#define CFG_MAMR_PTA 98
|
||||
#endif /*CONFIG_??MHz */
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
|
|
|
|||
|
|
@ -265,6 +265,9 @@ init_fnc_t *init_sequence[] = {
|
|||
|
||||
#if !defined(CONFIG_TQM866M)
|
||||
get_clocks, /* get CPU and bus clocks (etc.) */
|
||||
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
|
||||
adjust_sdram_tbs_8xx,
|
||||
#endif
|
||||
init_timebase,
|
||||
#endif
|
||||
#ifdef CFG_ALLOC_DPRAM
|
||||
|
|
|
|||
Loading…
Reference in a new issue