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arm: dts: sunxi: update H3 to new EMAC binding

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The U-Boot driver for the sun8i-emac was using some preliminary DT
binding. Now since Linux got its own driver in v4.15 and our driver
can now cope with both bindings, let's convert the DT nodes used by the
various H3 boards over to the new bindings used by the kernel.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
Andre Przywara 2018-04-04 01:31:18 +01:00 committed by Jagan Teki
parent 06a57f656b
commit e88d2a57f3
9 changed files with 75 additions and 51 deletions
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6
arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts
View file

@ -100,14 +100,10 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,use-internal-phy;
allwinner,leds-active-low;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {

7
arch/arm/dts/sun8i-h3-libretech-all-h3-cc.dts
View file

@ -125,15 +125,10 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,use-internal-phy;
allwinner,leds-active-low;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&ir {

6
arch/arm/dts/sun8i-h3-nanopi-neo.dts
View file

@ -48,12 +48,8 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,use-internal-phy;
allwinner,leds-active-low;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};

7
arch/arm/dts/sun8i-h3-orangepi-2.dts
View file

@ -55,6 +55,7 @@
aliases {
serial0 = &uart0;
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
ethernet0 = &emac;
ethernet1 = &rtl8189;
};
@ -110,14 +111,10 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,use-internal-phy;
allwinner,leds-active-low;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&ir {

7
arch/arm/dts/sun8i-h3-orangepi-one.dts
View file

@ -53,6 +53,7 @@
compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
@ -95,14 +96,10 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,use-internal-phy;
allwinner,leds-active-low;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {

7
arch/arm/dts/sun8i-h3-orangepi-pc.dts
View file

@ -53,6 +53,7 @@
compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
@ -167,12 +168,8 @@
};
&emac {
phy = <&phy1>;
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,use-internal-phy;
allwinner,leds-active-low;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};

8
arch/arm/dts/sun8i-h3-orangepi-plus.dts
View file

@ -82,7 +82,13 @@
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-mode = "rgmii";
/delete-property/allwinner,use-internal-phy;
};
&external_mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
&mmc2 {

9
arch/arm/dts/sun8i-h3-orangepi-plus2e.dts
View file

@ -69,8 +69,15 @@
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
/delete-property/allwinner,use-internal-phy;
};
&external_mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&pio {

69
arch/arm/dts/sun8i-h3.dtsi
View file

@ -144,9 +144,10 @@
#size-cells = <1>;
ranges;
syscon: syscon@01c00000 {
compatible = "allwinner,sun8i-h3-syscon","syscon";
reg = <0x01c00000 0x34>;
syscon: syscon@1c00000 {
compatible = "allwinner,sun8i-h3-system-controller",
"syscon";
reg = <0x01c00000 0x1000>;
};
dma: dma-controller@01c02000 {
@ -339,15 +340,12 @@
interrupt-controller;
#interrupt-cells = <3>;
emac_rgmii_pins: emac0@0 {
allwinner,pins = "PD0", "PD1", "PD2", "PD3",
"PD4", "PD5", "PD7",
"PD8", "PD9", "PD10",
"PD12", "PD13", "PD15",
"PD16", "PD17";
allwinner,function = "emac";
allwinner,drive = <SUN4I_PINCTRL_40_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
emac_rgmii_pins: emac0 {
pins = "PD0", "PD1", "PD2", "PD3", "PD4",
"PD5", "PD7", "PD8", "PD9", "PD10",
"PD12", "PD13", "PD15", "PD16", "PD17";
function = "emac";
drive-strength = <40>;
};
mmc0_pins_a: mmc0@0 {
@ -466,16 +464,51 @@
emac: ethernet@1c30000 {
compatible = "allwinner,sun8i-h3-emac";
reg = <0x01c30000 0x104>, <0x01c00030 0x4>;
reg-names = "emac", "syscon";
syscon = <&syscon>;
reg = <0x01c30000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ccu RST_BUS_EMAC>, <&ccu RST_BUS_EPHY>;
reset-names = "ahb", "ephy";
clocks = <&ccu CLK_BUS_EMAC>, <&ccu CLK_BUS_EPHY>;
clock-names = "ahb", "ephy";
interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC>;
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
};
mdio-mux {
compatible = "allwinner,sun8i-h3-mdio-mux";
#address-cells = <1>;
#size-cells = <0>;
mdio-parent-bus = <&mdio>;
/* Only one MDIO is usable at the time */
internal_mdio: mdio@1 {
compatible = "allwinner,sun8i-h3-mdio-internal";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
int_mii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
clocks = <&ccu CLK_BUS_EPHY>;
resets = <&ccu RST_BUS_EPHY>;
};
};
external_mdio: mdio@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
gic: interrupt-controller@01c81000 {