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Merge with git+ssh://sr@pollux.denx.org/home/sr/git/u-boot/denx/.git

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This commit is contained in:
Stefan Roese 2007-02-03 07:53:41 +01:00
commit e7511c266f
44 changed files with 3657 additions and 1132 deletions
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43
CHANGELOG
View file

@ -1,3 +1,46 @@
commit 6bd2447ee47ee23c18d2b3c7ccd5a20f7626f5b3
Author: Gary Jennejohn <garyj@pollux.denx.de>
Date: Wed Jan 24 12:16:56 2007 +0100
Add port for the lpc2292sodimm evaluation board from EmbeddedArtists
commit 2daf046ba627f85f44195815778140039636244e
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Tue Jan 23 17:22:06 2007 +0100
[iDMR] Add MTD and JFFS2 support, also add default partition definition.
commit f7db33101fbc9c8f0a10738ce87034875a17aeb9
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Tue Jan 23 14:21:14 2007 +0100
[iDMR] Flash driver on initialisation write-protects some sectors,
currently sectors 0-3. Sector 3 does not need to be protected, though
(U-boot occupies sectors 0-1 and the environment sector 2). This commit
fixes this, i.e., only sectors 0-2 are protected.
commit 0ed47bb119cd2c4c16edb2548789148f9e6dc9de
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Tue Jan 23 14:11:22 2007 +0100
[iDMR] Using MII-related commands on iDRM board doesn't work now (e.g.,
"mii device" results in "Unexpected exception"). Fixing this properly
requires some clean-up in the FEC drivers infrastructure for ColdFire, so
this commit disables MII commads for now.
commit 363d1d8f9c99b63daef81f5985cab3fc00edde5c
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Tue Jan 23 13:25:22 2007 +0100
[ColdFire MCF5271 family] Add CPU detection based on the value of Chip
Identification Register (CIR).
commit a4012396645533aef218354eeba754dff0deace8
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Fri Jan 19 23:08:39 2007 +0100
Minor code cleanup.
commit f539b7ba7d7ef6dd187c8209609001cb1cd95e39
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Fri Jan 19 19:57:10 2007 +0100

1
MAINTAINERS
View file

@ -28,6 +28,7 @@ Pantelis Antoniou <panto@intracom.gr>
Reinhard Arlt <reinhard.arlt@esd-electronics.com>
cpci5200 MPC5200
mecp5200 MPC5200
pf5200 MPC5200
CPCI750 PPC750FX/GX

8
MAKEALL
View file

@ -37,9 +37,9 @@ LIST_5xx=" \
LIST_5xxx=" \
BC3450 cpci5200 EVAL5200 fo300 \
icecube_5100 icecube_5200 lite5200b mcc200 \
o2dnt pf5200 PM520 TB5200 \
Total5100 Total5200 Total5200_Rev2 TQM5200 \
TQM5200_B TQM5200S v38b \
mecp5200 o2dnt pf5200 PM520 \
TB5200 Total5100 Total5200 Total5200_Rev2 \
TQM5200 TQM5200_B TQM5200S v38b \
"
#########################################################################
@ -181,7 +181,7 @@ LIST_SA="assabet dnp1110 gcplus lart shannon"
LIST_ARM7=" \
armadillo B2 ep7312 evb4510 \
impa7 integratorap ap7 ap720t \
modnet50 \
lpc2292sodimm modnet50 \
"
#########################################################################

11
Makefile
View file

@ -482,6 +482,9 @@ prs200_highboot_DDR_config: unconfig
}
@$(MKCONFIG) -n $@ -a mcc200 ppc mpc5xxx mcc200
mecp5200_config: unconfig
@$(MKCONFIG) -a mecp5200 ppc mpc5xxx mecp5200 esd
o2dnt_config:
@$(MKCONFIG) o2dnt ppc mpc5xxx o2dnt
@ -1236,7 +1239,10 @@ yosemite_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx yosemite amcc
yellowstone_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx yellowstone amcc
@mkdir -p $(obj)include
@echo "#define CONFIG_YELLOWSTONE" > $(obj)include/config.h
@echo "Configuring for yellowstone board as subset of yosemite..."
@$(MKCONFIG) -a yosemite ppc ppc4xx yosemite amcc
yucca_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx yucca amcc
@ -2029,6 +2035,9 @@ modnet50_config : unconfig
evb4510_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm720t evb4510
lpc2292sodimm_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm720t lpc2292sodimm
#########################################################################
## XScale Systems
#########################################################################

112
board/amcc/yellowstone/init.S
View file

@ -1,112 +0,0 @@
/*
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <config.h>
/* General */
#define TLB_VALID 0x00000200
/* Supported page sizes */
#define SZ_1K 0x00000000
#define SZ_4K 0x00000010
#define SZ_16K 0x00000020
#define SZ_64K 0x00000030
#define SZ_256K 0x00000040
#define SZ_1M 0x00000050
#define SZ_8M 0x00000060
#define SZ_16M 0x00000070
#define SZ_256M 0x00000090
/* Storage attributes */
#define SA_W 0x00000800 /* Write-through */
#define SA_I 0x00000400 /* Caching inhibited */
#define SA_M 0x00000200 /* Memory coherence */
#define SA_G 0x00000100 /* Guarded */
#define SA_E 0x00000080 /* Endian */
/* Access control */
#define AC_X 0x00000024 /* Execute */
#define AC_W 0x00000012 /* Write */
#define AC_R 0x00000009 /* Read */
/* Some handy macros */
#define EPN(e) ((e) & 0xfffffc00)
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
#define TLB2(a) ( (a)&0x00000fbf )
#define tlbtab_start\
mflr r1 ;\
bl 0f ;
#define tlbtab_end\
.long 0, 0, 0 ; \
0: mflr r0 ; \
mtlr r1 ; \
blr ;
#define tlbentry(epn,sz,rpn,erpn,attr)\
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
/* PCI */
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
/* USB 2.0 Device */
tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
tlbtab_end

549
board/amcc/yellowstone/yellowstone.c
View file

@ -1,549 +0,0 @@
/*
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#include <spd_sdram.h>
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
int board_early_init_f(void)
{
register uint reg;
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
mtdcr(ebccfga, xbcfg);
reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
/*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
/*CPLD cs */
/*setup Address lines for flash size 64Meg. */
out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
/*setup emac */
out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
/*UART1 */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
/* external interrupts IRQ0...3 */
out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
#if 0 /* test-only */
/*setup USB 2.0 */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
#endif
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup other serial configuration
*-------------------------------------------------------------------*/
mfsdr(sdr_pci0, reg);
mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
/*clear tmrclk divisor */
*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
/*enable ethernet */
*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
#if 0 /* test-only */
/*enable usb 1.1 fs device and remove usb 2.0 reset */
*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
#endif
/*get rid of flash write protect */
*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
return 0;
}
int misc_init_r (void)
{
uint pbcr;
int size_val = 0;
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
switch (gd->bd->bi_flashsize) {
case 1 << 20:
size_val = 0;
break;
case 2 << 20:
size_val = 1;
break;
case 4 << 20:
size_val = 2;
break;
case 8 << 20:
size_val = 3;
break;
case 16 << 20:
size_val = 4;
break;
case 32 << 20:
size_val = 5;
break;
case 64 << 20:
size_val = 6;
break;
case 128 << 20:
size_val = 7;
break;
}
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtdcr(ebccfga, pb0cr);
mtdcr(ebccfgd, pbcr);
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-CFG_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
return 0;
}
int checkboard(void)
{
char *s = getenv("serial#");
u8 rev;
u8 val;
printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
rev = *(u8 *)(CFG_CPLD + 0);
val = *(u8 *)(CFG_CPLD + 5) & 0x01;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
return (0);
}
/*************************************************************************
* sdram_init -- doesn't use serial presence detect.
*
* Assumes: 256 MB, ECC, non-registered
* PLB @ 133 MHz
*
************************************************************************/
#define NUM_TRIES 64
#define NUM_READS 10
void sdram_tr1_set(int ram_address, int* tr1_value)
{
int i;
int j, k;
volatile unsigned int* ram_pointer = (unsigned int*)ram_address;
int first_good = -1, last_bad = 0x1ff;
unsigned long test[NUM_TRIES] = {
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
/* go through all possible SDRAM0_TR1[RDCT] values */
for (i=0; i<=0x1ff; i++) {
/* set the current value for TR1 */
mtsdram(mem_tr1, (0x80800800 | i));
/* write values */
for (j=0; j<NUM_TRIES; j++) {
ram_pointer[j] = test[j];
/* clear any cache at ram location */
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
}
/* read values back */
for (j=0; j<NUM_TRIES; j++) {
for (k=0; k<NUM_READS; k++) {
/* clear any cache at ram location */
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
if (ram_pointer[j] != test[j])
break;
}
/* read error */
if (k != NUM_READS) {
break;
}
}
/* we have a SDRAM0_TR1[RDCT] that is part of the window */
if (j == NUM_TRIES) {
if (first_good == -1)
first_good = i; /* found beginning of window */
} else { /* bad read */
/* if we have not had a good read then don't care */
if(first_good != -1) {
/* first failure after a good read */
last_bad = i-1;
break;
}
}
}
/* return the current value for TR1 */
*tr1_value = (first_good + last_bad) / 2;
}
void sdram_init(void)
{
register uint reg;
int tr1_bank1, tr1_bank2;
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(mem_clktr, 0x40000000); /* ?? */
mtsdram(mem_wddctr, 0x40000000); /* ?? */
/*clear this first, if the DDR is enabled by a debugger
then you can not make changes. */
mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
*------------------------------------------------------------------*/
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
mtsdram(mem_tr0, 0x410a4012); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram(mem_cfg0, 0x80000000); /* Enable */
for (;;) {
mfsdram(mem_mcsts, reg);
if (reg & 0x80000000)
break;
}
sdram_tr1_set(0x00000000, &tr1_bank1);
sdram_tr1_set(0x08000000, &tr1_bank2);
mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
}
/*************************************************************************
* long int initdram
*
************************************************************************/
long int initdram(int board)
{
sdram_init();
return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_KBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
* Set up Direct MMIO registers
*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------+
| PowerPC440 EP PCI Master configuration.
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers
*--------------------------------------------------------------------------*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
CFG_PCI_SUBSYS_VENDORID);
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
/* Configure command register as bus master */
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
/* 240nS PCI clock */
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
/* No error reporting */
pci_write_config_word(0, PCI_ERREN, 0);
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
/*************************************************************************
* pci_master_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
/*--------------------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs.
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
+--------------------------------------------------------------------------*/
pci_read_config_word(0, PCI_COMMAND, &temp_short);
pci_write_config_word(0, PCI_COMMAND,
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* Bamboo is always configured as host. */
return (1);
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* hw_watchdog_reset
*
* This routine is called to reset (keep alive) the watchdog timer
*
************************************************************************/
#if defined(CONFIG_HW_WATCHDOG)
void hw_watchdog_reset(void)
{
}
#endif
void board_reset(void)
{
/* give reset to BCSR */
*(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09;
}

8
board/amcc/yosemite/yosemite.c
View file

@ -65,12 +65,14 @@ int board_early_init_f(void)
out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
#ifdef CONFIG_440EP
/*setup USB 2.0 */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
#endif
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
@ -105,8 +107,10 @@ int board_early_init_f(void)
/*enable ethernet */
*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
#ifdef CONFIG_440EP
/*enable usb 1.1 fs device and remove usb 2.0 reset */
*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
#endif
/*get rid of flash write protect */
*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
@ -171,7 +175,11 @@ int checkboard(void)
u8 rev;
u8 val;
#ifdef CONFIG_440EP
printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
#else
printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
#endif
rev = *(u8 *)(CFG_CPLD + 0);
val = *(u8 *)(CFG_CPLD + 5) & 0x01;

22
board/esd/cpci750/cpci750.c
View file

@ -29,6 +29,7 @@
*/
#include <common.h>
#include <command.h>
#include <74xx_7xx.h>
#include "../../Marvell/include/memory.h"
#include "../../Marvell/include/pci.h"
@ -899,3 +900,24 @@ void board_prebootm_init ()
flush_data_cache ();
dcache_disable ();
}
int do_show_cfg(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
unsigned int reset_sample_low;
unsigned int reset_sample_high;
GT_REG_READ(0x3c4, &reset_sample_low);
GT_REG_READ(0x3d4, &reset_sample_high);
printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
return(0);
}
U_BOOT_CMD(
show_cfg, 1, 1, do_show_cfg,
"show_cfg- Show Marvell strapping register\n",
"Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n"
);

43
board/esd/cpci750/sdram_init.c
View file

@ -1504,6 +1504,8 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
/* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
{
int l, l1;
i = info->slot;
DP (printf
("\n*** Running a MRS cycle for bank %d ***\n", i));
@ -1511,20 +1513,39 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info)
/* map the bank */
memory_map_bank (i, 0, GB / 4);
#if 1 /* test only */
/* set SDRAM mode */ /* To_do check it */
GT_REG_WRITE (SDRAM_OPERATION, 0x3);
check = GTREGREAD (SDRAM_OPERATION);
DP (printf
("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
check));
tmp = GTREGREAD (SDRAM_MODE);
GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0);
GT_REG_WRITE (SDRAM_OPERATION, 0x4);
while (GTREGREAD (SDRAM_OPERATION) != 0) {
DP (printf
("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
}
GT_REG_WRITE (SDRAM_MODE, tmp | 0x80);
GT_REG_WRITE (SDRAM_OPERATION, 0x3);
while (GTREGREAD (SDRAM_OPERATION) != 0) {
DP (printf
("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
}
l1 = 0;
for (l=0;l<200;l++)
l1 += GTREGREAD (SDRAM_OPERATION);
GT_REG_WRITE (SDRAM_MODE, tmp);
GT_REG_WRITE (SDRAM_OPERATION, 0x3);
while (GTREGREAD (SDRAM_OPERATION) != 0) {
DP (printf
("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
}
/* switch back to normal operation mode */
GT_REG_WRITE (SDRAM_OPERATION, 0);
check = GTREGREAD (SDRAM_OPERATION);
DP (printf
("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
check));
GT_REG_WRITE (SDRAM_OPERATION, 0x5);
while (GTREGREAD (SDRAM_OPERATION) != 0) {
DP (printf
("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"));
}
#endif /* test only */
/* unmap the bank */
memory_map_bank (i, 0, 0);

6
board/amcc/yellowstone/Makefile → board/esd/mecp5200/Makefile
View file

@ -1,5 +1,6 @@
#
# (C) Copyright 2002-2006
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@ -26,13 +27,12 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:

44
board/esd/mecp5200/config.mk Normal file
View file

@ -0,0 +1,44 @@
#
# (C) Copyright 2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# IceCube board:
#
# Valid values for TEXT_BASE are:
#
# 0xFFF00000 boot high (standard configuration)
# 0xFF000000 boot low for 16 MiB boards
# 0xFF800000 boot low for 8 MiB boards
# 0x00100000 boot from RAM (for testing only)
#
sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
## Standard: boot high
TEXT_BASE = 0xFFF00000
## For testing: boot from RAM
# TEXT_BASE = 0x00100000
endif
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board

261
board/esd/mecp5200/mecp5200.c Normal file
View file

@ -0,0 +1,261 @@
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* pf5200.c - main board support/init for the esd pf5200.
*/
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
#include <command.h>
#include "mt46v16m16-75.h"
void init_power_switch(void);
static void sdram_start(int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
*(vu_long *) MPC5XXX_SDRAM_CTRL =
SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
__asm__ volatile ("sync");
/* precharge all banks */
*(vu_long *) MPC5XXX_SDRAM_CTRL =
SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
/* set mode register: extended mode */
*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
__asm__ volatile ("sync");
/* set mode register: reset DLL */
*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
__asm__ volatile ("sync");
/* precharge all banks */
*(vu_long *) MPC5XXX_SDRAM_CTRL =
SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
/* auto refresh */
*(vu_long *) MPC5XXX_SDRAM_CTRL =
SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
__asm__ volatile ("sync");
/* set mode register */
*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
__asm__ volatile ("sync");
/* normal operation */
*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
__asm__ volatile ("sync");
}
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
* is something else than 0x00000000.
*/
long int initdram(int board_type)
{
ulong dramsize = 0;
ulong test1, test2;
/* setup SDRAM chip selects */
*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
__asm__ volatile ("sync");
/* setup config registers */
*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
__asm__ volatile ("sync");
/* set tap delay */
*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
__asm__ volatile ("sync");
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
test1 = get_ram_size(CFG_SDRAM_BASE, 0x80000000);
sdram_start(1);
test2 = get_ram_size(CFG_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
} else {
dramsize = test2;
}
/* memory smaller than 1MB is impossible */
if (dramsize < (1 << 20))
dramsize = 0;
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0) {
*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
0x13 + __builtin_ffs(dramsize >> 20) - 1;
/* let SDRAM CS1 start right after CS0 */
*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
} else {
#if 0
*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
/* let SDRAM CS1 start right after CS0 */
*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e; /* 2G */
#else
*(vu_long *) MPC5XXX_SDRAM_CS0CFG =
0x13 + __builtin_ffs(0x08000000 >> 20) - 1;
/* let SDRAM CS1 start right after CS0 */
*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x08000000 + 0x0000001e; /* 2G */
#endif
}
#if 0
/* find RAM size using SDRAM CS1 only */
sdram_start(0);
get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(1);
get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(0);
#endif
/* set SDRAM CS1 size according to the amount of RAM found */
*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
init_power_switch();
return (dramsize);
}
int checkboard(void)
{
puts("Board: esd CPX CPU5200 (mecp5200)\n");
return 0;
}
void flash_preinit(void)
{
/*
* Now, when we are in RAM, enable flash write
* access for detection process.
* Note that CS_BOOT cannot be cleared when
* executing in flash.
*/
*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}
void flash_afterinit(ulong size)
{
if (size == CFG_FLASH_SIZE) {
/* adjust mapping */
*(vu_long *) MPC5XXX_BOOTCS_START =
*(vu_long *) MPC5XXX_CS0_START =
START_REG(CFG_BOOTCS_START | size);
*(vu_long *) MPC5XXX_BOOTCS_STOP =
*(vu_long *) MPC5XXX_CS0_STOP =
STOP_REG(CFG_BOOTCS_START | size, size);
}
}
#ifdef CONFIG_PCI
static struct pci_controller hose;
extern void pci_mpc5xxx_init(struct pci_controller *);
void pci_init_board(void)
{
pci_mpc5xxx_init(&hose);
}
#endif
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
#define GPIO_PSC1_4 0x01000000UL
void init_ide_reset(void)
{
debug("init_ide_reset\n");
/* Configure PSC1_4 as GPIO output for ATA reset */
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
}
void ide_set_reset(int idereset)
{
debug("ide_reset(%d)\n", idereset);
if (idereset)
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
else
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
}
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
#define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004)
#define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C)
#define MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x0010)
#define MPC5XXX_SIMPLEIO_GPIO_DATA_INPUT (MPC5XXX_GPIO + 0x0014)
#define MPC5XXX_INTERRUPT_GPIO_ENABLE (MPC5XXX_GPIO + 0x0020)
#define MPC5XXX_INTERRUPT_GPIO_DIR (MPC5XXX_GPIO + 0x0028)
#define MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT (MPC5XXX_GPIO + 0x002C)
#define MPC5XXX_INTERRUPT_GPIO_STATUS (MPC5XXX_GPIO + 0x003C)
#define GPIO_WU6 0x40000000UL
#define GPIO_USB0 0x00010000UL
#define GPIO_USB9 0x08000000UL
#define GPIO_USB9S 0x00080000UL
void init_power_switch(void)
{
debug("init_power_switch\n");
/* Configure GPIO_WU6 as GPIO output for ATA reset */
*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6;
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6;
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6;
__asm__ volatile ("sync");
*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT &= ~GPIO_USB0;
*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_ENABLE |= GPIO_USB0;
*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DIR |= GPIO_USB0;
__asm__ volatile ("sync");
*(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9;
*(vu_long *) MPC5XXX_INTERRUPT_GPIO_ENABLE &= ~GPIO_USB9;
__asm__ volatile ("sync");
if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) {
*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
__asm__ volatile ("sync");
}
}

37
board/esd/mecp5200/mt46v16m16-75.h Normal file
View file

@ -0,0 +1,37 @@
/*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define SDRAM_DDR 1 /* is DDR */
#if defined(CONFIG_MPC5200)
/* Settings for XLB = 132 MHz */
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONTROL 0x705f0f00
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
#else
#error CONFIG_MPC5200 not defined
#endif

51
board/amcc/yellowstone/u-boot.lds → board/esd/mecp5200/u-boot.lds
View file

@ -1,5 +1,5 @@
/*
* (C) Copyright 2002
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -27,16 +27,6 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
@ -63,44 +53,21 @@ SECTIONS
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/yellowstone/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
cpu/mpc5xxx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
@ -111,8 +78,8 @@ SECTIONS
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
.data :
{
@ -126,22 +93,20 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
. = ALIGN(4096);
__init_end = .;
__bss_start = .;

58
board/lpc2292sodimm/Makefile Normal file
View file

@ -0,0 +1,58 @@
#
# (C) Copyright 2002
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
# Marius Groeger <mgroeger@sysgo.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := lpc2292sodimm.o flash.o mmc.o spi.o mmc_hw.o eth.o
SOBJS := lowlevel_init.o iap_entry.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
# this MUST be compiled as thumb code!
iap_entry.o:
arm-linux-gcc -D__ASSEMBLY__ -g -Os -fno-strict-aliasing \
-fno-common -ffixed-r8 -msoft-float -D__KERNEL__ \
-DTEXT_BASE=0x81500000 -I/home/garyj/proj/LPC/u-boot/include \
-fno-builtin -ffreestanding -nostdinc -isystem \
/opt/eldk/arm/usr/bin/../lib/gcc/arm-linux/4.0.0/include -pipe \
-DCONFIG_ARM -D__ARM__ -march=armv4t -mtune=arm7tdmi -mabi=apcs-gnu \
-c -o iap_entry.o iap_entry.S
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

30
board/amcc/yellowstone/config.mk → board/lpc2292sodimm/config.mk
View file

@ -1,5 +1,9 @@
#
# (C) Copyright 2002
# (C) Copyright 2000
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
# Marius Groeger <mgroeger@sysgo.de>
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@ -21,24 +25,6 @@
# MA 02111-1307 USA
#
#
# esd ADCIOP boards
#
#TEXT_BASE = 0x00001000
ifeq ($(ramsym),1)
TEXT_BASE = 0xFBD00000
else
TEXT_BASE = 0xFFF80000
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
endif
#address where u-boot will be relocated
#TEXT_BASE = 0x0
TEXT_BASE = 0x81500000

885
board/lpc2292sodimm/eth.c Normal file
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@ -0,0 +1,885 @@
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <net.h>
#include <asm/arch/hardware.h>
#include "spi.h"
/*
* Control Registers in Bank 0
*/
#define CTL_REG_ERDPTL 0x00
#define CTL_REG_ERDPTH 0x01
#define CTL_REG_EWRPTL 0x02
#define CTL_REG_EWRPTH 0x03
#define CTL_REG_ETXSTL 0x04
#define CTL_REG_ETXSTH 0x05
#define CTL_REG_ETXNDL 0x06
#define CTL_REG_ETXNDH 0x07
#define CTL_REG_ERXSTL 0x08
#define CTL_REG_ERXSTH 0x09
#define CTL_REG_ERXNDL 0x0A
#define CTL_REG_ERXNDA 0x0B
#define CTL_REG_ERXRDPTL 0x0C
#define CTL_REG_ERXRDPTH 0x0D
#define CTL_REG_ERXWRPTL 0x0E
#define CTL_REG_ERXWRPTH 0x0F
#define CTL_REG_EDMASTL 0x10
#define CTL_REG_EDMASTH 0x11
#define CTL_REG_EDMANDL 0x12
#define CTL_REG_EDMANDH 0x13
#define CTL_REG_EDMADSTL 0x14
#define CTL_REG_EDMADSTH 0x15
#define CTL_REG_EDMACSL 0x16
#define CTL_REG_EDMACSH 0x17
/* these are common in all banks */
#define CTL_REG_EIE 0x1B
#define CTL_REG_EIR 0x1C
#define CTL_REG_ESTAT 0x1D
#define CTL_REG_ECON2 0x1E
#define CTL_REG_ECON1 0x1F
/*
* Control Registers in Bank 1
*/
#define CTL_REG_EHT0 0x00
#define CTL_REG_EHT1 0x01
#define CTL_REG_EHT2 0x02
#define CTL_REG_EHT3 0x03
#define CTL_REG_EHT4 0x04
#define CTL_REG_EHT5 0x05
#define CTL_REG_EHT6 0x06
#define CTL_REG_EHT7 0x07
#define CTL_REG_EPMM0 0x08
#define CTL_REG_EPMM1 0x09
#define CTL_REG_EPMM2 0x0A
#define CTL_REG_EPMM3 0x0B
#define CTL_REG_EPMM4 0x0C
#define CTL_REG_EPMM5 0x0D
#define CTL_REG_EPMM6 0x0E
#define CTL_REG_EPMM7 0x0F
#define CTL_REG_EPMCSL 0x10
#define CTL_REG_EPMCSH 0x11
#define CTL_REG_EPMOL 0x14
#define CTL_REG_EPMOH 0x15
#define CTL_REG_EWOLIE 0x16
#define CTL_REG_EWOLIR 0x17
#define CTL_REG_ERXFCON 0x18
#define CTL_REG_EPKTCNT 0x19
/*
* Control Registers in Bank 2
*/
#define CTL_REG_MACON1 0x00
#define CTL_REG_MACON2 0x01
#define CTL_REG_MACON3 0x02
#define CTL_REG_MACON4 0x03
#define CTL_REG_MABBIPG 0x04
#define CTL_REG_MAIPGL 0x06
#define CTL_REG_MAIPGH 0x07
#define CTL_REG_MACLCON1 0x08
#define CTL_REG_MACLCON2 0x09
#define CTL_REG_MAMXFLL 0x0A
#define CTL_REG_MAMXFLH 0x0B
#define CTL_REG_MAPHSUP 0x0D
#define CTL_REG_MICON 0x11
#define CTL_REG_MICMD 0x12
#define CTL_REG_MIREGADR 0x14
#define CTL_REG_MIWRL 0x16
#define CTL_REG_MIWRH 0x17
#define CTL_REG_MIRDL 0x18
#define CTL_REG_MIRDH 0x19
/*
* Control Registers in Bank 3
*/
#define CTL_REG_MAADR1 0x00
#define CTL_REG_MAADR0 0x01
#define CTL_REG_MAADR3 0x02
#define CTL_REG_MAADR2 0x03
#define CTL_REG_MAADR5 0x04
#define CTL_REG_MAADR4 0x05
#define CTL_REG_EBSTSD 0x06
#define CTL_REG_EBSTCON 0x07
#define CTL_REG_EBSTCSL 0x08
#define CTL_REG_EBSTCSH 0x09
#define CTL_REG_MISTAT 0x0A
#define CTL_REG_EREVID 0x12
#define CTL_REG_ECOCON 0x15
#define CTL_REG_EFLOCON 0x17
#define CTL_REG_EPAUSL 0x18
#define CTL_REG_EPAUSH 0x19
/*
* PHY Register
*/
#define PHY_REG_PHID1 0x02
#define PHY_REG_PHID2 0x03
/*
* Receive Filter Register (ERXFCON) bits
*/
#define ENC_RFR_UCEN 0x80
#define ENC_RFR_ANDOR 0x40
#define ENC_RFR_CRCEN 0x20
#define ENC_RFR_PMEN 0x10
#define ENC_RFR_MPEN 0x08
#define ENC_RFR_HTEN 0x04
#define ENC_RFR_MCEN 0x02
#define ENC_RFR_BCEN 0x01
/*
* ECON1 Register Bits
*/
#define ENC_ECON1_TXRST 0x80
#define ENC_ECON1_RXRST 0x40
#define ENC_ECON1_DMAST 0x20
#define ENC_ECON1_CSUMEN 0x10
#define ENC_ECON1_TXRTS 0x08
#define ENC_ECON1_RXEN 0x04
#define ENC_ECON1_BSEL1 0x02
#define ENC_ECON1_BSEL0 0x01
/*
* ECON2 Register Bits
*/
#define ENC_ECON2_AUTOINC 0x80
#define ENC_ECON2_PKTDEC 0x40
#define ENC_ECON2_PWRSV 0x20
#define ENC_ECON2_VRPS 0x08
/*
* EIR Register Bits
*/
#define ENC_EIR_PKTIF 0x40
#define ENC_EIR_DMAIF 0x20
#define ENC_EIR_LINKIF 0x10
#define ENC_EIR_TXIF 0x08
#define ENC_EIR_WOLIF 0x04
#define ENC_EIR_TXERIF 0x02
#define ENC_EIR_RXERIF 0x01
/*
* ESTAT Register Bits
*/
#define ENC_ESTAT_INT 0x80
#define ENC_ESTAT_LATECOL 0x10
#define ENC_ESTAT_RXBUSY 0x04
#define ENC_ESTAT_TXABRT 0x02
#define ENC_ESTAT_CLKRDY 0x01
/*
* EIE Register Bits
*/
#define ENC_EIE_INTIE 0x80
#define ENC_EIE_PKTIE 0x40
#define ENC_EIE_DMAIE 0x20
#define ENC_EIE_LINKIE 0x10
#define ENC_EIE_TXIE 0x08
#define ENC_EIE_WOLIE 0x04
#define ENC_EIE_TXERIE 0x02
#define ENC_EIE_RXERIE 0x01
/*
* MACON1 Register Bits
*/
#define ENC_MACON1_LOOPBK 0x10
#define ENC_MACON1_TXPAUS 0x08
#define ENC_MACON1_RXPAUS 0x04
#define ENC_MACON1_PASSALL 0x02
#define ENC_MACON1_MARXEN 0x01
/*
* MACON2 Register Bits
*/
#define ENC_MACON2_MARST 0x80
#define ENC_MACON2_RNDRST 0x40
#define ENC_MACON2_MARXRST 0x08
#define ENC_MACON2_RFUNRST 0x04
#define ENC_MACON2_MATXRST 0x02
#define ENC_MACON2_TFUNRST 0x01
/*
* MACON3 Register Bits
*/
#define ENC_MACON3_PADCFG2 0x80
#define ENC_MACON3_PADCFG1 0x40
#define ENC_MACON3_PADCFG0 0x20
#define ENC_MACON3_TXCRCEN 0x10
#define ENC_MACON3_PHDRLEN 0x08
#define ENC_MACON3_HFRMEN 0x04
#define ENC_MACON3_FRMLNEN 0x02
#define ENC_MACON3_FULDPX 0x01
/*
* MICMD Register Bits
*/
#define ENC_MICMD_MIISCAN 0x02
#define ENC_MICMD_MIIRD 0x01
/*
* MISTAT Register Bits
*/
#define ENC_MISTAT_NVALID 0x04
#define ENC_MISTAT_SCAN 0x02
#define ENC_MISTAT_BUSY 0x01
/*
* PHID1 and PHID2 values
*/
#define ENC_PHID1_VALUE 0x0083
#define ENC_PHID2_VALUE 0x1400
#define ENC_PHID2_MASK 0xFC00
#define ENC_SPI_SLAVE_CS 0x00010000 /* pin P1.16 */
#define ENC_RESET 0x00020000 /* pin P1.17 */
#define FAILSAFE_VALUE 5000
/*
* Controller memory layout:
*
* 0x0000 - 0x17ff 6k bytes receive buffer
* 0x1800 - 0x1fff 2k bytes transmit buffer
*/
/* Use the lower memory for receiver buffer. See errata pt. 5 */
#define ENC_RX_BUF_START 0x0000
#define ENC_TX_BUF_START 0x1800
/* maximum frame length */
#define ENC_MAX_FRM_LEN 1518
#define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS)
#define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS)
#define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8);
static unsigned char encReadReg (unsigned char regNo);
static void encWriteReg (unsigned char regNo, unsigned char data);
static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c);
static void encReadBuff (unsigned short length, unsigned char *pBuff);
static void encWriteBuff (unsigned short length, unsigned char *pBuff);
static void encBitSet (unsigned char regNo, unsigned char data);
static void encBitClr (unsigned char regNo, unsigned char data);
static void encReset (void);
static void encInit (unsigned char *pEthAddr);
static unsigned short phyRead (unsigned char addr);
static void encPoll (void);
static void encRx (void);
#define m_nic_read(reg) encReadReg(reg)
#define m_nic_write(reg, data) encWriteReg(reg, data)
#define m_nic_write_retry(reg, data, count) encWriteRegRetry(reg, data, count)
#define m_nic_read_data(len, buf) encReadBuff((len), (buf))
#define m_nic_write_data(len, buf) encWriteBuff((len), (buf))
/* bit field set */
#define m_nic_bfs(reg, data) encBitSet(reg, data)
/* bit field clear */
#define m_nic_bfc(reg, data) encBitClr(reg, data)
static unsigned char bank = 0; /* current bank in enc28j60 */
static unsigned char next_pointer_lsb;
static unsigned char next_pointer_msb;
static unsigned char buffer[ENC_MAX_FRM_LEN];
static int rxResetCounter = 0;
#define RX_RESET_COUNTER 1000;
/*-----------------------------------------------------------------------------
* Returns 0 when failes otherwize 1
*/
int eth_init (bd_t * bis)
{
/* configure GPIO */
(*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS;
(*((volatile unsigned long *) IO1DIR)) |= ENC_RESET;
/* CS and RESET active low */
PUT32 (IO1SET, ENC_SPI_SLAVE_CS);
PUT32 (IO1SET, ENC_RESET);
spi_init ();
/* initialize controller */
encReset ();
encInit (bis->bi_enetaddr);
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */
return 0;
}
int eth_send (volatile void *packet, int length)
{
/* check frame length, etc. */
/* TODO: */
/* switch to bank 0 */
m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
/* set EWRPT */
m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff));
m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8));
/* set ETXST */
m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF);
m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8);
/* write packet */
m_nic_write_data (length, (unsigned char *) packet);
/* set ETXND */
m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF);
m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8);
/* set ECON1.TXRTS */
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS);
return 0;
}
/*****************************************************************************
* This function resets the receiver only. This function may be called from
* interrupt-context.
*/
static void encReceiverReset (void)
{
unsigned char econ1;
econ1 = m_nic_read (CTL_REG_ECON1);
if ((econ1 & ENC_ECON1_RXRST) == 0) {
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXRST);
rxResetCounter = RX_RESET_COUNTER;
}
}
/*****************************************************************************
* receiver reset timer
*/
static void encReceiverResetCallback (void)
{
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXRST);
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */
}
/*-----------------------------------------------------------------------------
* Check for received packets. Call NetReceive for each packet. The return
* value is ignored by the caller.
*/
int eth_rx (void)
{
if (rxResetCounter > 0 && --rxResetCounter == 0) {
encReceiverResetCallback ();
}
encPoll ();
return 0;
}
void eth_halt (void)
{
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXEN); /* disable receive */
}
/*****************************************************************************/
static void encPoll (void)
{
unsigned char eir_reg;
volatile unsigned char estat_reg;
unsigned char pkt_cnt;
/* clear global interrupt enable bit in enc28j60 */
m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE);
estat_reg = m_nic_read (CTL_REG_ESTAT);
eir_reg = m_nic_read (CTL_REG_EIR);
if (eir_reg & ENC_EIR_TXIF) {
/* clear TXIF bit in EIR */
m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXIF);
}
/* We have to use pktcnt and not pktif bit, see errata pt. 6 */
/* move to bank 1 */
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
/* read pktcnt */
pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
if (pkt_cnt > 0) {
if ((eir_reg & ENC_EIR_PKTIF) == 0) {
/*printf("encPoll: pkt cnt > 0, but pktif not set\n"); */
}
encRx ();
/* clear PKTIF bit in EIR, this should not need to be done but it
seems like we get problems if we do not */
m_nic_bfc (CTL_REG_EIR, ENC_EIR_PKTIF);
}
if (eir_reg & ENC_EIR_RXERIF) {
printf ("encPoll: rx error\n");
m_nic_bfc (CTL_REG_EIR, ENC_EIR_RXERIF);
}
if (eir_reg & ENC_EIR_TXERIF) {
printf ("encPoll: tx error\n");
m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF);
}
/* set global interrupt enable bit in enc28j60 */
m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
}
static void encRx (void)
{
unsigned short pkt_len;
unsigned short copy_len;
unsigned short status;
unsigned char eir_reg;
unsigned char pkt_cnt = 0;
/* switch to bank 0 */
m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
do {
m_nic_read_data (6, buffer);
next_pointer_lsb = buffer[0];
next_pointer_msb = buffer[1];
pkt_len = buffer[2];
pkt_len |= (unsigned short) buffer[3] << 8;
status = buffer[4];
status |= (unsigned short) buffer[5] << 8;
if (pkt_len <= ENC_MAX_FRM_LEN) {
copy_len = pkt_len;
} else {
copy_len = 0;
/* p_priv->stats.rx_dropped++; */
/* we will drop this packet */
}
if ((status & (1L << 7)) == 0) { /* check Received Ok bit */
copy_len = 0;
/* p_priv->stats.rx_errors++; */
}
if (copy_len > 0) {
m_nic_read_data (copy_len, buffer);
}
/* advance read pointer to next pointer */
m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb);
m_nic_write (CTL_REG_ERDPTH, next_pointer_msb);
/* decrease packet counter */
m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC);
/* move to bank 1 */
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
/* read pktcnt */
pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
/* switch to bank 0 */
m_nic_bfc (CTL_REG_ECON1,
(ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
if (copy_len == 0) {
eir_reg = m_nic_read (CTL_REG_EIR);
encReceiverReset ();
printf ("eth_rx: copy_len=0\n");
continue;
}
NetReceive ((unsigned char *) buffer, pkt_len);
eir_reg = m_nic_read (CTL_REG_EIR);
} while (pkt_cnt); /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
m_nic_write (CTL_REG_ERXRDPTL, next_pointer_lsb);
m_nic_write (CTL_REG_ERXRDPTH, next_pointer_msb);
}
static void encWriteReg (unsigned char regNo, unsigned char data)
{
spi_lock ();
enc_cfg_spi ();
enc_enable ();
spi_write (0x40 | regNo); /* write in regNo */
spi_write (data);
enc_disable ();
enc_enable ();
spi_write (0x1f); /* write reg 0x1f */
enc_disable ();
spi_unlock ();
}
static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c)
{
unsigned char readback;
int i;
spi_lock ();
for (i = 0; i < c; i++) {
enc_cfg_spi ();
enc_enable ();
spi_write (0x40 | regNo); /* write in regNo */
spi_write (data);
enc_disable ();
enc_enable ();
spi_write (0x1f); /* write reg 0x1f */
enc_disable ();
spi_unlock (); /* we must unlock spi first */
readback = encReadReg (regNo);
spi_lock ();
if (readback == data)
break;
}
spi_unlock ();
if (i == c) {
printf ("enc28j60: write reg %d failed\n", regNo);
}
}
static unsigned char encReadReg (unsigned char regNo)
{
unsigned char rxByte;
spi_lock ();
enc_cfg_spi ();
enc_enable ();
spi_write (0x1f); /* read reg 0x1f */
bank = spi_read () & 0x3;
enc_disable ();
enc_enable ();
spi_write (regNo);
rxByte = spi_read ();
/* check if MAC or MII register */
if (((bank == 2) && (regNo <= 0x1a)) ||
((bank == 3) && (regNo <= 0x05 || regNo == 0x0a))) {
/* ignore first byte and read another byte */
rxByte = spi_read ();
}
enc_disable ();
spi_unlock ();
return rxByte;
}
static void encReadBuff (unsigned short length, unsigned char *pBuff)
{
spi_lock ();
enc_cfg_spi ();
enc_enable ();
spi_write (0x20 | 0x1a); /* read buffer memory */
while (length--) {
if (pBuff != NULL)
*pBuff++ = spi_read ();
else
spi_write (0);
}
enc_disable ();
spi_unlock ();
}
static void encWriteBuff (unsigned short length, unsigned char *pBuff)
{
spi_lock ();
enc_cfg_spi ();
enc_enable ();
spi_write (0x60 | 0x1a); /* write buffer memory */
spi_write (0x00); /* control byte */
while (length--)
spi_write (*pBuff++);
enc_disable ();
spi_unlock ();
}
static void encBitSet (unsigned char regNo, unsigned char data)
{
spi_lock ();
enc_cfg_spi ();
enc_enable ();
spi_write (0x80 | regNo); /* bit field set */
spi_write (data);
enc_disable ();
spi_unlock ();
}
static void encBitClr (unsigned char regNo, unsigned char data)
{
spi_lock ();
enc_cfg_spi ();
enc_enable ();
spi_write (0xA0 | regNo); /* bit field clear */
spi_write (data);
enc_disable ();
spi_unlock ();
}
static void encReset (void)
{
spi_lock ();
enc_cfg_spi ();
enc_enable ();
spi_write (0xff); /* soft reset */
enc_disable ();
spi_unlock ();
/* sleep 1 ms. See errata pt. 2 */
udelay (1000);
#if 0
(*((volatile unsigned long *) IO1CLR)) &= ENC_RESET;
mdelay (5);
(*((volatile unsigned long *) IO1SET)) &= ENC_RESET;
#endif
}
static void encInit (unsigned char *pEthAddr)
{
unsigned short phid1 = 0;
unsigned short phid2 = 0;
/* switch to bank 0 */
m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
/*
* Setup the buffer space. The reset values are valid for the
* other pointers.
*/
#if 0
/* We shall not write to ERXST, see errata pt. 5. Instead we
have to make sure that ENC_RX_BUS_START is 0. */
m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1);
m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1);
#endif
m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1);
m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1);
next_pointer_lsb = (ENC_RX_BUF_START & 0xFF);
next_pointer_msb = (ENC_RX_BUF_START >> 8);
/*
* For tracking purposes, the ERXRDPT registers should be programmed with
* the same value. This is the read pointer.
*/
m_nic_write (CTL_REG_ERXRDPTL, (ENC_RX_BUF_START & 0xFF));
m_nic_write_retry (CTL_REG_ERXRDPTH, (ENC_RX_BUF_START >> 8), 1);
/* Setup receive filters. */
/* move to bank 1 */
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
/* OR-filtering, Unicast, CRC-check and broadcast */
m_nic_write_retry (CTL_REG_ERXFCON,
(ENC_RFR_UCEN | ENC_RFR_CRCEN | ENC_RFR_BCEN), 1);
/* Wait for Oscillator Start-up Timer (OST). */
while ((m_nic_read (CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY) == 0) {
static int cnt = 0;
if (cnt++ >= 1000) {
cnt = 0;
}
}
/* verify identification */
phid1 = phyRead (PHY_REG_PHID1);
phid2 = phyRead (PHY_REG_PHID2);
if (phid1 != ENC_PHID1_VALUE
|| (phid2 & ENC_PHID2_MASK) != ENC_PHID2_VALUE) {
printf ("ERROR: failed to identify controller\n");
printf ("phid1 = %x, phid2 = %x\n",
phid1, (phid2 & ENC_PHID2_MASK));
printf ("should be phid1 = %x, phid2 = %x\n",
ENC_PHID1_VALUE, ENC_PHID2_VALUE);
}
/*
* --- MAC Initialization ---
*/
/* Pull MAC out of Reset */
/* switch to bank 2 */
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
/* clear MAC reset bits */
m_nic_write_retry (CTL_REG_MACON2, 0, 1);
/* enable MAC to receive frames */
m_nic_write_retry (CTL_REG_MACON1, ENC_MACON1_MARXEN, 10);
/* configure pad, tx-crc and duplex */
/* TODO maybe enable FRMLNEN */
m_nic_write_retry (CTL_REG_MACON3,
(ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN), 10);
/* set maximum frame length */
m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10);
m_nic_write_retry (CTL_REG_MAMXFLH, (ENC_MAX_FRM_LEN >> 8), 10);
/*
* Set MAC back-to-back inter-packet gap. Recommended 0x12 for half duplex
* and 0x15 for full duplex.
*/
m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10);
/* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */
m_nic_write_retry (CTL_REG_MAIPGL, 0x12, 10);
/*
* Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended
* 0x0c for half-duplex. Nothing for full-duplex
*/
m_nic_write_retry (CTL_REG_MAIPGH, 0x0C, 10);
/* set MAC address */
/* switch to bank 3 */
m_nic_bfs (CTL_REG_ECON1, (ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1));
m_nic_write_retry (CTL_REG_MAADR0, pEthAddr[5], 1);
m_nic_write_retry (CTL_REG_MAADR1, pEthAddr[4], 1);
m_nic_write_retry (CTL_REG_MAADR2, pEthAddr[3], 1);
m_nic_write_retry (CTL_REG_MAADR3, pEthAddr[2], 1);
m_nic_write_retry (CTL_REG_MAADR4, pEthAddr[1], 1);
m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1);
/*
* Receive settings
*/
/* auto-increment RX-pointer when reading a received packet */
m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_AUTOINC);
/* enable interrupts */
m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE);
m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE);
m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE);
m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE);
m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
}
/*****************************************************************************
*
* Description:
* Read PHY registers.
*
* NOTE! This function will change to Bank 2.
*
* Params:
* [in] addr address of the register to read
*
* Returns:
* The value in the register
*/
static unsigned short phyRead (unsigned char addr)
{
unsigned short ret = 0;
/* move to bank 2 */
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
/* write address to MIREGADR */
m_nic_write (CTL_REG_MIREGADR, addr);
/* set MICMD.MIIRD */
m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD);
/* poll MISTAT.BUSY bit until operation is complete */
while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
static int cnt = 0;
if (cnt++ >= 1000) {
/* GJ - this seems extremely dangerous! */
/* printf("#"); */
cnt = 0;
}
}
/* clear MICMD.MIIRD */
m_nic_write (CTL_REG_MICMD, 0);
ret = (m_nic_read (CTL_REG_MIRDH) << 8);
ret |= (m_nic_read (CTL_REG_MIRDL) & 0xFF);
return ret;
}

476
board/lpc2292sodimm/flash.c Normal file
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/*
* (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/hardware.h>
/* IAP commands use 32 bytes at the top of CPU internal sram, we
use 512 bytes below that */
#define COPY_BUFFER_LOCATION 0x40003de0
#define IAP_LOCATION 0x7ffffff1
#define IAP_CMD_PREPARE 50
#define IAP_CMD_COPY 51
#define IAP_CMD_ERASE 52
#define IAP_CMD_CHECK 53
#define IAP_CMD_ID 54
#define IAP_CMD_VERSION 55
#define IAP_CMD_COMPARE 56
#define IAP_RET_CMD_SUCCESS 0
#define SST_BASEADDR 0x80000000
#define SST_ADDR1 ((volatile ushort*)(SST_BASEADDR + (0x5555 << 1)))
#define SST_ADDR2 ((volatile ushort*)(SST_BASEADDR + (0x2AAA << 1)))
static unsigned long command[5];
static unsigned long result[2];
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
extern void iap_entry(unsigned long * command, unsigned long * result);
/*-----------------------------------------------------------------------
*
*/
int get_flash_sector(flash_info_t * info, ulong flash_addr)
{
int i;
for(i=1; i < (info->sector_count); i++) {
if (flash_addr < (info->start[i]))
break;
}
return (i-1);
}
/*-----------------------------------------------------------------------
* This function assumes that flash_addr is aligned on 512 bytes boundary
* in flash. This function also assumes that prepare have been called
* for the sector in question.
*/
int copy_buffer_to_flash(flash_info_t * info, ulong flash_addr)
{
int first_sector;
int last_sector;
first_sector = get_flash_sector(info, flash_addr);
last_sector = get_flash_sector(info, flash_addr + 512 - 1);
/* prepare sectors for write */
command[0] = IAP_CMD_PREPARE;
command[1] = first_sector;
command[2] = last_sector;
iap_entry(command, result);
if (result[0] != IAP_RET_CMD_SUCCESS) {
printf("IAP prepare failed\n");
return ERR_PROG_ERROR;
}
command[0] = IAP_CMD_COPY;
command[1] = flash_addr;
command[2] = COPY_BUFFER_LOCATION;
command[3] = 512;
command[4] = CFG_SYS_CLK_FREQ >> 10;
iap_entry(command, result);
if (result[0] != IAP_RET_CMD_SUCCESS) {
printf("IAP copy failed\n");
return 1;
}
return 0;
}
/*-----------------------------------------------------------------------
*
*/
void write_word_sst(ulong addr, ushort data)
{
ushort tmp;
*SST_ADDR1 = 0x00AA;
*SST_ADDR2 = 0x0055;
*SST_ADDR1 = 0x00A0;
*((volatile ushort*)addr) = data;
/* do data polling */
do {
tmp = *((volatile ushort*)addr);
} while (tmp != data);
}
/*-----------------------------------------------------------------------
*/
ulong flash_init (void)
{
int j, k;
ulong size = 0;
ulong flashbase = 0;
flash_info[0].flash_id = (PHILIPS_LPC2292 & FLASH_VENDMASK);
flash_info[0].size = 0x003E000; /* 256 - 8 KB */
flash_info[0].sector_count = 17;
memset (flash_info[0].protect, 0, 17);
flashbase = 0x00000000;
for (j = 0, k = 0; j < 8; j++, k++) {
flash_info[0].start[k] = flashbase;
flashbase += 0x00002000;
}
for (j = 0; j < 2; j++, k++) {
flash_info[0].start[k] = flashbase;
flashbase += 0x00010000;
}
for (j = 0; j < 7; j++, k++) {
flash_info[0].start[k] = flashbase;
flashbase += 0x00002000;
}
size += flash_info[0].size;
flash_info[1].flash_id = (SST_MANUFACT & FLASH_VENDMASK);
flash_info[1].size = 0x00200000; /* 2 MB */
flash_info[1].sector_count = 512;
memset (flash_info[1].protect, 0, 512);
flashbase = SST_BASEADDR;
for (j=0; j<512; j++) {
flash_info[1].start[j] = flashbase;
flashbase += 0x1000; /* 4 KB sectors */
}
size += flash_info[1].size;
/* Protect monitor and environment sectors */
flash_protect (FLAG_PROTECT_SET,
0x0,
0x0 + monitor_flash_len - 1,
&flash_info[0]);
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
&flash_info[0]);
return size;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
int i;
int erased = 0;
unsigned long j;
unsigned long count;
unsigned char *p;
switch (info->flash_id & FLASH_VENDMASK) {
case (SST_MANUFACT & FLASH_VENDMASK):
printf("SST: ");
break;
case (PHILIPS_LPC2292 & FLASH_VENDMASK):
printf("Philips: ");
break;
default:
printf ("Unknown Vendor ");
break;
}
printf (" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
if ((i % 5) == 0) {
printf ("\n ");
}
if (i < (info->sector_count - 1)) {
count = info->start[i+1] - info->start[i];
}
else {
count = info->start[0] + info->size - info->start[i];
}
p = (unsigned char*)(info->start[i]);
erased = 1;
for (j = 0; j < count; j++) {
if (*p != 0xFF) {
erased = 0;
break;
}
p++;
}
printf (" %08lX%s%s", info->start[i], info->protect[i] ? " RO" : " ",
erased ? " E" : " ");
}
printf ("\n");
}
/*-----------------------------------------------------------------------
*/
int flash_erase_philips (flash_info_t * info, int s_first, int s_last)
{
int flag;
int prot;
int sect;
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot)
return ERR_PROTECTED;
flag = disable_interrupts();
printf ("Erasing %d sectors starting at sector %2d.\n"
"This make take some time ... ",
s_last - s_first + 1, s_first);
command[0] = IAP_CMD_PREPARE;
command[1] = s_first;
command[2] = s_last;
iap_entry(command, result);
if (result[0] != IAP_RET_CMD_SUCCESS) {
printf("IAP prepare failed\n");
return ERR_PROTECTED;
}
command[0] = IAP_CMD_ERASE;
command[1] = s_first;
command[2] = s_last;
command[3] = CFG_SYS_CLK_FREQ >> 10;
iap_entry(command, result);
if (result[0] != IAP_RET_CMD_SUCCESS) {
printf("IAP erase failed\n");
return ERR_PROTECTED;
}
if (flag)
enable_interrupts();
return ERR_OK;
}
int flash_erase_sst (flash_info_t * info, int s_first, int s_last)
{
int i;
for (i = s_first; i <= s_last; i++) {
*SST_ADDR1 = 0x00AA;
*SST_ADDR2 = 0x0055;
*SST_ADDR1 = 0x0080;
*SST_ADDR1 = 0x00AA;
*SST_ADDR2 = 0x0055;
*((volatile ushort*)(info->start[i])) = 0x0030;
/* wait for erase to finish */
udelay(25000);
}
return ERR_OK;
}
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
switch (info->flash_id & FLASH_VENDMASK) {
case (SST_MANUFACT & FLASH_VENDMASK):
return flash_erase_sst(info, s_first, s_last);
case (PHILIPS_LPC2292 & FLASH_VENDMASK):
return flash_erase_philips(info, s_first, s_last);
default:
return ERR_PROTECTED;
}
return ERR_PROTECTED;
}
/*-----------------------------------------------------------------------
* Copy memory to flash.
*
* cnt is in bytes
*/
int write_buff_sst (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ushort tmp;
ulong i;
uchar* src_org;
uchar* dst_org;
ulong cnt_org = cnt;
int ret = ERR_OK;
src_org = src;
dst_org = (uchar*)addr;
if (addr & 1) { /* if odd address */
tmp = *((uchar*)(addr - 1)); /* little endian */
tmp |= (*src << 8);
write_word_sst(addr - 1, tmp);
addr += 1;
cnt -= 1;
src++;
}
while (cnt > 1) {
tmp = ((*(src+1)) << 8) + (*src); /* little endian */
write_word_sst(addr, tmp);
addr += 2;
src += 2;
cnt -= 2;
}
if (cnt > 0) {
tmp = (*((uchar*)(addr + 1))) << 8;
tmp |= *src;
write_word_sst(addr, tmp);
}
for (i = 0; i < cnt_org; i++) {
if (*dst_org != *src_org) {
printf("Write failed. Byte %lX differs\n", i);
ret = ERR_PROG_ERROR;
break;
}
dst_org++;
src_org++;
}
return ret;
}
int write_buff_philips (flash_info_t * info,
uchar * src,
ulong addr,
ulong cnt)
{
int first_copy_size;
int last_copy_size;
int first_block;
int last_block;
int nbr_mid_blocks;
uchar memmap_value;
ulong i;
uchar* src_org;
uchar* dst_org;
int ret = ERR_OK;
src_org = src;
dst_org = (uchar*)addr;
first_block = addr / 512;
last_block = (addr + cnt) / 512;
nbr_mid_blocks = last_block - first_block - 1;
first_copy_size = 512 - (addr % 512);
last_copy_size = (addr + cnt) % 512;
#if 0
printf("\ncopy first block: (1) %lX -> %lX 0x200 bytes, "
"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n",
(ulong)(first_block * 512),
(ulong)COPY_BUFFER_LOCATION,
(ulong)src,
(ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
first_copy_size,
(ulong)COPY_BUFFER_LOCATION,
(ulong)(first_block * 512));
#endif
/* copy first block */
memcpy((void*)COPY_BUFFER_LOCATION,
(void*)(first_block * 512), 512);
memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
src, first_copy_size);
copy_buffer_to_flash(info, first_block * 512);
src += first_copy_size;
addr += first_copy_size;
/* copy middle blocks */
for (i = 0; i < nbr_mid_blocks; i++) {
#if 0
printf("copy middle block: %lX -> %lX 512 bytes, "
"%lX -> %lX 512 bytes\n",
(ulong)src,
(ulong)COPY_BUFFER_LOCATION,
(ulong)COPY_BUFFER_LOCATION,
(ulong)addr);
#endif
memcpy((void*)COPY_BUFFER_LOCATION, src, 512);
copy_buffer_to_flash(info, addr);
src += 512;
addr += 512;
}
if (last_copy_size > 0) {
#if 0
printf("copy last block: (1) %lX -> %lX 0x200 bytes, "
"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n",
(ulong)(last_block * 512),
(ulong)COPY_BUFFER_LOCATION,
(ulong)src,
(ulong)(COPY_BUFFER_LOCATION),
last_copy_size,
(ulong)COPY_BUFFER_LOCATION,
(ulong)addr);
#endif
/* copy last block */
memcpy((void*)COPY_BUFFER_LOCATION,
(void*)(last_block * 512), 512);
memcpy((void*)COPY_BUFFER_LOCATION,
src, last_copy_size);
copy_buffer_to_flash(info, addr);
}
/* verify write */
memmap_value = GET8(MEMMAP);
disable_interrupts();
PUT8(MEMMAP, 01); /* we must make sure that initial 64
bytes are taken from flash when we
do the compare */
for (i = 0; i < cnt; i++) {
if (*dst_org != *src_org){
printf("Write failed. Byte %lX differs\n", i);
ret = ERR_PROG_ERROR;
break;
}
dst_org++;
src_org++;
}
PUT8(MEMMAP, memmap_value);
enable_interrupts();
return ret;
}
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
switch (info->flash_id & FLASH_VENDMASK) {
case (SST_MANUFACT & FLASH_VENDMASK):
return write_buff_sst(info, src, addr, cnt);
case (PHILIPS_LPC2292 & FLASH_VENDMASK):
return write_buff_philips(info, src, addr, cnt);
default:
return ERR_PROG_ERROR;
}
return ERR_PROG_ERROR;
}

7
board/lpc2292sodimm/iap_entry.S Normal file
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IAP_ADDRESS: .word 0x7FFFFFF1
.globl iap_entry
iap_entry:
ldr r2, IAP_ADDRESS
bx r2
mov pc, lr

87
board/lpc2292sodimm/lowlevel_init.S Normal file
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/*
* (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/arch/hardware.h>
/* some parameters for the board */
/* setting up the memory */
#define SRAM_START 0x40000000
#define SRAM_SIZE 0x00004000
#define BCFG0_VALUE 0x1000ffef
#define BCFG1_VALUE 0x10001C61
_TEXT_BASE:
.word TEXT_BASE
MEMMAP_ADR:
.word MEMMAP
BCFG0_ADR:
.word BCFG0
_BCFG0_VALUE:
.word BCFG0_VALUE
BCFG1_ADR:
.word BCFG1
_BCFG1_VALUE:
.word BCFG1_VALUE
PINSEL2_ADR:
.word PINSEL2
PINSEL2_MASK:
.word 0x00000000
PINSEL2_VALUE:
.word 0x0F800914
.extern _start
.globl lowlevel_init
lowlevel_init:
/* set up memory control register for bank 0 */
ldr r0, _BCFG0_VALUE
ldr r1, BCFG0_ADR
str r0, [r1]
/* set up memory control register for bank 1 */
ldr r0, _BCFG1_VALUE
ldr r1, BCFG1_ADR
str r0, [r1]
/* set up PINSEL2 for bus-pins */
ldr r0, PINSEL2_ADR
ldr r1, [r0]
ldr r2, PINSEL2_MASK
ldr r3, PINSEL2_VALUE
and r1, r1, r2
orr r1, r1, r3
str r1, [r0]
/* move vectors to beginning of SRAM */
mov r2, #SRAM_START
mov r0, #0 /*_start*/
ldmneia r0!, {r3-r10}
stmneia r2!, {r3-r10}
ldmneia r0, {r3-r9}
stmneia r2, {r3-r9}
/* Set-up MEMMAP register, so vectors are taken from SRAM */
ldr r0, MEMMAP_ADR
mov r1, #0x02 /* vectors re-mapped to static RAM */
str r1, [r0]
/* everything is fine now */
mov pc, lr

62
board/lpc2292sodimm/lpc2292sodimm.c Normal file
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/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
* Armadillo board HT1070
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <clps7111.h>
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
/* Activate LED flasher */
IO_LEDFLSH = 0x40;
/* arch number MACH_TYPE_ARMADILLO - not official*/
gd->bd->bi_arch_number = 83;
/* location of boot parameters */
gd->bd->bi_boot_params = 0xc0000100;
return 0;
}
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
return (0);
}

154
board/lpc2292sodimm/mmc.c Normal file
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@ -0,0 +1,154 @@
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <mmc.h>
#include <asm/errno.h>
#include <asm/arch/hardware.h>
#include <part.h>
#include <fat.h>
#include "mmc_hw.h"
#include "spi.h"
#ifdef CONFIG_MMC
#undef MMC_DEBUG
static block_dev_desc_t mmc_dev;
/* these are filled out by a call to mmc_hw_get_parameters */
static int hw_size; /* in kbytes */
static int hw_nr_sects;
static int hw_sect_size; /* in bytes */
block_dev_desc_t * mmc_get_dev(int dev)
{
return (block_dev_desc_t *)(&mmc_dev);
}
unsigned long mmc_block_read(int dev,
unsigned long start,
lbaint_t blkcnt,
unsigned long *buffer)
{
unsigned long rc = 0;
unsigned char *p = (unsigned char *)buffer;
unsigned long i;
unsigned long addr = start;
#ifdef MMC_DEBUG
printf("mmc_block_read: start=%lu, blkcnt=%lu\n", start,
(unsigned long)blkcnt);
#endif
for(i = 0; i < (unsigned long)blkcnt; i++) {
#ifdef MMC_DEBUG
printf("mmc_read_sector: addr=%lu, buffer=%p\n", addr, p);
#endif
(void)mmc_read_sector(addr, p);
rc++;
addr++;
p += hw_sect_size;
}
return rc;
}
/*-----------------------------------------------------------------------------
* Read hardware paramterers (sector size, size, number of sectors)
*/
static int mmc_hw_get_parameters(void)
{
unsigned char csddata[16];
unsigned int sizemult;
unsigned int size;
mmc_read_csd(csddata);
hw_sect_size = 1<<(csddata[5] & 0x0f);
size = ((csddata[6]&0x03)<<10)+(csddata[7]<<2)+(csddata[8]&0xc0);
sizemult = ((csddata[10] & 0x80)>>7)+((csddata[9] & 0x03)<<1);
hw_nr_sects = (size+1)*(1<<(sizemult+2));
hw_size = hw_nr_sects*hw_sect_size/1024;
#ifdef MMC_DEBUG
printf("mmc_hw_get_parameters: hw_sect_size=%d, hw_nr_sects=%d, "
"hw_size=%d\n", hw_sect_size, hw_nr_sects, hw_size);
#endif
return 0;
}
int mmc_init(int verbose)
{
int ret = -ENODEV;
if (verbose)
printf("mmc_init\n");
spi_init();
mmc_hw_init();
mmc_hw_get_parameters();
mmc_dev.if_type = IF_TYPE_MMC;
mmc_dev.part_type = PART_TYPE_DOS;
mmc_dev.dev = 0;
mmc_dev.lun = 0;
mmc_dev.type = 0;
mmc_dev.blksz = hw_sect_size;
mmc_dev.lba = hw_nr_sects;
sprintf((char*)mmc_dev.vendor, "Unknown vendor");
sprintf((char*)mmc_dev.product, "Unknown product");
sprintf((char*)mmc_dev.revision, "N/A");
mmc_dev.removable = 0; /* should be true??? */
mmc_dev.block_read = mmc_block_read;
fat_register_device(&mmc_dev, 1);
ret = 0;
return ret;
}
int mmc_write(uchar * src, ulong dst, int size)
{
#ifdef MMC_DEBUG
printf("mmc_write: src=%p, dst=%lu, size=%u\n", src, dst, size);
#endif
/* Since mmc2info always returns 0 this function will never be called */
return 0;
}
int mmc_read(ulong src, uchar * dst, int size)
{
#ifdef MMC_DEBUG
printf("mmc_read: src=%lu, dst=%p, size=%u\n", src, dst, size);
#endif
/* Since mmc2info always returns 0 this function will never be called */
return 0;
}
int mmc2info(ulong addr)
{
/* This function is used by cmd_cp to determine if source or destination
address resides on MMC-card or not. We do not support copy to and from
MMC-card so we always return 0. */
return 0;
}
#endif /* CONFIG_MMC */

233
board/lpc2292sodimm/mmc_hw.c Normal file
View file

@ -0,0 +1,233 @@
/*
This code was original written by Ulrich Radig and modified by
Embedded Artists AB (www.embeddedartists.com).
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/arch/hardware.h>
#include "spi.h"
#define MMC_Enable() PUT32(IO1CLR, 1l << 22)
#define MMC_Disable() PUT32(IO1SET, 1l << 22)
#define mmc_spi_cfg() spi_set_clock(8); spi_set_cfg(0, 1, 0);
static unsigned char Write_Command_MMC (unsigned char *CMD);
static void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer,
unsigned short int Bytes);
/* initialize the hardware */
int mmc_hw_init(void)
{
unsigned long a;
unsigned short int Timeout = 0;
unsigned char b;
unsigned char CMD[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95};
/* set-up GPIO and SPI */
(*((volatile unsigned long *)PINSEL2)) &= ~(1l << 3); /* clear bit 3 */
(*((volatile unsigned long *)IO1DIR)) |= (1l << 22); /* set bit 22 (output) */
MMC_Disable();
spi_lock();
spi_set_clock(248);
spi_set_cfg(0, 1, 0);
MMC_Enable();
/* waste some time */
for(a=0; a < 20000; a++)
asm("nop");
/* Put the MMC/SD-card into SPI-mode */
for (b = 0; b < 10; b++) /* Sends min 74+ clocks to the MMC/SD-card */
spi_write(0xff);
/* Sends command CMD0 to MMC/SD-card */
while (Write_Command_MMC(CMD) != 1) {
if (Timeout++ > 200) {
MMC_Disable();
spi_unlock();
return(1); /* Abort with command 1 (return 1) */
}
}
/* Sends Command CMD1 an MMC/SD-card */
Timeout = 0;
CMD[0] = 0x41;/* Command 1 */
CMD[5] = 0xFF;
while (Write_Command_MMC(CMD) != 0) {
if (Timeout++ > 200) {
MMC_Disable();
spi_unlock();
return (2); /* Abort with command 2 (return 2) */
}
}
MMC_Disable();
spi_unlock();
return 0;
}
/* ############################################################################
Sends a command to the MMC/SD-card
######################################################################### */
static unsigned char Write_Command_MMC (unsigned char *CMD)
{
unsigned char a, tmp = 0xff;
unsigned short int Timeout = 0;
MMC_Disable();
spi_write(0xFF);
MMC_Enable();
for (a = 0; a < 0x06; a++)
spi_write(*CMD++);
while (tmp == 0xff) {
tmp = spi_read();
if (Timeout++ > 5000)
break;
}
return (tmp);
}
/* ############################################################################
Routine to read the CID register from the MMC/SD-card (16 bytes)
######################################################################### */
void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, unsigned short
int Bytes)
{
unsigned short int a;
spi_lock();
mmc_spi_cfg();
MMC_Enable();
if (Write_Command_MMC(CMD) != 0) {
MMC_Disable();
spi_unlock();
return;
}
while (spi_read() != 0xfe) {};
for (a = 0; a < Bytes; a++)
*Buffer++ = spi_read();
/* Read the CRC-byte */
spi_read(); /* CRC - byte is discarded */
spi_read(); /* CRC - byte is discarded */
/* set MMC_Chip_Select to high (MMC/SD-card Inaktiv) */
MMC_Disable();
spi_unlock();
return;
}
/* ############################################################################
Routine to read a block (512 bytes) from the MMC/SD-card
######################################################################### */
unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer)
{
/* Command 16 to read aBlocks from the MMC/SD - caed */
unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
/* The addres on the MMC/SD-card is in bytes,
addr is transformed from blocks to bytes and the result is
placed into the command */
addr = addr << 9; /* addr = addr * 512 */
CMD[1] = ((addr & 0xFF000000) >> 24);
CMD[2] = ((addr & 0x00FF0000) >> 16);
CMD[3] = ((addr & 0x0000FF00) >> 8 );
MMC_Read_Block(CMD, Buffer, 512);
return (0);
}
/* ############################################################################
Routine to write a block (512 byte) to the MMC/SD-card
######################################################################### */
unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer)
{
unsigned char tmp, a;
unsigned short int b;
/* Command 24 to write a block to the MMC/SD - card */
unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
/* The addres on the MMC/SD-card is in bytes,
addr is transformed from blocks to bytes and the result is
placed into the command */
addr = addr << 9; /* addr = addr * 512 */
CMD[1] = ((addr & 0xFF000000) >> 24);
CMD[2] = ((addr & 0x00FF0000) >> 16);
CMD[3] = ((addr & 0x0000FF00) >> 8 );
spi_lock();
mmc_spi_cfg();
MMC_Enable();
/* Send command CMD24 to the MMC/SD-card (Write 1 Block/512 Bytes) */
tmp = Write_Command_MMC(CMD);
if (tmp != 0) {
MMC_Disable();
spi_unlock();
return(tmp);
}
/* Do a short delay and send a clock-pulse to the MMC/SD-card */
for (a = 0; a < 100; a++)
spi_read();
/* Send a start byte to the MMC/SD-card */
spi_write(0xFE);
/* Write the block (512 bytes) to the MMC/SD-card */
for (b = 0; b < 512; b++)
spi_write(*Buffer++);
/* write the CRC-Byte */
spi_write(0xFF); /* write a dummy CRC */
spi_write(0xFF); /* CRC code is not used */
/* Wait for MMC/SD-card busy */
while (spi_read() != 0xff) {};
/* set MMC_Chip_Select to high (MMC/SD-card inactive) */
MMC_Disable();
spi_unlock();
return (0);
}
/* #########################################################################
Routine to read the CSD register from the MMC/SD-card (16 bytes)
######################################################################### */
unsigned char mmc_read_csd (unsigned char *Buffer)
{
/* Command to read the CSD register */
unsigned char CMD[] = {0x49, 0x00, 0x00, 0x00, 0x00, 0xFF};
MMC_Read_Block(CMD, Buffer, 16);
return (0);
}

29
board/lpc2292sodimm/mmc_hw.h Normal file
View file

@ -0,0 +1,29 @@
/*
This module implements a linux character device driver for the 24c256 chip.
Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MMC_HW_
#define _MMC_HW_
unsigned char mmc_read_csd(unsigned char *Buffer);
unsigned char mmc_read_sector (unsigned long addr,
unsigned char *Buffer);
unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer);
int mmc_hw_init(void);
#endif /* _MMC_HW_ */

40
board/lpc2292sodimm/spi.c Normal file
View file

@ -0,0 +1,40 @@
/*
This module implements an interface to the SPI on the lpc22xx.
Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/errno.h>
#include <asm/arch/hardware.h>
#include "spi.h"
unsigned long spi_flags;
unsigned char spi_idle = 0x00;
int spi_init(void)
{
unsigned long pinsel0_value;
/* activate spi pins */
pinsel0_value = GET32(PINSEL0);
pinsel0_value &= ~(0xFFl << 8);
pinsel0_value |= (0x55l << 8);
PUT32(PINSEL0, pinsel0_value);
return 0;
}

82
board/lpc2292sodimm/spi.h Normal file
View file

@ -0,0 +1,82 @@
/*
This file defines the interface to the lpc22xx SPI module.
Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com)
This file may be included in software not adhering to the GPL.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef SPI_H
#define SPI_H
#include <config.h>
#include <common.h>
#include <asm/errno.h>
#include <asm/arch/hardware.h>
#define SPIF 0x80
#define spi_lock() disable_interrupts();
#define spi_unlock() enable_interrupts();
extern unsigned long spi_flags;
extern unsigned char spi_idle;
int spi_init(void);
static inline unsigned char spi_read(void)
{
unsigned char b;
PUT8(S0SPDR, spi_idle);
while (!(GET8(S0SPSR) & SPIF));
b = GET8(S0SPDR);
return b;
}
static inline void spi_write(unsigned char b)
{
PUT8(S0SPDR, b);
while (!(GET8(S0SPSR) & SPIF));
GET8(S0SPDR); /* this will clear the SPIF bit */
}
static inline void spi_set_clock(unsigned char clk_value)
{
PUT8(S0SPCCR, clk_value);
}
static inline void spi_set_cfg(unsigned char phase,
unsigned char polarity,
unsigned char lsbf)
{
unsigned char v = 0x20; /* master bit set */
if (phase)
v |= 0x08; /* set phase bit */
if (polarity) {
v |= 0x10; /* set polarity bit */
spi_idle = 0xFF;
} else {
spi_idle = 0x00;
}
if (lsbf)
v |= 0x40; /* set lsbf bit */
PUT8(S0SPCR, v);
}
#endif /* SPI_H */

55
board/lpc2292sodimm/u-boot.lds Normal file
View file

@ -0,0 +1,55 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
cpu/arm720t/start.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
_end = .;
}

3
cpu/arm720t/cpu.c
View file

@ -73,7 +73,7 @@ int cleanup_before_linux (void)
/* go to high speed */
IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73;
#endif
#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B)
#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292)
disable_interrupts ();
/* Nothing more needed */
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
@ -252,6 +252,7 @@ int dcache_status (void)
void icache_enable (void)
{
}
#elif defined(CONFIG_LPC2292) /* just to satisfy the compiler */
#else
#error No icache/dcache enable/disable functions defined for this CPU type
#endif

27
cpu/arm720t/interrupts.c
View file

@ -36,6 +36,12 @@
#define TIMER_LOAD_VAL 0xffff
/* macro to read the 16 bit timer */
#define READ_TIMER (IO_TC1D & 0xffff)
#ifdef CONFIG_LPC2292
#undef READ_TIMER
#define READ_TIMER (0xFFFFFFFF - GET32(T0TC))
#endif
#else
#define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
@ -195,6 +201,13 @@ void do_irq (struct pt_regs *pt_regs)
}
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* No do_irq() for IntegratorAP/CM720T as yet */
#elif defined(CONFIG_LPC2292)
void (*pfnct)(void);
pfnct = (void (*)(void))VICVectAddr;
(*pfnct)();
#else
#error do_irq() not defined for this CPU type
#endif
@ -293,6 +306,13 @@ int interrupt_init (void)
/* Start timer */
SET_REG( REG_TMOD, TM0_RUN);
#elif defined(CONFIG_LPC2292)
PUT32(T0IR, 0); /* disable all timer0 interrupts */
PUT32(T0TCR, 0); /* disable timer0 */
PUT32(T0PR, CFG_SYS_CLK_FREQ / CFG_HZ);
PUT32(T0MCR, 0);
PUT32(T0TC, 0);
PUT32(T0TCR, 1); /* enable timer0 */
#else
#error No interrupt_init() defined for this CPU type
@ -309,7 +329,7 @@ int interrupt_init (void)
*/
#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292)
void reset_timer (void)
{
@ -337,7 +357,12 @@ void udelay (unsigned long usec)
tmo += get_timer (0);
while (get_timer_masked () < tmo)
#ifdef CONFIG_LPC2292
/* GJ - not sure whether this is really needed or a misunderstanding */
__asm__ __volatile__(" nop");
#else
/*NOP*/;
#endif
}
void reset_timer_masked (void)

78
cpu/arm720t/serial.c
View file

@ -123,4 +123,80 @@ serial_puts (const char *s)
}
}
#endif /* defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) */
#elif defined(CONFIG_LPC2292)
#include <asm/arch/hardware.h>
void serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned short divisor = 0;
switch (gd->baudrate) {
case 1200: divisor = 3072; break;
case 9600: divisor = 384; break;
case 19200: divisor = 192; break;
case 38400: divisor = 96; break;
case 57600: divisor = 64; break;
case 115200: divisor = 32; break;
default: hang (); break;
}
/* init serial UART0 */
PUT8(U0LCR, 0);
PUT8(U0IER, 0);
PUT8(U0LCR, 0x80); /* DLAB=1 */
PUT8(U0DLL, (unsigned char)(divisor & 0x00FF));
PUT8(U0DLM, (unsigned char)(divisor >> 8));
PUT8(U0LCR, 0x03); /* 8N1, DLAB=0 */
PUT8(U0FCR, 1); /* Enable RX and TX FIFOs */
}
int serial_init (void)
{
unsigned long pinsel0;
serial_setbrg ();
pinsel0 = GET32(PINSEL0);
pinsel0 &= ~(0x00000003);
pinsel0 |= 5;
PUT32(PINSEL0, pinsel0);
return (0);
}
void serial_putc (const char c)
{
if (c == '\n')
{
while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */
PUT8(U0THR, '\r');
}
while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */
PUT8(U0THR, c);
}
int serial_getc (void)
{
while((GET8(U0LSR) & 1) == 0);
return GET8(U0RBR);
}
void
serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
/* Test if there is a byte to read */
int serial_tstc (void)
{
return (GET8(U0LSR) & 1);
}
#endif

69
cpu/arm720t/start.S
View file

@ -43,7 +43,11 @@ _start: b reset
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
ldr pc, _data_abort
#ifdef CONFIG_LPC2292
.word 0xB4405F76 /* 2's complement of the checksum of the vectors */
#else
ldr pc, _not_used
#endif
ldr pc, _irq
ldr pc, _fiq
@ -123,6 +127,10 @@ reset:
bl cpu_init_crit
#endif
#ifdef CONFIG_LPC2292
bl lowlevel_init
#endif
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
@ -131,6 +139,7 @@ relocate: /* relocate U-Boot to RAM */
beq stack_setup
#if TEXT_BASE
#ifndef CONFIG_LPC2292 /* already done in lowlevel_init */
ldr r2, =0x0 /* Relocate the exception vectors */
cmp r1, r2 /* and associated data to address */
ldmneia r0!, {r3-r10} /* 0x0. Do nothing if TEXT_BASE is */
@ -138,6 +147,7 @@ relocate: /* relocate U-Boot to RAM */
ldmneia r0, {r3-r9}
stmneia r2, {r3-r9}
adrne r0, _start /* restore r0 */
#endif /* !CONFIG_LPC2292 */
#endif
ldr r2, _armboot_start
@ -206,6 +216,14 @@ SYSCON3: .word 0x80002200
#define CLKCTL_49 0x4 /* 49.152 MHz */
#define CLKCTL_73 0x6 /* 73.728 MHz */
#elif defined(CONFIG_LPC2292)
PLLCFG_ADR: .word PLLCFG
PLLFEED_ADR: .word PLLFEED
PLLCON_ADR: .word PLLCON
PLLSTAT_ADR: .word PLLSTAT
VPBDIV_ADR: .word VPBDIV
MEMMAP_ADR: .word MEMMAP
#endif
cpu_init_crit:
@ -306,6 +324,50 @@ cpu_init_crit:
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* No specific initialisation for IntegratorAP/CM720T as yet */
#elif defined(CONFIG_LPC2292)
/* Set-up PLL */
mov r3, #0xAA
mov r4, #0x55
/* First disconnect and disable the PLL */
ldr r0, PLLCON_ADR
mov r1, #0x00
str r1, [r0]
ldr r0, PLLFEED_ADR /* start feed sequence */
str r3, [r0]
str r4, [r0] /* feed sequence done */
/* Set new M and P values */
ldr r0, PLLCFG_ADR
mov r1, #0x23 /* M=4 and P=2 */
str r1, [r0]
ldr r0, PLLFEED_ADR /* start feed sequence */
str r3, [r0]
str r4, [r0] /* feed sequence done */
/* Then enable the PLL */
ldr r0, PLLCON_ADR
mov r1, #0x01 /* PLL enable bit */
str r1, [r0]
ldr r0, PLLFEED_ADR /* start feed sequence */
str r3, [r0]
str r4, [r0] /* feed sequence done */
/* Wait for the lock */
ldr r0, PLLSTAT_ADR
mov r1, #0x400 /* lock bit */
lock_loop:
ldr r2, [r0]
and r2, r1, r2
cmp r2, #0
beq lock_loop
/* And finally connect the PLL */
ldr r0, PLLCON_ADR
mov r1, #0x03 /* PLL enable bit and connect bit */
str r1, [r0]
ldr r0, PLLFEED_ADR /* start feed sequence */
str r3, [r0]
str r4, [r0] /* feed sequence done */
/* Set-up VPBDIV register */
ldr r0, VPBDIV_ADR
mov r1, #0x01 /* VPB clock is same as process clock */
str r1, [r0]
#else
#error No cpu_init_crit() defined for current CPU type
#endif
@ -321,6 +383,7 @@ cpu_init_crit:
str r1, [r0]
#endif
#ifndef CONFIG_LPC2292
mov ip, lr
/*
* before relocating, we have to setup RAM timing
@ -329,6 +392,7 @@ cpu_init_crit:
*/
bl lowlevel_init
mov lr, ip
#endif
mov pc, lr
@ -537,6 +601,11 @@ reset_cpu:
* on external peripherals such as watchdog timers, etc. */
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* No specific reset actions for IntegratorAP/CM720T as yet */
#elif defined(CONFIG_LPC2292)
.align 5
.globl reset_cpu
reset_cpu:
mov pc, r0
#else
#error No reset_cpu() defined for current CPU type
#endif

12
cpu/ppc4xx/cpu.c
View file

@ -312,25 +312,29 @@ int checkcpu (void)
#endif /* CONFIG_440GR */
#endif /* CONFIG_440 */
case PVR_440EPX1_RA:
#ifdef CONFIG_440EPX
case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
puts("EPx Rev. A");
strcpy(addstr, "Security/Kasumi support");
break;
case PVR_440EPX2_RA:
case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
puts("EPx Rev. A");
strcpy(addstr, "No Security/Kasumi support");
break;
#endif /* CONFIG_440EPX */
case PVR_440GRX1_RA:
#ifdef CONFIG_440GRX
case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
puts("GRx Rev. A");
strcpy(addstr, "Security/Kasumi support");
break;
case PVR_440GRX2_RA:
case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
puts("GRx Rev. A");
strcpy(addstr, "No Security/Kasumi support");
break;
#endif /* CONFIG_440GRX */
case PVR_440SP_6_RAB:
puts("SP Rev. A/B");

2
include/asm-arm/arch-arm720t/hardware.h
View file

@ -36,6 +36,8 @@
/* include armadillo specific hardware file if there was one */
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* include IntegratorCP/CM720T specific hardware file if there was one */
#elif defined(CONFIG_LPC2292)
#include <asm-arm/arch-arm720t/lpc2292_registers.h>
#else
#error No hardware file defined for this configuration
#endif

225
include/asm-arm/arch-arm720t/lpc2292_registers.h Normal file
View file

@ -0,0 +1,225 @@
#ifndef __LPC2292_REGISTERS_H
#define __LPC2292_REGISTERS_H
#include <config.h>
/* Macros for reading/writing registers */
#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value))
#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value))
#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value))
#define GET8(reg) (*(volatile unsigned char*)(reg))
#define GET16(reg) (*(volatile unsigned short*)(reg))
#define GET32(reg) (*(volatile unsigned int*)(reg))
/* External Memory Controller */
#define BCFG0 0xFFE00000 /* 32-bits */
#define BCFG1 0xFFE00004 /* 32-bits */
#define BCFG2 0xFFE00008 /* 32-bits */
#define BCFG3 0xFFE0000c /* 32-bits */
/* System Control Block */
#define EXTINT 0xE01FC140
#define EXTWAKE 0xE01FC144
#define EXTMODE 0xE01FC148
#define EXTPOLAR 0xE01FC14C
#define MEMMAP 0xE01FC040
#define PLLCON 0xE01FC080
#define PLLCFG 0xE01FC084
#define PLLSTAT 0xE01FC088
#define PLLFEED 0xE01FC08C
#define PCON 0xE01FC0C0
#define PCONP 0xE01FC0C4
#define VPBDIV 0xE01FC100
/* Memory Acceleration Module */
#define MAMCR 0xE01FC000
#define MAMTIM 0xE01FC004
/* Vectored Interrupt Controller */
#define VICIRQStatus 0xFFFFF000
#define VICFIQStatus 0xFFFFF004
#define VICRawIntr 0xFFFFF008
#define VICIntSelect 0xFFFFF00C
#define VICIntEnable 0xFFFFF010
#define VICIntEnClr 0xFFFFF014
#define VICSoftInt 0xFFFFF018
#define VICSoftIntClear 0xFFFFF01C
#define VICProtection 0xFFFFF020
#define VICVectAddr 0xFFFFF030
#define VICDefVectAddr 0xFFFFF034
#define VICVectAddr0 0xFFFFF100
#define VICVectAddr1 0xFFFFF104
#define VICVectAddr2 0xFFFFF108
#define VICVectAddr3 0xFFFFF10C
#define VICVectAddr4 0xFFFFF110
#define VICVectAddr5 0xFFFFF114
#define VICVectAddr6 0xFFFFF118
#define VICVectAddr7 0xFFFFF11C
#define VICVectAddr8 0xFFFFF120
#define VICVectAddr9 0xFFFFF124
#define VICVectAddr10 0xFFFFF128
#define VICVectAddr11 0xFFFFF12C
#define VICVectAddr12 0xFFFFF130
#define VICVectAddr13 0xFFFFF134
#define VICVectAddr14 0xFFFFF138
#define VICVectAddr15 0xFFFFF13C
#define VICVectCntl0 0xFFFFF200
#define VICVectCntl1 0xFFFFF204
#define VICVectCntl2 0xFFFFF208
#define VICVectCntl3 0xFFFFF20C
#define VICVectCntl4 0xFFFFF210
#define VICVectCntl5 0xFFFFF214
#define VICVectCntl6 0xFFFFF218
#define VICVectCntl7 0xFFFFF21C
#define VICVectCntl8 0xFFFFF220
#define VICVectCntl9 0xFFFFF224
#define VICVectCntl10 0xFFFFF228
#define VICVectCntl11 0xFFFFF22C
#define VICVectCntl12 0xFFFFF230
#define VICVectCntl13 0xFFFFF234
#define VICVectCntl14 0xFFFFF238
#define VICVectCntl15 0xFFFFF23C
/* Pin connect block */
#define PINSEL0 0xE002C000 /* 32 bits */
#define PINSEL1 0xE002C004 /* 32 bits */
#define PINSEL2 0xE002C014 /* 32 bits */
/* GPIO */
#define IO0PIN 0xE0028000
#define IO0SET 0xE0028004
#define IO0DIR 0xE0028008
#define IO0CLR 0xE002800C
#define IO1PIN 0xE0028010
#define IO1SET 0xE0028014
#define IO1DIR 0xE0028018
#define IO1CLR 0xE002801C
#define IO2PIN 0xE0028020
#define IO2SET 0xE0028024
#define IO2DIR 0xE0028028
#define IO2CLR 0xE002802C
#define IO3PIN 0xE0028030
#define IO3SET 0xE0028034
#define IO3DIR 0xE0028038
#define IO3CLR 0xE002803C
/* Uarts */
#define U0RBR 0xE000C000
#define U0THR 0xE000C000
#define U0IER 0xE000C004
#define U0IIR 0xE000C008
#define U0FCR 0xE000C008
#define U0LCR 0xE000C00C
#define U0LSR 0xE000C014
#define U0SCR 0xE000C01C
#define U0DLL 0xE000C000
#define U0DLM 0xE000C004
#define U1RBR 0xE0010000
#define U1THR 0xE0010000
#define U1IER 0xE0010004
#define U1IIR 0xE0010008
#define U1FCR 0xE0010008
#define U1LCR 0xE001000C
#define U1MCR 0xE0010010
#define U1LSR 0xE0010014
#define U1MSR 0xE0010018
#define U1SCR 0xE001001C
#define U1DLL 0xE0010000
#define U1DLM 0xE0010004
/* I2C */
#define I2CONSET 0xE001C000
#define I2STAT 0xE001C004
#define I2DAT 0xE001C008
#define I2ADR 0xE001C00C
#define I2SCLH 0xE001C010
#define I2SCLL 0xE001C014
#define I2CONCLR 0xE001C018
/* SPI */
#define S0SPCR 0xE0020000
#define S0SPSR 0xE0020004
#define S0SPDR 0xE0020008
#define S0SPCCR 0xE002000C
#define S0SPINT 0xE002001C
#define S1SPCR 0xE0030000
#define S1SPSR 0xE0030004
#define S1SPDR 0xE0030008
#define S1SPCCR 0xE003000C
#define S1SPINT 0xE003001C
/* CAN controller */
/* skip for now */
/* Timers */
#define T0IR 0xE0004000
#define T0TCR 0xE0004004
#define T0TC 0xE0004008
#define T0PR 0xE000400C
#define T0PC 0xE0004010
#define T0MCR 0xE0004014
#define T0MR0 0xE0004018
#define T0MR1 0xE000401C
#define T0MR2 0xE0004020
#define T0MR3 0xE0004024
#define T0CCR 0xE0004028
#define T0CR0 0xE000402C
#define T0CR1 0xE0004030
#define T0CR2 0xE0004034
#define T0CR3 0xE0004038
#define T0EMR 0xE000403C
#define T1IR 0xE0008000
#define T1TCR 0xE0008004
#define T1TC 0xE0008008
#define T1PR 0xE000800C
#define T1PC 0xE0008010
#define T1MCR 0xE0008014
#define T1MR0 0xE0008018
#define T1MR1 0xE000801C
#define T1MR2 0xE0008020
#define T1MR3 0xE0008024
#define T1CCR 0xE0008028
#define T1CR0 0xE000802C
#define T1CR1 0xE0008030
#define T1CR2 0xE0008034
#define T1CR3 0xE0008038
#define T1EMR 0xE000803C
/* PWM */
/* skip for now */
/* A/D converter */
/* skip for now */
/* Real Time Clock */
/* skip for now */
/* Watchdog */
#define WDMOD 0xE0000000
#define WDTC 0xE0000004
#define WDFEED 0xE0000008
#define WDTV 0xE000000C
/* EmbeddedICE LOGIC */
/* skip for now */
#endif

22
include/asm-arm/arch-arm720t/mmc.h Normal file
View file

@ -0,0 +1,22 @@
/*
* A dummy header file for use with the LPC2292 port to keep the
* compiler happy.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _MMC_ARM_TDM_H_
#define _MMC_ARM_TDM_H_
#endif /* _MMC_ARM_TDM_H_ */

4
include/asm-ppc/processor.h
View file

@ -740,8 +740,8 @@
#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */
#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */
#define PVR_440GRX1_RA 0x216218D8 /* 440GRX rev A with Security / Kasumi */
#define PVR_440GRX2_RA 0x216218DC /* 440GRX rev A without Security / Kasumi */
#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */
#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */
#define PVR_440GX_RA 0x51B21850
#define PVR_440GX_RB 0x51B21851
#define PVR_440GX_RC 0x51B21892

14
include/configs/alpr.h
View file

@ -1,5 +1,5 @@
/*
* (C) Copyright 2006
* (C) Copyright 2006-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -135,7 +135,7 @@
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo Type \"run kernelx\" to boot the system;" \
"echo"
#undef CONFIG_BOOTARGS
@ -144,7 +144,7 @@
"netdev=eth3\0" \
"hostname=alpr\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"nfsroot=${serverip}:${rootpath} ${init}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
@ -170,7 +170,6 @@
"ethact=ppc_4xx_eth3\0" \
"autoload=no\0" \
"ipconfig=dhcp;setenv serverip 11.0.0.152\0" \
"actkernel=kernel2\0" \
"load_fpga=fpga load 0 ffe00000 10dd9a\0" \
"mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \
"rootfstype=jffs2 init=/sbin/init\0" \
@ -178,8 +177,10 @@
";bootm 200000\0" \
"kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \
"addtty;bootm 200000\0" \
"kernel1=run ipconfig load_fpga kernel1_mtd\0" \
"kernel2=run ipconfig load_fpga kernel2_mtd\0" \
"kernel1=setenv actkernel 'kernel1';run load_fpga " \
"kernel1_mtd\0" \
"kernel2=setenv actkernel 'kernel2';run load_fpga " \
"kernel2_mtd\0" \
""
#define CONFIG_BOOTCOMMAND "run kernel2"
@ -244,6 +245,7 @@
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_ALT_MEMTEST 1 /* Enable more extensive memtest*/
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */

158
include/configs/lpc2292sodimm.h Normal file
View file

@ -0,0 +1,158 @@
/*
* (C) Copyright 2000
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* Configuation settings for the EP7312 board.
*
* Modified to work on Armadillo HT1070 ARM720T board
* (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
#undef CONFIG_INIT_CRITICAL /* undef for developing */
#undef CONFIG_SKIP_LOWLEVEL_INIT
#undef CONFIG_SKIP_RELOCATE_UBOOT
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
#define CONFIG_LPC2292
#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
#undef CONFIG_USE_IRQ /* don't need them anymore */
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
*/
/*
* select serial console configuration
*/
#define CONFIG_SERIAL1 1 /* we use Serial line 1 */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
/*
* Supported commands
*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_DHCP | \
CFG_CMD_FAT | \
CFG_CMD_MMC | \
CFG_CMD_NET | \
CFG_CMD_PING)
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 5
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "LPC2292SODIMM # " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x40000000 /* memtest works on */
#define CFG_MEMTEST_END 0x40000000 /* 4 ... 8 MB in DRAM */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR 0x00040000 /* default load address for armadillo: kernel img is here*/
#define CFG_SYS_CLK_FREQ 58982400 /* Hz */
#define CFG_HZ 2048 /* decrementer freq in Hz */
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x81000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB SDRAM */
#define PHYS_FLASH_1 0x80000000 /* Flash Bank #1 */
#define PHYS_FLASH_SIZE 0x00200000 /* 2 MB */
#define CFG_FLASH_BASE PHYS_FLASH_1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (0x0 + 0x3C000) /* Addr of Environment Sector */
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_MMC 1
#endif /* __CONFIG_H */

345
include/configs/mecp5200.h Normal file
View file

@ -0,0 +1,345 @@
/*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*************************************************************************
* (c) 2005 esd gmbh Hannover
*
*
* from IceCube.h file
* by Reinhard Arlt reinhard.arlt@esd-electronics.com
*
*************************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_ICECUBE 1 /* ... on IceCube board */
#define CONFIG_MECP5200 1 /* ... on MECP5200 board */
#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#if 0 /* test-only */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#else
#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
#endif
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
#define CONFIG_MII
#if 0 /* test-only !!! */
#define CONFIG_NET_MULTI 1
#define CONFIG_EEPRO100 1
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
#endif
#else /* MPC5100 */
#endif
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
/* USB */
#if 0
#define CONFIG_USB_OHCI
#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
#else
#define ADD_USB_CMD 0
#endif
/*
* Supported commands
*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_EEPROM | \
CFG_CMD_FAT | \
CFG_CMD_EXT2 | \
CFG_CMD_I2C | \
CFG_CMD_IDE | \
CFG_CMD_BSP | \
CFG_CMD_ELF)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
# define CFG_LOWBOOT 1
# define CFG_LOWBOOT16 1
#endif
#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
# define CFG_LOWBOOT 1
# define CFG_LOWBOOT08 1
#endif
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
"echo Welcome to CBX-CPU5200 (mecp5200);" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
"net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
"vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
"loadaddr=01000000\0" \
"serverip=192.168.2.99\0" \
"gatewayip=10.0.0.79\0" \
"user=mu\0" \
"target=mecp5200.esd\0" \
"script=mecp5200.bat\0" \
"image=/tftpboot/vxWorks_mecp5200\0" \
"ipaddr=10.0.13.196\0" \
"netmask=255.255.0.0\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_vxworks0"
#if defined(CONFIG_MPC5200)
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#endif
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
#define CFG_I2C_SPEED 86000 /* 100 kHz */
#define CFG_I2C_SLAVE 0x7F
/*
* EEPROM configuration
*/
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_EEPROM_PAGE_WRITE_BITS 5
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
#define CFG_I2C_MULTI_EEPROMS 1
/*
* Flash configuration
*/
#define CFG_FLASH_BASE 0xFFC00000
#define CFG_FLASH_SIZE 0x00400000
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x003E0000)
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
#define CFG_MAX_FLASH_SECT 512
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
/*
* Environment settings
*/
#if 1 /* test-only */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x10000
#define CFG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_OVERWRITE 1
#else
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CFG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars*/
/* total size of a CAT24WC32 is 8192 bytes */
#define CONFIG_ENV_OVERWRITE 1
#endif
#define CFG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
#if 0
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#endif
#define CFG_FLASH_INCREMENT 0x00400000 /* size of flash bank */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */
/*
* Memory map
*/
#define CFG_MBAR 0xF0000000
#define CFG_SDRAM_BASE 0x00000000
#define CFG_DEFAULT_MBAR 0x80000000
/* Use SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT 1
#endif
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
/*
* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
*/
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR 0x00
#define CONFIG_UDP_CHECKSUM 1
/*
* GPIO configuration
*/
#define CFG_GPS_PORT_CONFIG 0x01052444
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
/*
* Various low-level settings
*/
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL HID0_ICE
#else
#define CFG_HID0_INIT 0
#define CFG_HID0_FINAL 0
#endif
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG 0x00085d00
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
#define CFG_CS1_START 0xfd000000
#define CFG_CS1_SIZE 0x00010000
#define CFG_CS1_CFG 0x10101410
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333333
#define CFG_RESET_ADDRESS 0xff000000
/*-----------------------------------------------------------------------
* USB stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00001000
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#define CONFIG_IDE_RESET /* reset for ide supported */
#define CONFIG_IDE_PREINIT
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
#define CFG_ATA_IDE0_OFFSET 0x0000
#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */
#define CFG_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */
#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET (0x005C)
/* Interval between registers */
#define CFG_ATA_STRIDE 4
#endif /* __CONFIG_H */

11
include/configs/pdnb3.h
View file

@ -1,5 +1,5 @@
/*
* (C) Copyright 2006
* (C) Copyright 2006-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Configuation settings for the PDNB3 board.
@ -237,18 +237,19 @@
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
#if defined(CONFIG_SCPU)
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
/* no redundant environment on SCPU */
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
#else
#define CFG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */
#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
#endif
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
#if !defined(CONFIG_SCPU)
/*

30
include/configs/sequoia.h
View file

@ -1,5 +1,5 @@
/*
* (C) Copyright 2006
* (C) Copyright 2006-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
@ -23,7 +23,7 @@
*/
/************************************************************************
* sequoia.h - configuration for Sequoia board (PowerPC440EPx)
* sequoia.h - configuration for Sequoia & Rainier boards
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
@ -31,7 +31,7 @@
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
#ifndef CONFIG_RAINIER
#define CONFIG_SEQUOIA 1 /* Board is Sequoia */
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
@ -39,7 +39,7 @@
#define CONFIG_440GRX 1 /* Specific PPC440GRx */
#endif
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_SYS_CLK_FREQ 33000000 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
@ -222,9 +222,21 @@
#undef CONFIG_BOOTARGS
/* Setup some board specific values for the default environment variables */
#ifndef CONFIG_RAINIER
#define CONFIG_HOSTNAME sequoia
#define CFG_BOOTFILE "bootfile=/tftpboot/sequoia/uImage\0"
#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
#else
#define CONFIG_HOSTNAME rainier
#define CFG_BOOTFILE "bootfile=/tftpboot/rainier/uImage\0"
#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
CFG_BOOTFILE \
CFG_ROOTPATH \
"netdev=eth0\0" \
"hostname=sequoia\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
@ -238,13 +250,11 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xxFP\0" \
"bootfile=/tftpboot/sequoia/uImage\0" \
"kernel_addr=FC000000\0" \
"ramdisk_addr=FC180000\0" \
"load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0" \
"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
"cp.b 100000 FFFA0000 60000\0" \
"cp.b 200000 FFFA0000 60000\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
@ -349,7 +359,7 @@
*----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/

340
include/configs/yellowstone.h
View file

@ -1,340 +0,0 @@
/*
* (C) Copyright 2005-2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************************************
* yellowstone.h - configuration for YELLOWSTONE board
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_YOLLOWSTONE 1 /* Board is Yellowstone */
#define CONFIG_440GR 1 /* Specific PPC440EP support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_BOARD_RESET 1 /* call board_reset() */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
/*Don't change either of these*/
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/
/*Don't change either of these*/
#define CFG_USB_DEVICE 0x50000000
#define CFG_NVRAM_BASE_ADDR 0x80000000
#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
#define CFG_BOOT_BASE_ADDR 0xf0000000
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (8 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
/*define this if you want console on UART1*/
#undef CONFIG_UART1_CONSOLE
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
/*
* Define here the location of the environment variables (FLASH or EEPROM).
* Note: DENX encourages to use redundant environment in FLASH.
*/
#if 1
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#endif
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
#define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */
#define CFG_SDRAM_BANKS (2)
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#ifdef CFG_ENV_IS_IN_EEPROM
#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
#define CFG_ENV_OFFSET 0x0
#endif /* CFG_ENV_IS_IN_EEPROM */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=yellowstone\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/yellowstone/uImage\0" \
"kernel_addr=fc000000\0" \
"ramdisk_addr=fc180000\0" \
"load=tftp 100000 /tftpboot/yellowstone/u-boot.bin\0" \
"update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
"cp.b 100000 fff80000 80000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1 /* required for netconsole */
#define CONFIG_PHY1_ADDR 3
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_NETCONSOLE /* include NetConsole support */
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#ifdef CONFIG_440EP
/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/*Comment this out to enable USB 1.1 device*/
#define USB_2_0_DEVICE
#endif /*CONFIG_440EP*/
#ifdef DEBUG
#define CONFIG_PANIC_HANG
#else
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI 1 /* support kdi files */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
#define CFG_FLASH CFG_FLASH_BASE
#define CFG_CPLD 0x80000000
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CFG_EBC_PB0AP 0x03017300
#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000)
/* Memory Bank 2 (CPLD) initialization */
#define CFG_EBC_PB2AP 0x04814500
#define CFG_EBC_PB2CR (CFG_CPLD | 0x18000)
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#endif /* __CONFIG_H */

54
include/configs/yosemite.h
View file

@ -1,5 +1,5 @@
/*
* (C) Copyright 2005-2006
* (C) Copyright 2005-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -22,7 +22,7 @@
*/
/************************************************************************
* yosemite.h - configuration for YOSEMITE board
* yosemite.h - configuration for Yosemite & Yellowstone boards
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
@ -30,9 +30,16 @@
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_YOSEMITE 1 /* Board is Yosemite */
#define CONFIG_440EP 1 /* Specific PPC440EP support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
/* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/
#ifndef CONFIG_YELLOWSTONE
#define CONFIG_YOSEMITE 1 /* Board is Yosemite */
#define CONFIG_440EP 1 /* Specific PPC440EP support */
#define CONFIG_HOSTNAME yosemite
#else
#define CONFIG_440GR 1 /* Specific PPC440GR support */
#define CONFIG_HOSTNAME yellowstone
#endif
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
@ -159,9 +166,21 @@
#undef CONFIG_BOOTARGS
/* Setup some board specific values for the default environment variables */
#ifndef CONFIG_YELLOWSTONE
#define CONFIG_HOSTNAME yosemite
#define CFG_BOOTFILE "bootfile=/tftpboot/yosemite/uImage\0"
#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
#else
#define CONFIG_HOSTNAME yellowstone
#define CFG_BOOTFILE "bootfile=/tftpboot/yellowstone/uImage\0"
#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
CFG_BOOTFILE \
CFG_ROOTPATH \
"netdev=eth0\0" \
"hostname=yosemite\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
@ -175,13 +194,12 @@
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/yosemite/uImage\0" \
"bootfile=/tftpboot/${hostname}/uImage\0" \
"kernel_addr=fc000000\0" \
"ramdisk_addr=fc180000\0" \
"load=tftp 100000 /tftpboot/yosemite/u-boot.bin\0" \
"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
"update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
"cp.b 100000 fff80000 80000;" \
"cp.b 200000 fff80000 80000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
@ -218,9 +236,15 @@
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/*Comment this out to enable USB 1.1 device*/
/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE
#endif /*CONFIG_440EP*/
#define CMD_USB (CFG_CMD_USB | CFG_CMD_FAT | CFG_CMD_EXT2)
#define CONFIG_SUPPORT_VFAT
#else
#define CMD_USB 0 /* no USB on 440GR */
#endif /* CONFIG_440EP */
#ifdef DEBUG
#define CONFIG_PANIC_HANG
@ -243,11 +267,7 @@
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CFG_CMD_FAT | \
CFG_CMD_EXT2 | \
CFG_CMD_USB )
#define CONFIG_SUPPORT_VFAT
CMD_USB)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

1
include/flash.h
View file

@ -304,6 +304,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
#define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */
#define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */
#define PHILIPS_LPC2292 0x0401FF13 /* LPC2292 internal FLASH */
/*-----------------------------------------------------------------------
* Internal FLASH identification codes