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https://github.com/AsahiLinux/u-boot
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usb: musb: add support for Blackfin MUSB
Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Remy Bohmer <linux@bohmer.net>
This commit is contained in:
Bryan Wu
Remy Bohmer
parent
bc72a919e0
commit
e608f221c1
7 changed files with 528 additions and 2 deletions
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@ -27,6 +27,7 @@ LIB := $(obj)libusb_musb.a
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COBJS-$(CONFIG_MUSB_HCD) += musb_hcd.o musb_core.o
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COBJS-$(CONFIG_MUSB_UDC) += musb_udc.o musb_core.o
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COBJS-$(CONFIG_USB_BLACKFIN) += blackfin_usb.o
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COBJS-$(CONFIG_USB_DAVINCI) += davinci.o
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COBJS-$(CONFIG_USB_OMAP3) += omap3.o
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COBJS-$(CONFIG_USB_DA8XX) += da8xx.o
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143
drivers/usb/musb/blackfin_usb.c
Normal file
143
drivers/usb/musb/blackfin_usb.c
Normal file
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@ -0,0 +1,143 @@
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/*
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* Blackfin MUSB HCD (Host Controller Driver) for u-boot
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*
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* Copyright (c) 2008-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <usb.h>
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#include <asm/blackfin.h>
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#include <asm/mach-common/bits/usb.h>
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#include "musb_core.h"
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/* MUSB platform configuration */
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struct musb_config musb_cfg = {
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.regs = (struct musb_regs *)USB_FADDR,
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.timeout = 0x3FFFFFF,
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.musb_speed = 0,
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};
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/*
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* This function read or write data to endpoint fifo
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* Blackfin use DMA polling method to avoid buffer alignment issues
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*
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* ep - Endpoint number
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* length - Number of bytes to write to FIFO
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* fifo_data - Pointer to data buffer to be read/write
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* is_write - Flag for read or write
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*/
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void rw_fifo(u8 ep, u32 length, void *fifo_data, int is_write)
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{
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struct bfin_musb_dma_regs *regs;
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u32 val = (u32)fifo_data;
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blackfin_dcache_flush_invalidate_range(fifo_data, fifo_data + length);
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regs = (void *)USB_DMA_INTERRUPT;
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regs += ep;
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/* Setup DMA address register */
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bfin_write16(®s->addr_low, val);
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SSYNC();
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bfin_write16(®s->addr_high, val >> 16);
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SSYNC();
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/* Setup DMA count register */
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bfin_write16(®s->count_low, length);
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bfin_write16(®s->count_high, 0);
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SSYNC();
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/* Enable the DMA */
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val = (ep << 4) | DMA_ENA | INT_ENA;
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if (is_write)
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val |= DIRECTION;
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bfin_write16(®s->control, val);
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SSYNC();
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/* Wait for compelete */
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while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << ep)))
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continue;
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/* acknowledge dma interrupt */
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bfin_write_USB_DMA_INTERRUPT(1 << ep);
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SSYNC();
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/* Reset DMA */
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bfin_write16(®s->control, 0);
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SSYNC();
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}
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void write_fifo(u8 ep, u32 length, void *fifo_data)
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{
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rw_fifo(ep, length, fifo_data, 1);
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}
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void read_fifo(u8 ep, u32 length, void *fifo_data)
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{
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rw_fifo(ep, length, fifo_data, 0);
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}
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/*
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* CPU and board-specific MUSB initializations. Aliased function
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* signals caller to move on.
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*/
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static void __def_musb_init(void)
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{
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}
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void board_musb_init(void) __attribute__((weak, alias("__def_musb_init")));
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int musb_platform_init(void)
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{
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/* board specific initialization */
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board_musb_init();
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if (ANOMALY_05000346) {
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bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
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SSYNC();
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}
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if (ANOMALY_05000347) {
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bfin_write_USB_APHY_CNTRL(0x0);
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SSYNC();
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}
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/* Configure PLL oscillator register */
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bfin_write_USB_PLLOSC_CTRL(0x30a8);
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SSYNC();
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bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
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SSYNC();
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bfin_write_USB_EP_NI0_RXMAXP(64);
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SSYNC();
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bfin_write_USB_EP_NI0_TXMAXP(64);
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SSYNC();
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/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
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bfin_write_USB_GLOBINTR(0x7);
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SSYNC();
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bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
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EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
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EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
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EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
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EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
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SSYNC();
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return 0;
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}
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/*
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* This function performs Blackfin platform specific deinitialization for usb.
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*/
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void musb_platform_deinit(void)
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{
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}
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99
drivers/usb/musb/blackfin_usb.h
Normal file
99
drivers/usb/musb/blackfin_usb.h
Normal file
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@ -0,0 +1,99 @@
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/*
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* Blackfin MUSB HCD (Host Controller Driver) for u-boot
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*
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* Copyright (c) 2008-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef __BLACKFIN_USB_H__
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#define __BLACKFIN_USB_H__
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#include <linux/types.h>
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/* Every register is 32bit aligned, but only 16bits in size */
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#define ureg(name) u16 name; u16 __pad_##name;
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#define musb_regs musb_regs
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struct musb_regs {
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/* common registers */
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ureg(faddr)
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ureg(power)
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ureg(intrtx)
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ureg(intrrx)
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ureg(intrtxe)
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ureg(intrrxe)
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ureg(intrusb)
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ureg(intrusbe)
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ureg(frame)
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ureg(index)
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ureg(testmode)
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ureg(globintr)
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ureg(global_ctl)
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u32 reserved0[3];
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/* indexed registers */
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ureg(txmaxp)
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ureg(txcsr)
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ureg(rxmaxp)
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ureg(rxcsr)
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ureg(rxcount)
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ureg(txtype)
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ureg(txinterval)
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ureg(rxtype)
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ureg(rxinterval)
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u32 reserved1;
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ureg(txcount)
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u32 reserved2[5];
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/* fifo */
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u16 fifox[32];
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/* OTG, dynamic FIFO, version & vendor registers */
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u32 reserved3[16];
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ureg(devctl)
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ureg(vbus_irq)
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ureg(vbus_mask)
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u32 reserved4[15];
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ureg(linkinfo)
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ureg(vplen)
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ureg(hseof1)
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ureg(fseof1)
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ureg(lseof1)
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u32 reserved5[41];
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/* target address registers */
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struct musb_tar_regs {
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ureg(txmaxp)
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ureg(txcsr)
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ureg(rxmaxp)
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ureg(rxcsr)
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ureg(rxcount)
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ureg(txtype)
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ureg(txinternal)
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ureg(rxtype)
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ureg(rxinternal)
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u32 reserved6;
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ureg(txcount)
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u32 reserved7[5];
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} tar[8];
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} __attribute__((packed));
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struct bfin_musb_dma_regs {
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ureg(interrupt);
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ureg(control);
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ureg(addr_low);
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ureg(addr_high);
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ureg(count_low);
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ureg(count_high);
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ureg(pad);
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};
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#undef ureg
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/* EP5-EP7 are the only ones with 1024 byte FIFOs which BULK really needs */
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#define MUSB_BULK_EP 5
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/* Blackfin FIFO's are static */
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#define MUSB_NO_DYNAMIC_FIFO
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/* No HUB support :( */
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#define MUSB_NO_MULTIPOINT
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#endif
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@ -38,6 +38,10 @@
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#include <usb_defs.h>
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#include <asm/io.h>
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#ifdef CONFIG_USB_BLACKFIN
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# include "blackfin_usb.h"
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#endif
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#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */
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/* EP0 */
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@ -71,6 +75,7 @@ struct musb_epN_regs {
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};
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/* Mentor USB core register overlay structure */
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#ifndef musb_regs
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struct musb_regs {
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/* common registers */
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u8 faddr;
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@ -138,6 +143,7 @@ struct musb_regs {
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} ep[16];
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} __attribute__((packed, aligned(32)));
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#endif
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/*
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* MUSB Register bits
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@ -347,4 +353,14 @@ extern void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt);
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extern void write_fifo(u8 ep, u32 length, void *fifo_data);
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extern void read_fifo(u8 ep, u32 length, void *fifo_data);
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#if defined(CONFIG_USB_BLACKFIN)
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/* Every USB register is accessed as a 16-bit even if the value itself
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* is only 8-bits in size. Fun stuff.
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*/
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# undef readb
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# define readb(addr) (u8)bfin_read16(addr)
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# undef writeb
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# define writeb(b, addr) bfin_write16(addr, b)
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#endif
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#endif /* __MUSB_HDRC_DEFS_H__ */
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@ -38,7 +38,9 @@ extern unsigned char new[];
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#define MUSB_CONTROL_EP 0
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/* This defines the endpoint number used for bulk transfer */
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#define MUSB_BULK_EP 1
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#ifndef MUSB_BULK_EP
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# define MUSB_BULK_EP 1
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#endif
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/* This defines the endpoint number used for interrupt transfer */
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#define MUSB_INTR_EP 2
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264
include/asm-blackfin/mach-common/bits/usb.h
Normal file
264
include/asm-blackfin/mach-common/bits/usb.h
Normal file
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@ -0,0 +1,264 @@
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/*
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* USB Masks
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*/
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#ifndef __BFIN_PERIPHERAL_USB__
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#define __BFIN_PERIPHERAL_USB__
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/* Bit masks for USB_FADDR */
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#define FUNCTION_ADDRESS 0x7f /* Function address */
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/* Bit masks for USB_POWER */
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#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
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#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
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#define RESUME_MODE 0x4 /* DMA Mode */
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#define RESET 0x8 /* Reset indicator */
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#define HS_MODE 0x10 /* High Speed mode indicator */
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#define HS_ENABLE 0x20 /* high Speed Enable */
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#define SOFT_CONN 0x40 /* Soft connect */
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#define ISO_UPDATE 0x80 /* Isochronous update */
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/* Bit masks for USB_INTRTX */
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#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
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#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
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#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
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#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
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#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
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#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
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#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
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#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
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/* Bit masks for USB_INTRRX */
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#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
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#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
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#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
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#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
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#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
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#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
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#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
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/* Bit masks for USB_INTRTXE */
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#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
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#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt enable */
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#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt enable */
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#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt enable */
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#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt enable */
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#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt enable */
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#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt enable */
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#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt enable */
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/* Bit masks for USB_INTRRXE */
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#define EP1_RX_E 0x02 /* Rx Endpoint 1 interrupt enable */
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#define EP2_RX_E 0x04 /* Rx Endpoint 2 interrupt enable */
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#define EP3_RX_E 0x08 /* Rx Endpoint 3 interrupt enable */
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#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt enable */
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#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt enable */
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#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt enable */
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#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt enable */
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/* Bit masks for USB_INTRUSB */
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#define SUSPEND_B 0x01 /* Suspend indicator */
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#define RESUME_B 0x02 /* Resume indicator */
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#define RESET_OR_BABLE_B 0x04 /* Reset/babble indicator */
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#define SOF_B 0x08 /* Start of frame */
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#define CONN_B 0x10 /* Connection indicator */
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#define DISCON_B 0x20 /* Disconnect indicator */
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#define SESSION_REQ_B 0x40 /* Session Request */
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#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
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/* Bit masks for USB_INTRUSBE */
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#define SUSPEND_BE 0x01 /* Suspend indicator int enable */
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#define RESUME_BE 0x02 /* Resume indicator int enable */
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#define RESET_OR_BABLE_BE 0x04 /* Reset/babble indicator int enable */
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#define SOF_BE 0x08 /* Start of frame int enable */
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#define CONN_BE 0x10 /* Connection indicator int enable */
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#define DISCON_BE 0x20 /* Disconnect indicator int enable */
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#define SESSION_REQ_BE 0x40 /* Session Request int enable */
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#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
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/* Bit masks for USB_FRAME */
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#define FRAME_NUMBER 0x7ff /* Frame number */
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/* Bit masks for USB_INDEX */
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#define SELECTED_ENDPOINT 0xf /* selected endpoint */
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/* Bit masks for USB_GLOBAL_CTL */
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#define GLOBAL_ENA 0x0001 /* enables USB module */
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#define EP1_TX_ENA 0x0002 /* Transmit endpoint 1 enable */
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#define EP2_TX_ENA 0x0004 /* Transmit endpoint 2 enable */
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#define EP3_TX_ENA 0x0008 /* Transmit endpoint 3 enable */
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#define EP4_TX_ENA 0x0010 /* Transmit endpoint 4 enable */
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#define EP5_TX_ENA 0x0020 /* Transmit endpoint 5 enable */
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#define EP6_TX_ENA 0x0040 /* Transmit endpoint 6 enable */
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#define EP7_TX_ENA 0x0080 /* Transmit endpoint 7 enable */
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#define EP1_RX_ENA 0x0100 /* Receive endpoint 1 enable */
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#define EP2_RX_ENA 0x0200 /* Receive endpoint 2 enable */
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#define EP3_RX_ENA 0x0400 /* Receive endpoint 3 enable */
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#define EP4_RX_ENA 0x0800 /* Receive endpoint 4 enable */
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#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
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#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
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#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
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/* Bit masks for USB_OTG_DEV_CTL */
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#define SESSION 0x1 /* session indicator */
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#define HOST_REQ 0x2 /* Host negotiation request */
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#define HOST_MODE 0x4 /* indicates USBDRC is a host */
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#define VBUS0 0x8 /* Vbus level indicator[0] */
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#define VBUS1 0x10 /* Vbus level indicator[1] */
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#define LSDEV 0x20 /* Low-speed indicator */
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#define FSDEV 0x40 /* Full or High-speed indicator */
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#define B_DEVICE 0x80 /* A' or 'B' device indicator */
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/* Bit masks for USB_OTG_VBUS_IRQ */
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#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
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#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
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#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
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#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
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#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
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#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
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/* Bit masks for USB_OTG_VBUS_MASK */
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||||
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||||
#define DRIVE_VBUS_ON_ENA 0x01 /* enable DRIVE_VBUS_ON interrupt */
|
||||
#define DRIVE_VBUS_OFF_ENA 0x02 /* enable DRIVE_VBUS_OFF interrupt */
|
||||
#define CHRG_VBUS_START_ENA 0x04 /* enable CHRG_VBUS_START interrupt */
|
||||
#define CHRG_VBUS_END_ENA 0x08 /* enable CHRG_VBUS_END interrupt */
|
||||
#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
|
||||
#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
|
||||
|
||||
/* Bit masks for USB_CSR0 */
|
||||
|
||||
#define RXPKTRDY 0x1 /* data packet receive indicator */
|
||||
#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
|
||||
#define STALL_SENT 0x4 /* STALL handshake sent */
|
||||
#define DATAEND 0x8 /* Data end indicator */
|
||||
#define SETUPEND 0x10 /* Setup end */
|
||||
#define SENDSTALL 0x20 /* Send STALL handshake */
|
||||
#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
|
||||
#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
|
||||
#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
|
||||
#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
|
||||
#define SETUPPKT_H 0x8 /* send Setup token host mode */
|
||||
#define ERROR_H 0x10 /* timeout error indicator host mode */
|
||||
#define REQPKT_H 0x20 /* Request an IN transaction host mode */
|
||||
#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
|
||||
#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
|
||||
|
||||
/* Bit masks for USB_COUNT0 */
|
||||
|
||||
#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
|
||||
|
||||
/* Bit masks for USB_NAKLIMIT0 */
|
||||
|
||||
#define EP0_NAK_LIMIT 0x1f /* frames/micro frames count after which EP0 timeouts */
|
||||
|
||||
/* Bit masks for USB_TX_MAX_PACKET */
|
||||
|
||||
#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
|
||||
|
||||
/* Bit masks for USB_RX_MAX_PACKET */
|
||||
|
||||
#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
|
||||
|
||||
/* Bit masks for USB_TXCSR */
|
||||
|
||||
#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
|
||||
#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
|
||||
#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
|
||||
#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
|
||||
#define STALL_SEND_T 0x10 /* issue a Stall handshake */
|
||||
#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
|
||||
#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
|
||||
#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
|
||||
#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
|
||||
#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
|
||||
#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
|
||||
#define ISO_T 0x4000 /* enable Isochronous transfers */
|
||||
#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
|
||||
#define ERROR_TH 0x4 /* error condition host mode */
|
||||
#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
|
||||
#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
|
||||
|
||||
/* Bit masks for USB_TXCOUNT */
|
||||
|
||||
#define TX_COUNT 0x1fff /* Byte len for the selected endpoint Tx FIFO */
|
||||
|
||||
/* Bit masks for USB_RXCSR */
|
||||
|
||||
#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
|
||||
#define FIFO_FULL_R 0x2 /* FIFO not empty */
|
||||
#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
|
||||
#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
|
||||
#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
|
||||
#define STALL_SEND_R 0x20 /* issue a Stall handshake */
|
||||
#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
|
||||
#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
|
||||
#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
|
||||
#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
|
||||
#define DISNYET_R 0x1000 /* disable Nyet handshakes */
|
||||
#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
|
||||
#define ISO_R 0x4000 /* enable Isochronous transfers */
|
||||
#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
|
||||
#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
|
||||
#define REQPKT_RH 0x20 /* request an IN transaction host mode */
|
||||
#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
|
||||
#define INCOMPRX_RH 0x100 /* large packet is split host mode */
|
||||
#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
|
||||
#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
|
||||
|
||||
/* Bit masks for USB_RXCOUNT */
|
||||
|
||||
#define RX_COUNT 0x1fff /* Packet byte len in the Rx FIFO */
|
||||
|
||||
/* Bit masks for USB_TXTYPE */
|
||||
|
||||
#define TARGET_EP_NO_T 0xf /* EP number */
|
||||
#define PROTOCOL_T 0xc /* transfer type */
|
||||
|
||||
/* Bit masks for USB_TXINTERVAL */
|
||||
|
||||
#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
|
||||
|
||||
/* Bit masks for USB_RXTYPE */
|
||||
|
||||
#define TARGET_EP_NO_R 0xf /* EP number */
|
||||
#define PROTOCOL_R 0xc /* transfer type */
|
||||
|
||||
/* Bit masks for USB_RXINTERVAL */
|
||||
|
||||
#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
|
||||
|
||||
/* Bit masks for USB_DMA_INTERRUPT */
|
||||
|
||||
#define DMA0_INT 0x1 /* DMA0 pending interrupt */
|
||||
#define DMA1_INT 0x2 /* DMA1 pending interrupt */
|
||||
#define DMA2_INT 0x4 /* DMA2 pending interrupt */
|
||||
#define DMA3_INT 0x8 /* DMA3 pending interrupt */
|
||||
#define DMA4_INT 0x10 /* DMA4 pending interrupt */
|
||||
#define DMA5_INT 0x20 /* DMA5 pending interrupt */
|
||||
#define DMA6_INT 0x40 /* DMA6 pending interrupt */
|
||||
#define DMA7_INT 0x80 /* DMA7 pending interrupt */
|
||||
|
||||
/* Bit masks for USB_DMAxCONTROL */
|
||||
|
||||
#define DMA_ENA 0x1 /* DMA enable */
|
||||
#define DIRECTION 0x2 /* direction of DMA transfer */
|
||||
#define MODE 0x4 /* DMA Bus error */
|
||||
#define INT_ENA 0x8 /* Interrupt enable */
|
||||
#define EPNUM 0xf0 /* EP number */
|
||||
#define BUSERROR 0x100 /* DMA Bus error */
|
||||
|
||||
#endif
|
||||
|
|
@ -132,7 +132,8 @@ struct usb_device {
|
|||
defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_OHCI_NEW) || \
|
||||
defined(CONFIG_USB_SL811HS) || defined(CONFIG_USB_ISP116X_HCD) || \
|
||||
defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI) || \
|
||||
defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX)
|
||||
defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \
|
||||
defined(CONFIG_USB_BLACKFIN)
|
||||
|
||||
int usb_lowlevel_init(void);
|
||||
int usb_lowlevel_stop(void);
|
||||
|
|
|
|||
Loading…
Reference in a new issue