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https://github.com/AsahiLinux/u-boot
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board/ti/am43xx: add support for parallel NAND
This patch adds support for NAND device connected to GPMC chip-select on
following AM43xx EVM boards.
am437x-gp-evm: On this board, NAND Flash signals are muxed with eMMC, thus at a
time either eMMC or NAND can be enabled. Selection between eMMC and NAND is
controlled by:
(a) Statically using Jumper on connecter (J89) present on board.
(a) If Jumper on J89 is NOT used, then selection can be dynamically controlled
by driving SPI2_CS0[MUX_MODE=GPIO] pin via software:
SPI2_CS0 == 0: NAND (default)
SPI2_CS0 == 1: eMMC
am43x-epos-evm: On this board, NAND Flash control lines are muxed with QSPI,
Thus only one of the two can be used at a time. Selection is controlled by:
(a) Dynamically driving following GPIO pin from software
GPMC_A0(GPIO) == 0 NAND is selected (default)
NAND device (MT29F4G08AB) on these boards has:
- data-width=8bits
- blocksize=256KB
- pagesize=4KB
- oobsize=224 bytes
For above NAND device, ROM code expects the boot-loader to be flashed in BCH16
ECC scheme for NAND boot, So by default BCH16 ECC is enabled for AM43xx EVMs.
Signed-off-by: Pekon Gupta <pekon@ti.com>
This commit is contained in:
pekon gupta
Tom Rini
parent
3df3bc1e1d
commit
e53ad4b445
3 changed files with 107 additions and 1 deletions
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@ -626,6 +626,7 @@ int board_init(void)
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modena_init0_bw_integer, modena_init0_watermark_0;
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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gpmc_init();
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/* Clear all important bits for DSS errata that may need to be tweaked*/
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mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
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@ -73,7 +73,38 @@ static struct module_pin_mux gpio5_7_pin_mux[] = {
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{-1},
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};
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static struct module_pin_mux qspi_pin_mux[] = {
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#ifdef CONFIG_NAND
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static struct module_pin_mux nand_pin_mux[] = {
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{OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
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{OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
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{OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
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{OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
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{OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
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{OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
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{OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
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{OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
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#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
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{OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
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{OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
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{OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
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{OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
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{OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
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{OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
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{OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
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{OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
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#endif
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{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* Wait */
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{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* Write Protect */
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{OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* Chip-Select */
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{OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* Write Enable */
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{OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* Read Enable */
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{OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* Addr Latch Enable*/
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{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* Byte Enable */
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{-1},
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};
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#endif
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static __maybe_unused struct module_pin_mux qspi_pin_mux[] = {
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{OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
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{OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
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{OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */
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@ -97,12 +128,22 @@ void enable_board_pin_mux(void)
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if (board_is_gpevm()) {
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configure_module_pin_mux(gpio5_7_pin_mux);
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configure_module_pin_mux(rgmii1_pin_mux);
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#if defined(CONFIG_NAND)
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configure_module_pin_mux(nand_pin_mux);
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#endif
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} else if (board_is_sk()) {
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configure_module_pin_mux(rgmii1_pin_mux);
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#if defined(CONFIG_NAND)
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printf("Error: NAND flash not present on this board\n");
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#endif
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configure_module_pin_mux(qspi_pin_mux);
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} else if (board_is_eposevm()) {
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configure_module_pin_mux(rmii1_pin_mux);
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#if defined(CONFIG_NAND)
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configure_module_pin_mux(nand_pin_mux);
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#else
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configure_module_pin_mux(qspi_pin_mux);
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#endif
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}
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}
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@ -265,4 +265,68 @@
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#define CONFIG_SPL_NET_SUPPORT
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#define CONFIG_SYS_RX_ETH_BUFFER 64
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/* NAND support */
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#ifdef CONFIG_NAND
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/* NAND: device related configs */
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#define CONFIG_SYS_NAND_PAGE_SIZE 4096
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#define CONFIG_SYS_NAND_OOBSIZE 224
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#define CONFIG_SYS_NAND_BLOCK_SIZE (256*1024)
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#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
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CONFIG_SYS_NAND_PAGE_SIZE)
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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/* NAND: driver related configs */
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_NAND_OMAP_ELM
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
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10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
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20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
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30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
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40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \
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50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
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60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \
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70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
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80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \
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90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \
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100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
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110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \
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120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \
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130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \
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140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \
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150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \
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160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \
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170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \
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180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \
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190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
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200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
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}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 26
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#define MTDIDS_DEFAULT "nand0=nand.0"
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#define MTDPARTS_DEFAULT "mtdparts=nand.0:" \
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"256k(NAND.SPL)," \
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"256k(NAND.SPL.backup1)," \
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"256k(NAND.SPL.backup2)," \
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"256k(NAND.SPL.backup3)," \
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"512k(NAND.u-boot-spl-os)," \
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"1m(NAND.u-boot)," \
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"256k(NAND.u-boot-env)," \
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"256k(NAND.u-boot-env.backup1)," \
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"7m(NAND.kernel)," \
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"-(NAND.rootfs)"
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00180000
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/* NAND: SPL related configs */
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#ifdef CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_NAND_AM33XX_BCH
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#endif
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/* NAND: SPL falcon mode configs */
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#ifdef CONFIG_SPL_OS_BOOT
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#define CONFIG_CMD_SPL_NAND_OFS 0x00100000 /* os parameters */
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#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00300000 /* kernel offset */
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#define CONFIG_CMD_SPL_WRITE_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#endif
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#endif /* !CONFIG_NAND */
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#endif /* __CONFIG_AM43XX_EVM_H */
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