arm: exynos: add support for Exynos7420 SoC

Add support for Exynos7420 SoC. The Exynos7420 SoC has four Cortex-A57
and four Cortex-A53 CPUs and includes various peripheral controllers.

Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

arch/arm/dts/exynos7420.dtsi

@@ -0,0 +1,83 @@
+/*
+ * Samsung Exynos7420 SoC device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/exynos7420-clk.h>
+/ {
+	compatible = "samsung,exynos7420";
+
+	fin_pll: xxti {
+		compatible = "fixed-clock";
+		clock-output-names = "fin_pll";
+		u-boot,dm-pre-reloc;
+		#clock-cells = <0>;
+	};
+
+	clock_topc: clock-controller@10570000 {
+		compatible = "samsung,exynos7-clock-topc";
+		reg = <0x10570000 0x10000>;
+		u-boot,dm-pre-reloc;
+		#clock-cells = <1>;
+		clocks = <&fin_pll>;
+		clock-names = "fin_pll";
+	};
+
+	clock_top0: clock-controller@105d0000 {
+		compatible = "samsung,exynos7-clock-top0";
+		reg = <0x105d0000 0xb000>;
+		u-boot,dm-pre-reloc;
+		#clock-cells = <1>;
+		clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
+			 <&clock_topc DOUT_SCLK_BUS1_PLL>,
+			 <&clock_topc DOUT_SCLK_CC_PLL>,
+			 <&clock_topc DOUT_SCLK_MFC_PLL>;
+		clock-names = "fin_pll", "dout_sclk_bus0_pll",
+			      "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
+			      "dout_sclk_mfc_pll";
+	};
+
+	clock_peric1: clock-controller@14c80000 {
+		compatible = "samsung,exynos7-clock-peric1";
+		reg = <0x14c80000 0xd00>;
+		u-boot,dm-pre-reloc;
+		#clock-cells = <1>;
+		clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
+			 <&clock_top0 CLK_SCLK_UART1>,
+			 <&clock_top0 CLK_SCLK_UART2>,
+			 <&clock_top0 CLK_SCLK_UART3>;
+		clock-names = "fin_pll", "dout_aclk_peric1_66",
+			      "sclk_uart1", "sclk_uart2", "sclk_uart3";
+	};
+
+	pinctrl@13470000 {
+		compatible = "samsung,exynos7420-pinctrl";
+		reg = <0x13470000 0x1000>;
+		u-boot,dm-pre-reloc;
+
+		serial2_bus: serial2-bus {
+			samsung,pins = "gpd1-4", "gpd1-5";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	serial@14C30000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x14C30000 0x100>;
+		u-boot,dm-pre-reloc;
+		clocks = <&clock_peric1 PCLK_UART2>,
+			 <&clock_peric1 SCLK_UART2>;
+		clock-names = "uart", "clk_uart_baud0";
+		pinctrl-names = "default";
+		pinctrl-0 = <&serial2_bus>;
+	};
+};

arch/arm/mach-exynos/Kconfig

@@ -20,6 +20,14 @@ config ARCH_EXYNOS5
 	  Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs
 	  in this family including Exynos5250, Exynos5420 and Exynos5800.
 
+config ARCH_EXYNOS7
+	bool "Exynos7 SoC family"
+	select ARM64
+	help
+	  Samsung Exynos7 SoC family are based on ARM Cortex-A57 CPU or
+	  Cortex-A53 CPU (and some in a big.LITTLE configuration). There are
+	  multiple SoCs in this family including Exynos7420.
+
 endchoice
 
 if ARCH_EXYNOS4

arch/arm/mach-exynos/Makefile

@@ -7,6 +7,7 @@
 
 obj-y	+= soc.o
 obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o system.o
+obj-$(CONFIG_ARM64)	+= mmu-arm64.o
 
 obj-$(CONFIG_EXYNOS5420)	+= sec_boot.o
 

arch/arm/mach-exynos/mmu-arm64.c

@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_EXYNOS7420
+static struct mm_region exynos7420_mem_map[] = {
+	{
+		.base	= 0x10000000UL,
+		.size	= 0x10000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		.base	= 0x40000000UL,
+		.size	= 0x80000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* List terminator */
+		.base	= 0,
+		.size	= 0,
+		.attrs	= 0,
+	},
+};
+
+struct mm_region *mem_map = exynos7420_mem_map;
+#endif

arch/arm/mach-exynos/soc.c

@@ -23,3 +23,11 @@ void enable_caches(void)
 	dcache_enable();
 }
 #endif
+
+#ifdef CONFIG_ARM64
+void lowlevel_init(void)
+{
+	armv8_switch_to_el2();
+	armv8_switch_to_el1();
+}
+#endif

include/configs/espresso7420.h

@@ -0,0 +1,34 @@
+/*
+ * Configuration settings for the SAMSUNG ESPRESSO7420 board.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ESPRESSO7420_H
+#define __CONFIG_ESPRESSO7420_H
+
+#include <configs/exynos7420-common.h>
+
+#define CONFIG_BOARD_COMMON
+
+#define CONFIG_ESPRESSO7420
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_TEXT_BASE		0x43E00000
+#define CONFIG_SPL_STACK		CONFIG_IRAM_END
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_IRAM_END
+
+/* select serial console configuration */
+#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC1,115200n8\0"
+
+#define CONFIG_IDENT_STRING	" for ESPRESSO7420"
+#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC1,115200n8\0"
+
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS	8
+#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
+
+#endif	/* __CONFIG_ESPRESSO7420_H */

include/configs/exynos7420-common.h

@@ -0,0 +1,113 @@
+/*
+ * Configuration settings for the Espresso7420 board.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_EXYNOS7420_COMMON_H
+#define __CONFIG_EXYNOS7420_COMMON_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
+#define CONFIG_EXYNOS7420		/* Exynos7 Family */
+#define CONFIG_S5P
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <linux/sizes.h>
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Size of malloc() pool before and after relocation */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 << 20))
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		1024	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE			115200
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+/* Timer input clock frequency */
+#define COUNTER_FREQUENCY		24000000
+
+/* Device Tree */
+#define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420"
+
+/* IRAM Layout */
+#define CONFIG_IRAM_BASE		0x02100000
+#define CONFIG_IRAM_SIZE		0x58000
+#define CONFIG_IRAM_END			(CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
+
+/* Number of CPUs available */
+#define CONFIG_CORE_COUNT		0x8
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_CONSOLE_MUX
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
+
+/* Configuration of ENV Blocks */
+#define CONFIG_ENV_SIZE	(16 << 10) /* 16 KB */
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+
+#ifndef MEM_LAYOUT_ENV_SETTINGS
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"kernel_addr_r=0x42000000\0" \
+	"fdt_addr_r=0x43000000\0" \
+	"ramdisk_addr_r=0x43300000\0" \
+	"scriptaddr=0x50000000\0" \
+	"pxefile_addr_r=0x51000000\0"
+#endif
+
+#ifndef EXYNOS_DEVICE_SETTINGS
+#define EXYNOS_DEVICE_SETTINGS \
+	"stdin=serial\0" \
+	"stdout=serial\0" \
+	"stderr=serial\0"
+#endif
+
+#ifndef EXYNOS_FDTFILE_SETTING
+#define EXYNOS_FDTFILE_SETTING
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	EXYNOS_DEVICE_SETTINGS \
+	EXYNOS_FDTFILE_SETTING \
+	MEM_LAYOUT_ENV_SETTINGS
+
+#endif	/* __CONFIG_EXYNOS7420_COMMON_H */