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imx: mx6sxsabreauto: enable more dm drivers
Enable MMC/I2C/GPIO/PMIC/REGULATOR/PCA953X DM drivers for mx6sxsabreauto board. Drop non-DM code. Note: The i.MX DM drivers has such dependency. MXC GPIO -> MXC I2C -> PFUZE/REGULATOR MXC GPIO -> PCA953X MXC GPIO -> FSL_USDHC So the drivers needs to be enabled all to avoid compiling error. The uboot dm tree log: => dm tree Class Probed Name ---------------------------------------- root [ + ] root_driver thermal [ ] |-- imx_thermal simple_bus [ + ] |-- soc simple_bus [ + ] | |-- aips-bus@02000000 simple_bus [ ] | | |-- spba-bus@02000000 gpio [ + ] | | |-- gpio@0209c000 gpio [ + ] | | |-- gpio@020a0000 gpio [ + ] | | |-- gpio@020a4000 gpio [ + ] | | |-- gpio@020a8000 gpio [ + ] | | |-- gpio@020ac000 gpio [ + ] | | |-- gpio@020b0000 gpio [ + ] | | |-- gpio@020b4000 simple_bus [ ] | | |-- anatop@020c8000 simple_bus [ ] | | |-- snvs@020cc000 pinctrl [ + ] | | `-- iomuxc@020e0000 pinconfig [ + ] | | `-- imx6x-sabreauto pinconfig [ + ] | | |-- i2c2grp-1 pinconfig [ + ] | | |-- i2c3grp-2 pinconfig [ ] | | |-- uart1grp pinconfig [ + ] | | |-- usdhc3grp pinconfig [ ] | | |-- usdhc3grp-100mhz pinconfig [ ] | | |-- usdhc3grp-200mhz pinconfig [ + ] | | |-- usdhc4grp pinconfig [ + ] | | `-- vccsd3grp simple_bus [ + ] | |-- aips-bus@02100000 mmc [ + ] | | |-- usdhc@02198000 mmc [ + ] | | |-- usdhc@0219c000 i2c [ + ] | | |-- i2c@021a4000 i2c_generic [ + ] | | | |-- generic_8 i2c_generic [ + ] | | | `-- generic_4e i2c [ + ] | | `-- i2c@021a8000 gpio [ + ] | | |-- gpio@30 gpio [ + ] | | `-- gpio@32 simple_bus [ ] | `-- aips-bus@02200000 simple_bus [ ] | `-- spba-bus@02200000 simple_bus [ + ] `-- regulators regulator [ + ] `-- regulator@0 Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
parent
caf2578f65
commit
e389033f72
3 changed files with 69 additions and 209 deletions
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@ -16,12 +16,9 @@
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/io.h>
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#include <asm/imx-common/mxc_i2c.h>
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#include <linux/sizes.h>
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <mmc.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <power/pmic.h>
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@ -37,15 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | \
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PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
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@ -56,54 +44,11 @@ DECLARE_GLOBAL_DATA_PTR;
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#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
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#define I2C_PMIC 1
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#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
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#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
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PAD_CTL_SRE_FAST)
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#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
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/*Define for building port exp gpio, pin starts from 0*/
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#define PORTEXP_IO_NR(chip, pin) \
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((chip << 5) + pin)
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/*Get the chip addr from a ioexp gpio*/
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#define PORTEXP_IO_TO_CHIP(gpio_nr) \
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(gpio_nr >> 5)
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/*Get the pin number from a ioexp gpio*/
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#define PORTEXP_IO_TO_PIN(gpio_nr) \
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(gpio_nr & 0x1f)
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#define CPU_PER_RST_B PORTEXP_IO_NR(0x30, 4)
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#define STEER_ENET PORTEXP_IO_NR(0x32, 2)
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static int port_exp_direction_output(unsigned gpio, int value)
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{
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int ret;
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i2c_set_bus_num(2);
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ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
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if (ret)
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return ret;
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ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
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(1 << PORTEXP_IO_TO_PIN(gpio)),
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(PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
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if (ret)
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return ret;
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ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
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(1 << PORTEXP_IO_TO_PIN(gpio)),
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(value << PORTEXP_IO_TO_PIN(gpio)));
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if (ret)
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return ret;
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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@ -116,41 +61,6 @@ static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc3_pads[] = {
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MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/* CD pin */
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MX6_PAD_USB_H_DATA__GPIO7_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* RST_B, used for power reset cycle */
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MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc4_pads[] = {
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MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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/* CD pin */
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MX6_PAD_USB_H_STROBE__GPIO7_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const fec2_pads[] = {
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MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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@ -217,42 +127,43 @@ int board_phy_config(struct phy_device *phydev)
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return 0;
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}
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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/* I2C2 for PMIC */
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struct i2c_pads_info i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,
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.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
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.gp = IMX_GPIO_NR(1, 2),
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},
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.sda = {
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.i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,
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.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
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.gp = IMX_GPIO_NR(1, 3),
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},
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};
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/* I2C3 for IO Expander */
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struct i2c_pads_info i2c_pad_info3 = {
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.scl = {
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.i2c_mode = MX6_PAD_KEY_COL4__I2C3_SCL | PC,
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.gpio_mode = MX6_PAD_KEY_COL4__GPIO2_IO_14 | PC,
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.gp = IMX_GPIO_NR(2, 14),
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},
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.sda = {
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.i2c_mode = MX6_PAD_KEY_ROW4__I2C3_SDA | PC,
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.gpio_mode = MX6_PAD_KEY_ROW4__GPIO2_IO_19 | PC,
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.gp = IMX_GPIO_NR(2, 19),
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},
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};
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int power_init_board(void)
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{
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struct pmic *p;
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struct udevice *dev;
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int ret;
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u32 dev_id, rev_id, i;
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u32 switch_num = 6;
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u32 offset = PFUZE100_SW1CMODE;
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p = pfuze_common_init(I2C_PMIC);
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if (!p)
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return -ENODEV;
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ret = pmic_get("pfuze100", &dev);
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if (ret == -ENODEV)
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return 0;
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if (ret != 0)
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return ret;
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dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
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rev_id = pmic_reg_read(dev, PFUZE100_REVID);
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printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
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/* Init mode to APS_PFM */
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pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
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for (i = 0; i < switch_num - 1; i++)
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pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
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/* set SW1AB staby volatage 0.975V */
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pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
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/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
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pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
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/* set SW1C staby volatage 1.10V */
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pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20);
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/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
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pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
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return 0;
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}
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@ -307,78 +218,6 @@ int board_early_init_f(void)
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return 0;
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}
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static struct fsl_esdhc_cfg usdhc_cfg[3] = {
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{USDHC3_BASE_ADDR},
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{USDHC4_BASE_ADDR},
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};
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#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 10)
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#define USDHC3_RST_GPIO IMX_GPIO_NR(2, 11)
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#define USDHC4_CD_GPIO IMX_GPIO_NR(7, 11)
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC3_BASE_ADDR:
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ret = !gpio_get_value(USDHC3_CD_GPIO);
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break;
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case USDHC4_BASE_ADDR:
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ret = !gpio_get_value(USDHC4_CD_GPIO);
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break;
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}
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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int i, ret;
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/*
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* According to the board_mmc_init() the following map is done:
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* (U-Boot device node) (Physical Port)
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* mmc0 USDHC3
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* mmc1 USDHC4
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*/
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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switch (i) {
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case 0:
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imx_iomux_v3_setup_multiple_pads(
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usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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gpio_direction_input(USDHC3_CD_GPIO);
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/* This starts a power cycle for UHS-I. Need to set steer to B0 to A*/
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gpio_direction_output(USDHC3_RST_GPIO, 0);
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udelay(1000); /* need 1ms at least */
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gpio_direction_output(USDHC3_RST_GPIO, 1);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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break;
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case 1:
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imx_iomux_v3_setup_multiple_pads(
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usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
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gpio_direction_input(USDHC4_CD_GPIO);
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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break;
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default:
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printf("Warning: you configured more USDHC controllers"
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"(%d) than supported by the board\n", i + 1);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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if (ret) {
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printf("Warning: failed to initialize mmc dev %d\n", i);
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return ret;
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}
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}
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return 0;
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}
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#ifdef CONFIG_FSL_QSPI
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#define QSPI_PAD_CTRL1 \
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@ -450,21 +289,36 @@ static void setup_gpmi_nand(void)
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int board_init(void)
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{
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struct gpio_desc desc;
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int ret;
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/* Address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_SYS_I2C_MXC
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setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
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setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
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#endif
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ret = dm_gpio_lookup_name("gpio@30_4", &desc);
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if (ret)
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return ret;
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ret = dm_gpio_request(&desc, "cpu_per_rst_b");
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if (ret)
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return ret;
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/* Reset CPU_PER_RST_B signal for enet phy and PCIE */
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port_exp_direction_output(CPU_PER_RST_B, 0);
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dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
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udelay(500);
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port_exp_direction_output(CPU_PER_RST_B, 1);
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dm_gpio_set_value(&desc, 1);
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ret = dm_gpio_lookup_name("gpio@32_2", &desc);
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if (ret)
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return ret;
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ret = dm_gpio_request(&desc, "steer_enet");
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if (ret)
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return ret;
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dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
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udelay(500);
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/* Set steering signal to L for selecting B0 */
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port_exp_direction_output(STEER_ENET, 0);
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dm_gpio_set_value(&desc, 0);
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#ifdef CONFIG_USB_EHCI_MX6
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setup_usb();
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@ -19,17 +19,30 @@ CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_REGULATOR=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_OF_CONTROL=y
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# CONFIG_BLK is not set
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CONFIG_DM_GPIO=y
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CONFIG_DM_PCA953X=y
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CONFIG_DM_I2C=y
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CONFIG_DM_MMC=y
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# CONFIG_DM_MMC_OPS is not set
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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CONFIG_DM_PMIC=y
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CONFIG_DM_PMIC_PFUZE100=y
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CONFIG_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_PFUZE100=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_FSL_QSPI=y
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CONFIG_USB=y
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CONFIG_USB_STORAGE=y
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@ -114,19 +114,12 @@
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#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
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/* I2C Configs */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
/* PMIC */
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_PFUZE100
|
||||
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
|
||||
|
||||
/* NAND flash command */
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_NAND_TRIMFFS
|
||||
|
|
Loading…
Reference in a new issue