mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-02 09:30:10 +00:00
sunxi: switch PRCM to non-secure on H3/H5 SoCs
The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls the access to some clock/power related registers in PRCM. Current Linux kernel will access the CPUS (AR100) clock in the PRCM block, so the PRCM should be switched to non-secure. Add code to switch the PRCM to non-secure. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
This commit is contained in:
parent
39858b12cc
commit
e37a1b17e7
1 changed files with 6 additions and 0 deletions
|
@ -66,11 +66,17 @@ void clock_init_sec(void)
|
|||
#ifdef CONFIG_MACH_SUNXI_H3_H5
|
||||
struct sunxi_ccm_reg * const ccm =
|
||||
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
||||
struct sunxi_prcm_reg * const prcm =
|
||||
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
|
||||
|
||||
setbits_le32(&ccm->ccu_sec_switch,
|
||||
CCM_SEC_SWITCH_MBUS_NONSEC |
|
||||
CCM_SEC_SWITCH_BUS_NONSEC |
|
||||
CCM_SEC_SWITCH_PLL_NONSEC);
|
||||
setbits_le32(&prcm->prcm_sec_switch,
|
||||
PRCM_SEC_SWITCH_APB0_CLK_NONSEC |
|
||||
PRCM_SEC_SWITCH_PLL_CFG_NONSEC |
|
||||
PRCM_SEC_SWITCH_PWR_GATE_NONSEC);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in a new issue