mirror of
https://github.com/AsahiLinux/u-boot
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m68k: add DM model serial driver
Boards can now use DM serial driver, or still legacy mcf uart driver version. Signed-off-by: Angelo Dureghello <angelo@sysam.it> Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
angelo@sysam.it
Simon Glass
parent
5044c9cc6c
commit
e27802af54
2 changed files with 167 additions and 44 deletions
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@ -2,6 +2,9 @@
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* (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew, Tsi-Chung.Liew@freescale.com.
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*
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* Modified to add device model (DM) support
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* (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -11,9 +14,10 @@
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/platform_data/serial_coldfire.h>
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#include <serial.h>
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#include <linux/compiler.h>
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#include <asm/immap.h>
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#include <asm/uart.h>
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@ -21,91 +25,110 @@ DECLARE_GLOBAL_DATA_PTR;
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extern void uart_port_conf(int port);
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static int mcf_serial_init(void)
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static int mcf_serial_init_common(uart_t *uart, int port_idx, int baudrate)
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{
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volatile uart_t *uart;
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u32 counter;
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uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
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uart_port_conf(CONFIG_SYS_UART_PORT);
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uart_port_conf(port_idx);
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/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
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uart->ucr = UART_UCR_RESET_RX;
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uart->ucr = UART_UCR_RESET_TX;
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uart->ucr = UART_UCR_RESET_ERROR;
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uart->ucr = UART_UCR_RESET_MR;
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writeb(UART_UCR_RESET_RX, &uart->ucr);
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writeb(UART_UCR_RESET_TX, &uart->ucr);
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writeb(UART_UCR_RESET_ERROR, &uart->ucr);
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writeb(UART_UCR_RESET_MR, &uart->ucr);
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__asm__("nop");
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uart->uimr = 0;
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writeb(0, &uart->uimr);
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/* write to CSR: RX/TX baud rate from timers */
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uart->ucsr = (UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK);
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writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
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uart->umr = (UART_UMR_BC_8 | UART_UMR_PM_NONE);
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uart->umr = UART_UMR_SB_STOP_BITS_1;
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writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
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writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
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/* Setting up BaudRate */
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counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
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counter = counter / gd->baudrate;
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counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
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counter = counter / baudrate;
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/* write to CTUR: divide counter upper byte */
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uart->ubg1 = (u8) ((counter & 0xff00) >> 8);
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writeb((u8)((counter & 0xff00) >> 8), &uart->ubg1);
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/* write to CTLR: divide counter lower byte */
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uart->ubg2 = (u8) (counter & 0x00ff);
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writeb((u8)(counter & 0x00ff), &uart->ubg2);
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uart->ucr = (UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED);
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writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
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return (0);
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}
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static void mcf_serial_setbrg_common(uart_t *uart, int baudrate)
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{
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u32 counter;
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/* Setting up BaudRate */
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counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
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counter = counter / baudrate;
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/* write to CTUR: divide counter upper byte */
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writeb(((counter & 0xff00) >> 8), &uart->ubg1);
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/* write to CTLR: divide counter lower byte */
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writeb((counter & 0x00ff), &uart->ubg2);
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writeb(UART_UCR_RESET_RX, &uart->ucr);
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writeb(UART_UCR_RESET_TX, &uart->ucr);
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writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
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}
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#ifndef CONFIG_DM_SERIAL
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static int mcf_serial_init(void)
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{
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uart_t *uart_base;
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int port_idx;
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uart_base = (uart_t *)CONFIG_SYS_UART_BASE;
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port_idx = CONFIG_SYS_UART_PORT;
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return mcf_serial_init_common(uart_base, port_idx, gd->baudrate);
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}
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static void mcf_serial_putc(const char c)
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{
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volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
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uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
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if (c == '\n')
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serial_putc('\r');
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/* Wait for last character to go. */
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while (!(uart->usr & UART_USR_TXRDY)) ;
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while (!(readb(&uart->usr) & UART_USR_TXRDY))
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;
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uart->utb = c;
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writeb(c, &uart->utb);
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}
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static int mcf_serial_getc(void)
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{
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volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
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uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
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/* Wait for a character to arrive. */
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while (!(uart->usr & UART_USR_RXRDY)) ;
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return uart->urb;
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}
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while (!(readb(&uart->usr) & UART_USR_RXRDY))
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;
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static int mcf_serial_tstc(void)
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{
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volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
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return (uart->usr & UART_USR_RXRDY);
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return readb(&uart->urb);
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}
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static void mcf_serial_setbrg(void)
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{
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volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
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u32 counter;
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uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
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/* Setting up BaudRate */
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counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
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counter = counter / gd->baudrate;
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mcf_serial_setbrg_common(uart, gd->baudrate);
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}
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/* write to CTUR: divide counter upper byte */
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uart->ubg1 = ((counter & 0xff00) >> 8);
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/* write to CTLR: divide counter lower byte */
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uart->ubg2 = (counter & 0x00ff);
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static int mcf_serial_tstc(void)
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{
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uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
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uart->ucr = UART_UCR_RESET_RX;
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uart->ucr = UART_UCR_RESET_TX;
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uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED;
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return readb(&uart->usr) & UART_USR_RXRDY;
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}
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static struct serial_device mcf_serial_drv = {
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@ -128,3 +151,80 @@ __weak struct serial_device *default_serial_console(void)
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{
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return &mcf_serial_drv;
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}
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#endif
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#ifdef CONFIG_DM_SERIAL
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static int coldfire_serial_probe(struct udevice *dev)
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{
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struct coldfire_serial_platdata *plat = dev->platdata;
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return mcf_serial_init_common((uart_t *)plat->base,
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plat->port, plat->baudrate);
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}
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static int coldfire_serial_putc(struct udevice *dev, const char ch)
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{
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struct coldfire_serial_platdata *plat = dev->platdata;
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uart_t *uart = (uart_t *)plat->base;
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/* Wait for last character to go. */
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if (!(readb(&uart->usr) & UART_USR_TXRDY))
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return -EAGAIN;
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writeb(ch, &uart->utb);
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return 0;
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}
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static int coldfire_serial_getc(struct udevice *dev)
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{
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struct coldfire_serial_platdata *plat = dev->platdata;
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uart_t *uart = (uart_t *)(plat->base);
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/* Wait for a character to arrive. */
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if (!(readb(&uart->usr) & UART_USR_RXRDY))
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return -EAGAIN;
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return readb(&uart->urb);
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}
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int coldfire_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct coldfire_serial_platdata *plat = dev->platdata;
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uart_t *uart = (uart_t *)(plat->base);
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mcf_serial_setbrg_common(uart, baudrate);
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return 0;
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}
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static int coldfire_serial_pending(struct udevice *dev, bool input)
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{
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struct coldfire_serial_platdata *plat = dev->platdata;
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uart_t *uart = (uart_t *)(plat->base);
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if (input)
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return readb(&uart->usr) & UART_USR_RXRDY ? 1 : 0;
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else
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return readb(&uart->usr) & UART_USR_TXRDY ? 0 : 1;
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return 0;
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}
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static const struct dm_serial_ops coldfire_serial_ops = {
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.putc = coldfire_serial_putc,
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.pending = coldfire_serial_pending,
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.getc = coldfire_serial_getc,
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.setbrg = coldfire_serial_setbrg,
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};
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U_BOOT_DRIVER(serial_coldfire) = {
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.name = "serial_coldfire",
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.id = UCLASS_SERIAL,
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.probe = coldfire_serial_probe,
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.ops = &coldfire_serial_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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#endif
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23
include/dm/platform_data/serial_coldfire.h
Normal file
23
include/dm/platform_data/serial_coldfire.h
Normal file
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@ -0,0 +1,23 @@
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/*
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* Copyright (c) 2015 Angelo Dureghello <angelo@sysam.it>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __serial_coldfire_h
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#define __serial_coldfire_h
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/*
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* struct coldfire_serial_platdata - information about a coldfire port
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*
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* @base: Uart port base register address
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* @port: Uart port index, for cpu with pinmux for uart / gpio
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* baudrtatre: Uart port baudrate
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*/
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struct coldfire_serial_platdata {
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unsigned long base;
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int port;
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int baudrate;
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};
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#endif /* __serial_coldfire_h */
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