- Fix USB support for rk3399 Pinebook Pro;
- Fix SPI boot for rk3399 boards other than Bob;
- Fix 32bit boards firmware build without SPL_OPTEE support;
- Fix rockchip display driver license;
This commit is contained in:
Tom Rini 2020-11-16 09:50:21 -05:00
commit e1fdb2045a
18 changed files with 62 additions and 23 deletions

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@ -1721,7 +1721,7 @@ config ARCH_STM32MP
config ARCH_ROCKCHIP
bool "Support Rockchip SoCs"
select BLK
select BINMAN if !ARM64
select BINMAN if SPL_OPTEE
select DM
select DM_GPIO
select DM_I2C

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@ -6,10 +6,6 @@
#include "rk3399-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
/ {
aliases {
spi0 = &spi1;
};
chosen {
u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdmmc, &sdhci;
};

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@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015 Google, Inc
* Copyright 2014 Rockchip Inc.

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@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015 Google, Inc
* Copyright 2014 Rockchip Inc.

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@ -4,6 +4,7 @@
*/
#include <common.h>
#include <dm.h>
#include <init.h>
#ifdef CONFIG_SPL_BUILD
@ -31,3 +32,25 @@ int board_early_init_f(void)
return 0;
}
#endif
#ifndef CONFIG_SPL_BUILD
int board_early_init_r(void)
{
struct udevice *clk;
int ret;
/*
* This init is done in SPL, but when chain-loading U-Boot SPL will
* have been skipped. Allow the clock driver to check if it needs
* setting up.
*/
ret = uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(clk_rk3399), &clk);
if (ret) {
debug("%s: CLK init failed: %d\n", __func__, ret);
return ret;
}
return 0;
}
#endif

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@ -19,6 +19,11 @@ CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_BLOBLIST=y
CONFIG_BLOBLIST_SIZE=0x1000
CONFIG_BLOBLIST_ADDR=0x100000
CONFIG_HANDOFF=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000

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@ -55,6 +55,8 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_TYPEC=y
CONFIG_DM_PMIC_FAN53555=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
@ -76,8 +78,9 @@ CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_KEYBOARD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_RTL8152=y

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@ -32,6 +32,7 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_DM_KEYBOARD=y
@ -41,6 +42,7 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y

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@ -23,6 +23,8 @@
#include <linux/bitops.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3399_clk_plat {
struct dtd_rockchip_rk3399_cru dtd;
@ -50,10 +52,9 @@ struct pll_div {
.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
#if defined(CONFIG_SPL_BUILD)
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
#else
#if !defined(CONFIG_SPL_BUILD)
static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
#endif
@ -1293,7 +1294,6 @@ static struct clk_ops rk3399_clk_ops = {
.disable = rk3399_clk_disable,
};
#ifdef CONFIG_SPL_BUILD
static void rkclk_init(struct rockchip_cru *cru)
{
u32 aclk_div;
@ -1371,20 +1371,30 @@ static void rkclk_init(struct rockchip_cru *cru)
hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
}
#endif
static int rk3399_clk_probe(struct udevice *dev)
{
#ifdef CONFIG_SPL_BUILD
struct rk3399_clk_priv *priv = dev_get_priv(dev);
bool init_clocks = false;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3399_clk_plat *plat = dev_get_platdata(dev);
priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
rkclk_init(priv->cru);
#if defined(CONFIG_SPL_BUILD)
init_clocks = true;
#elif CONFIG_IS_ENABLED(HANDOFF)
if (!(gd->flags & GD_FLG_RELOC)) {
if (!(gd->spl_handoff))
init_clocks = true;
}
#endif
if (init_clocks)
rkclk_init(priv->cru);
return 0;
}

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@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
* Author: Eric Gao <eric.gao@rock-chips.com>

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@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
* Copyright (c) 2015 Google, Inc

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@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
* Author: Eric Gao <eric.gao@rock-chips.com>

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@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
* Copyright (c) 2015 Google, Inc

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@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015 Google, Inc
* Copyright 2014 Rockchip Inc.

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@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
* Author: Eric Gao <eric.gao@rock-chips.com>

View file

@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
* Author: Eric Gao <eric.gao@rock-chips.com>

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@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2015 Google, Inc
* Copyright 2014 Rockchip Inc.

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@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
*/