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https://github.com/AsahiLinux/u-boot
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Merge tag 'u-boot-rockchip-20201113' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Fix USB support for rk3399 Pinebook Pro; - Fix SPI boot for rk3399 boards other than Bob; - Fix 32bit boards firmware build without SPL_OPTEE support; - Fix rockchip display driver license;
This commit is contained in:
commit
e1fdb2045a
18 changed files with 62 additions and 23 deletions
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@ -1721,7 +1721,7 @@ config ARCH_STM32MP
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config ARCH_ROCKCHIP
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bool "Support Rockchip SoCs"
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select BLK
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select BINMAN if !ARM64
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select BINMAN if SPL_OPTEE
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select DM
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select DM_GPIO
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select DM_I2C
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@ -6,10 +6,6 @@
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#include "rk3399-u-boot.dtsi"
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#include "rk3399-sdram-lpddr4-100.dtsi"
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/ {
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aliases {
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spi0 = &spi1;
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};
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chosen {
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u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdmmc, &sdhci;
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};
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@ -1,4 +1,4 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2015 Google, Inc
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* Copyright 2014 Rockchip Inc.
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@ -1,4 +1,4 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2015 Google, Inc
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* Copyright 2014 Rockchip Inc.
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@ -4,6 +4,7 @@
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*/
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#include <common.h>
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#include <dm.h>
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#include <init.h>
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#ifdef CONFIG_SPL_BUILD
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@ -31,3 +32,25 @@ int board_early_init_f(void)
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return 0;
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}
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#endif
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#ifndef CONFIG_SPL_BUILD
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int board_early_init_r(void)
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{
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struct udevice *clk;
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int ret;
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/*
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* This init is done in SPL, but when chain-loading U-Boot SPL will
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* have been skipped. Allow the clock driver to check if it needs
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* setting up.
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*/
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(clk_rk3399), &clk);
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if (ret) {
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debug("%s: CLK init failed: %d\n", __func__, ret);
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return ret;
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}
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return 0;
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}
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#endif
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@ -19,6 +19,11 @@ CONFIG_DEBUG_UART=y
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CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_BOARD_EARLY_INIT_R=y
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CONFIG_BLOBLIST=y
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CONFIG_BLOBLIST_SIZE=0x1000
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CONFIG_BLOBLIST_ADDR=0x100000
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CONFIG_HANDOFF=y
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# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
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@ -55,6 +55,8 @@ CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_DM_ETH=y
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CONFIG_NVME=y
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CONFIG_PCI=y
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CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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CONFIG_PHY_ROCKCHIP_TYPEC=y
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CONFIG_DM_PMIC_FAN53555=y
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CONFIG_PMIC_RK8XX=y
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CONFIG_REGULATOR_PWM=y
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@ -76,8 +78,9 @@ CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_OHCI_HCD=y
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CONFIG_USB_OHCI_GENERIC=y
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CONFIG_USB_DWC3=y
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CONFIG_ROCKCHIP_USB2_PHY=y
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CONFIG_USB_DWC3_GENERIC=y
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CONFIG_USB_KEYBOARD=y
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CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
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CONFIG_USB_HOST_ETHER=y
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CONFIG_USB_ETHER_ASIX=y
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CONFIG_USB_ETHER_RTL8152=y
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@ -32,6 +32,7 @@ CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_DM_KEYBOARD=y
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@ -41,6 +42,7 @@ CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ROCKCHIP=y
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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@ -23,6 +23,8 @@
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#include <linux/bitops.h>
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#include <linux/delay.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct rk3399_clk_plat {
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struct dtd_rockchip_rk3399_cru dtd;
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@ -50,10 +52,9 @@ struct pll_div {
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.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
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.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
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#if defined(CONFIG_SPL_BUILD)
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
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static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
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#else
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#if !defined(CONFIG_SPL_BUILD)
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static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
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#endif
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@ -1293,7 +1294,6 @@ static struct clk_ops rk3399_clk_ops = {
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.disable = rk3399_clk_disable,
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};
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#ifdef CONFIG_SPL_BUILD
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static void rkclk_init(struct rockchip_cru *cru)
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{
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u32 aclk_div;
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@ -1371,20 +1371,30 @@ static void rkclk_init(struct rockchip_cru *cru)
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hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
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HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
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}
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#endif
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static int rk3399_clk_probe(struct udevice *dev)
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{
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#ifdef CONFIG_SPL_BUILD
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struct rk3399_clk_priv *priv = dev_get_priv(dev);
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bool init_clocks = false;
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct rk3399_clk_plat *plat = dev_get_platdata(dev);
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priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
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#endif
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rkclk_init(priv->cru);
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#if defined(CONFIG_SPL_BUILD)
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init_clocks = true;
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#elif CONFIG_IS_ENABLED(HANDOFF)
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if (!(gd->flags & GD_FLG_RELOC)) {
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if (!(gd->spl_handoff))
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init_clocks = true;
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}
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#endif
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if (init_clocks)
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rkclk_init(priv->cru);
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return 0;
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}
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@ -1,4 +1,4 @@
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// SPDX-License-Identifier: GPL-2.0+
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
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* Author: Eric Gao <eric.gao@rock-chips.com>
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@ -1,4 +1,4 @@
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// SPDX-License-Identifier: GPL-2.0+
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
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* Copyright (c) 2015 Google, Inc
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@ -1,4 +1,4 @@
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// SPDX-License-Identifier: GPL-2.0+
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
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* Author: Eric Gao <eric.gao@rock-chips.com>
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@ -1,4 +1,4 @@
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// SPDX-License-Identifier: GPL-2.0+
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
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* Copyright (c) 2015 Google, Inc
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@ -1,4 +1,4 @@
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// SPDX-License-Identifier: GPL-2.0+
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2015 Google, Inc
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* Copyright 2014 Rockchip Inc.
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@ -1,4 +1,4 @@
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// SPDX-License-Identifier: GPL-2.0+
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
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* Author: Eric Gao <eric.gao@rock-chips.com>
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@ -1,4 +1,4 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
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* Author: Eric Gao <eric.gao@rock-chips.com>
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@ -1,4 +1,4 @@
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// SPDX-License-Identifier: GPL-2.0+
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2015 Google, Inc
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* Copyright 2014 Rockchip Inc.
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@ -1,4 +1,4 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
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*/
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