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https://github.com/AsahiLinux/u-boot
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usb:udc:samsung: Zero copy approach for data passed to Samsung's UDC driver
The Samsung's UDC driver is not anymore copying data from USB requests to aligned internal buffers. Now it works directly in data allocated in the upper layers like UMS, DFU, THOR. This change is possible since those gadgets now must take care to allocate buffers aligned to cache line (CONFIG_SYS_CACHELINE_SIZE). This can be achieved by using DEFINE_CACHE_ALIGN_BUFFER() or ALLOC_CACHE_ALIGN_BUFFER() macros. Those take care to allocate buffer aligned to cache line in both starting address and its size. Sometimes it is enough to just use memalign() with size being a multiplication of cache line size. Test condition - test HW + measurement: Trats - Exynos4210 rev.1 - test HW Trats2 - Exynos4412 rev.1 400 MiB compressed rootfs image download with `thor 0 mmc 0` Measurement: Transmission speed: 27.04 MiB/s Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
This commit is contained in:
Lukasz Majewski
Marek Vasut
parent
9c9822188c
commit
e0059eaef1
3 changed files with 43 additions and 44 deletions
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@ -843,7 +843,7 @@ static struct s3c_udc memory = {
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int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
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{
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struct s3c_udc *dev = &memory;
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int retval = 0, i;
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int retval = 0;
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debug("%s: %p\n", __func__, pdata);
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@ -864,16 +864,15 @@ int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
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the_controller = dev;
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for (i = 0; i < S3C_MAX_ENDPOINTS+1; i++) {
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dev->dma_buf[i] = memalign(CONFIG_SYS_CACHELINE_SIZE,
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DMA_BUFFER_SIZE);
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dev->dma_addr[i] = (dma_addr_t) dev->dma_buf[i];
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invalidate_dcache_range((unsigned long) dev->dma_buf[i],
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(unsigned long) (dev->dma_buf[i]
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+ DMA_BUFFER_SIZE));
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usb_ctrl = memalign(CONFIG_SYS_CACHELINE_SIZE,
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ROUND(sizeof(struct usb_ctrlrequest),
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CONFIG_SYS_CACHELINE_SIZE));
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if (!usb_ctrl) {
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error("No memory available for UDC!\n");
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return -ENOMEM;
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}
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usb_ctrl = dev->dma_buf[0];
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usb_ctrl_dma_addr = dev->dma_addr[0];
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usb_ctrl_dma_addr = (dma_addr_t) usb_ctrl;
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udc_reinit(dev);
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@ -110,8 +110,7 @@ static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req)
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ctrl = readl(®->out_endp[ep_num].doepctl);
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writel(the_controller->dma_addr[ep_index(ep)+1],
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®->out_endp[ep_num].doepdma);
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writel((unsigned int) ep->dma_buf, ®->out_endp[ep_num].doepdma);
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writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length),
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®->out_endp[ep_num].doeptsiz);
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writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl);
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@ -134,7 +133,6 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req)
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u32 *buf, ctrl = 0;
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u32 length, pktcnt;
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u32 ep_num = ep_index(ep);
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u32 *p = the_controller->dma_buf[ep_index(ep)+1];
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buf = req->req.buf + req->req.actual;
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length = req->req.length - req->req.actual;
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@ -144,10 +142,10 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req)
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ep->len = length;
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ep->dma_buf = buf;
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memcpy(p, ep->dma_buf, length);
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flush_dcache_range((unsigned long) p ,
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(unsigned long) p + DMA_BUFFER_SIZE);
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flush_dcache_range((unsigned long) ep->dma_buf,
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(unsigned long) ep->dma_buf +
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ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE));
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if (length == 0)
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pktcnt = 1;
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@ -160,8 +158,7 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req)
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while (readl(®->grstctl) & TX_FIFO_FLUSH)
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;
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writel(the_controller->dma_addr[ep_index(ep)+1],
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®->in_endp[ep_num].diepdma);
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writel((unsigned long) ep->dma_buf, ®->in_endp[ep_num].diepdma);
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writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length),
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®->in_endp[ep_num].dieptsiz);
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@ -194,7 +191,6 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num)
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struct s3c_ep *ep = &dev->ep[ep_num];
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struct s3c_request *req = NULL;
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u32 ep_tsr = 0, xfer_size = 0, is_short = 0;
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u32 *p = the_controller->dma_buf[ep_index(ep)+1];
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if (list_empty(&ep->queue)) {
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debug_cond(DEBUG_OUT_EP != 0,
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@ -214,10 +210,23 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num)
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xfer_size = ep->len - xfer_size;
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invalidate_dcache_range((unsigned long) p,
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(unsigned long) p + DMA_BUFFER_SIZE);
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memcpy(ep->dma_buf, p, ep->len);
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/*
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* NOTE:
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*
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* Please be careful with proper buffer allocation for USB request,
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* which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only
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* with starting address, but also its size shall be a cache line
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* multiplication.
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*
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* This will prevent from corruption of data allocated immediatelly
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* before or after the buffer.
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*
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* For armv7, the cache_v7.c provides proper code to emit "ERROR"
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* message to warn users.
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*/
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invalidate_dcache_range((unsigned long) ep->dma_buf,
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(unsigned long) ep->dma_buf +
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ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE));
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req->req.actual += min(xfer_size, req->req.length - req->req.actual);
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is_short = (xfer_size < ep->ep.maxpacket);
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@ -711,19 +720,14 @@ static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req)
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int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max)
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{
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u32 bytes;
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bytes = sizeof(struct usb_ctrlrequest);
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invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_index(ep)],
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(unsigned long) ep->dev->dma_buf[ep_index(ep)]
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+ DMA_BUFFER_SIZE);
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invalidate_dcache_range((unsigned long)cp, (unsigned long)cp +
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ROUND(max, CONFIG_SYS_CACHELINE_SIZE));
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debug_cond(DEBUG_EP0 != 0,
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"%s: bytes=%d, ep_index=%d %p\n", __func__,
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bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]);
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"%s: bytes=%d, ep_index=%d 0x%p\n", __func__,
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max, ep_index(ep), cp);
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return bytes;
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return max;
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}
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/**
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@ -855,14 +859,12 @@ static int s3c_ep0_write(struct s3c_udc *dev)
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return 1;
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}
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u16 g_status;
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int s3c_udc_get_status(struct s3c_udc *dev,
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struct usb_ctrlrequest *crq)
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{
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u8 ep_num = crq->wIndex & 0x7F;
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u16 g_status = 0;
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u32 ep_ctrl;
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u32 *p = the_controller->dma_buf[1];
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debug_cond(DEBUG_SETUP != 0,
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"%s: *** USB_REQ_GET_STATUS\n", __func__);
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@ -900,12 +902,13 @@ int s3c_udc_get_status(struct s3c_udc *dev,
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return 1;
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}
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memcpy(p, &g_status, sizeof(g_status));
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memcpy(usb_ctrl, &g_status, sizeof(g_status));
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flush_dcache_range((unsigned long) p,
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(unsigned long) p + DMA_BUFFER_SIZE);
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flush_dcache_range((unsigned long) usb_ctrl,
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(unsigned long) usb_ctrl +
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ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE));
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writel(the_controller->dma_addr[1], ®->in_endp[EP0_CON].diepdma);
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writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma);
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writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2),
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®->in_endp[EP0_CON].dieptsiz);
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@ -19,7 +19,7 @@
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/*-------------------------------------------------------------------------*/
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/* DMA bounce buffer size, 16K is enough even for mass storage */
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#define DMA_BUFFER_SIZE (4096*4)
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#define DMA_BUFFER_SIZE (16*SZ_1K)
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#define EP0_FIFO_SIZE 64
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#define EP_FIFO_SIZE 512
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@ -81,9 +81,6 @@ struct s3c_udc {
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struct s3c_plat_otg_data *pdata;
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void *dma_buf[S3C_MAX_ENDPOINTS+1];
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dma_addr_t dma_addr[S3C_MAX_ENDPOINTS+1];
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int ep0state;
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struct s3c_ep ep[S3C_MAX_ENDPOINTS];
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