Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-10 07:04:28 +00:00
Code Issues Projects Releases Packages Wiki Activity

board: ls1043ardb: fdt fixups for revision v7.0 boards

Browse source 
The LS1043ARDB rev v7.0 board replaces the AQR105 PHY on MAC9 with an
AQR113C PHY. The address of the PHY on the MDIO bus changes from 0x1 to
0x8. Enable CONFIG_OF_BOARD_FIXUP and update both u-boot and Linux device
trees to reflect this change.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
This commit is contained in:
Camelia Groza 2022-07-28 17:28:11 +03:00 committed by Peng Fan
parent 47465877a5
commit dfea459f20
10 changed files with 55 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

44
board/freescale/ls1043ardb/ls1043ardb.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
* Copyright 2021-2022 NXP
*/
#include <common.h>
@ -272,6 +272,39 @@ void fdt_del_qe(void *blob)
}
}
/* Update the address of the Aquantia PHY on the MDIO bus for boards revision
* v7.0 and up. Also rename the PHY node to align with the address change.
*/
void fdt_fixup_phy_addr(void *blob)
{
const char phy_path[] =
"/soc/fman@1a00000/mdio@fd000/ethernet-phy@1";
int ret, offset, new_addr = AQR113C_PHY_ADDR;
char new_name[] = "ethernet-phy@00";
if (CPLD_READ(pcba_ver) < 0x7)
return;
offset = fdt_path_offset(blob, phy_path);
if (offset < 0) {
printf("ethernet-phy@1 node not found in the dts\n");
return;
}
ret = fdt_setprop_u32(blob, offset, "reg", new_addr);
if (ret < 0) {
printf("Unable to set 'reg' for node ethernet-phy@1: %s\n",
fdt_strerror(ret));
return;
}
sprintf(new_name, "ethernet-phy@%x", new_addr);
ret = fdt_set_name(blob, offset, new_name);
if (ret < 0)
printf("Unable to rename node ethernet-phy@1: %s\n",
fdt_strerror(ret));
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
u64 base[CONFIG_NR_DRAM_BANKS];
@ -290,6 +323,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
fdt_fixup_phy_addr(blob);
#endif
fdt_fixup_icid(blob);
@ -313,6 +347,14 @@ int ft_board_setup(void *blob, struct bd_info *bd)
return 0;
}
#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
int board_fix_fdt(void *blob)
{
fdt_fixup_phy_addr(blob);
return 0;
}
#endif
u8 flash_read8(void *addr)
{
return __raw_readb(addr + 1);

1
configs/ls1043ardb_SECURE_BOOT_defconfig
View file

@ -12,6 +12,7 @@ CONFIG_SYS_I2C_MXC_I2C4=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
CONFIG_PCIE1=y

1
configs/ls1043ardb_defconfig
View file

@ -14,6 +14,7 @@ CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_FSL_LS_PPA=y
CONFIG_ENV_ADDR=0x60300000
CONFIG_OF_BOARD_FIXUP=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/ls1043ardb_nand_SECURE_BOOT_defconfig
View file

@ -14,6 +14,7 @@ CONFIG_FSL_LS_PPA=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
CONFIG_PCIE1=y

1
configs/ls1043ardb_nand_defconfig
View file

@ -19,6 +19,7 @@ CONFIG_FSL_LS_PPA=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
View file

@ -15,6 +15,7 @@ CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
CONFIG_PCIE1=y

1
configs/ls1043ardb_sdcard_defconfig
View file

@ -20,6 +20,7 @@ CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

1
configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
View file

@ -14,6 +14,7 @@ CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_NXP_ESBC=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
CONFIG_PCIE1=y

1
configs/ls1043ardb_tfa_defconfig
View file

@ -17,6 +17,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_ENV_ADDR=0x60500000
CONFIG_OF_BOARD_FIXUP=y
CONFIG_LAYERSCAPE_NS_ACCESS=y
CONFIG_PCIE1=y
CONFIG_PCIE2=y

5
include/configs/ls1043ardb.h
View file

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2015 Freescale Semiconductor
* Copyright 2022 NXP
*/
#ifndef __LS1043ARDB_H__
@ -206,7 +207,9 @@
#define QSGMII_PORT3_PHY_ADDR 0x6
#define QSGMII_PORT4_PHY_ADDR 0x7
#define FM1_10GEC1_PHY_ADDR 0x1
/* The AQR PHY model and MDIO address differ between board revisions */
#define FM1_10GEC1_PHY_ADDR 0x1 /* AQR105 on boards up to v6.0 */
#define AQR113C_PHY_ADDR 0x8 /* AQR113C on boards v7.0 and up */
#endif
#endif