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- mips: gardena-smart-gateway: adjust config to new production values

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- mips: malta: convert to PCI DM and ETH DM
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Merge tag 'mips-pull-2021-07-18' of https://source.denx.de/u-boot/custodians/u-boot-mips

- mips: gardena-smart-gateway: adjust config to new production values
- mips: malta: convert to PCI DM and ETH DM
This commit is contained in:
Tom Rini 2021-07-18 18:31:16 -04:00
commit df761ba425
8 changed files with 284 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
arch/mips/Kconfig
View file

@ -14,8 +14,11 @@ choice
config TARGET_MALTA
bool "Support malta"
select BOARD_EARLY_INIT_R
select DM
select DM_SERIAL
select DM_PCI
select DM_ETH
select DYNAMIC_IO_PORT_BASE
select MIPS_CM
select MIPS_INSERT_BOOT_CONFIG
@ -23,6 +26,7 @@ config TARGET_MALTA
select MIPS_L2_CACHE
select OF_CONTROL
select OF_ISA_BUS
select PCI_MAP_SYSTEM_MEMORY
select ROM_EXCEPTION_VECTORS
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1

28
arch/mips/dts/mti,malta.dts
View file

@ -29,4 +29,32 @@
u-boot,dm-pre-reloc;
};
};
pci0@1bd00000 {
compatible = "mips,pci-msc01";
device_type = "pci";
reg = <0x1bd00000 0x2000>;
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0x0>;
ranges = <0x01000000 0 0x00000000 0x00000000 0 0x800000 /* I/O */
0x02000000 0 0x10000000 0xb0000000 0 0x10000000 /* MEM */>;
status = "disabled";
};
pci0@1be00000 {
compatible = "marvell,pci-gt64120";
device_type = "pci";
reg = <0x1be00000 0x2000>;
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0x0>;
ranges = <0x01000000 0 0x00000000 0x00000000 0 0x20000 /* I/O */
0x02000000 0 0x10000000 0x10000000 0 0x8000000 /* MEM */>;
status = "okay";
};
};

80
board/imgtec/malta/malta.c
View file

@ -4,7 +4,8 @@
* Copyright (C) 2013 Imagination Technologies
*/
#include <common.h>
#include <config.h>
#include <fdt_support.h>
#include <ide.h>
#include <init.h>
#include <net.h>
@ -24,6 +25,9 @@
DECLARE_GLOBAL_DATA_PTR;
#define MALTA_GT_PATH "/pci0@1be00000"
#define MALTA_MSC_PATH "/pci0@1bd00000"
enum core_card {
CORE_UNKNOWN,
CORE_LV,
@ -120,10 +124,12 @@ int checkboard(void)
return 0;
}
#if !IS_ENABLED(CONFIG_DM_ETH)
int board_eth_init(struct bd_info *bis)
{
return pci_eth_init(bis);
}
#endif
void _machine_restart(void)
{
@ -167,6 +173,77 @@ int misc_init_r(void)
return 0;
}
#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
/*
* TODO: currently doesn't work because rw_fdt_blob points to a
* NOR flash address. This needs some changes in board_init_f.
*/
int board_fix_fdt(void *rw_fdt_blob)
{
int node = -1;
switch (malta_sys_con()) {
case SYSCON_GT64120:
node = fdt_path_offset(rw_fdt_blob, MALTA_GT_PATH);
break;
default:
case SYSCON_MSC01:
node = fdt_path_offset(rw_fdt_blob, MALTA_MSC_PATH);
break;
}
return fdt_status_okay(rw_fdt_blob, node);
}
#endif
#if IS_ENABLED(CONFIG_DM_PCI)
int board_early_init_r(void)
{
struct udevice *dev;
int ret;
pci_init();
ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
PCI_DEVICE_ID_INTEL_82371AB_0, 0, &dev);
if (ret)
panic("Failed to find PIIX4 PCI bridge\n");
/* setup PCI interrupt routing */
dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCA, 10);
dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCB, 10);
dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCC, 11);
dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCD, 11);
/* mux SERIRQ onto SERIRQ pin */
dm_pci_clrset_config32(dev, PCI_CFG_PIIX4_GENCFG, 0,
PCI_CFG_PIIX4_GENCFG_SERIRQ);
/* enable SERIRQ - Linux currently depends upon this */
dm_pci_clrset_config8(dev, PCI_CFG_PIIX4_SERIRQC, 0,
PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT);
ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
PCI_DEVICE_ID_INTEL_82371AB, 0, &dev);
if (ret)
panic("Failed to find PIIX4 IDE controller\n");
/* enable bus master & IO access */
dm_pci_clrset_config32(dev, PCI_COMMAND, 0,
PCI_COMMAND_MASTER | PCI_COMMAND_IO);
/* set latency */
dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
/* enable IDE/ATA */
dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_PRI,
PCI_CFG_PIIX4_IDETIM_IDE);
dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_SEC,
PCI_CFG_PIIX4_IDETIM_IDE);
return 0;
}
#else
void pci_init_board(void)
{
pci_dev_t bdf;
@ -231,3 +308,4 @@ void pci_init_board(void)
pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
PCI_CFG_PIIX4_IDETIM_IDE);
}
#endif

11
configs/gardena-smart-gateway-mt7688_defconfig
View file

@ -2,13 +2,14 @@ CONFIG_MIPS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x0
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xA0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="gardena-smart-gateway-mt7688"
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SYS_BOOTCOUNT_ADDR=0xb000006c
CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
CONFIG_SPL_SYS_MALLOC_F_LEN=0x80000
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_ENV_OFFSET_REDUND=0xB0000
@ -22,6 +23,8 @@ CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR="x"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="cp.b 83000000 84000000 10000 && dhcp uEnv.txt && env import -t ${fileaddr} ${filesize} && run do_u_boot_init; reset"
CONFIG_USE_PREBOOT=y
@ -34,6 +37,8 @@ CONFIG_CMD_LICENSE=y
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADS is not set
@ -45,14 +50,17 @@ CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_GETTIME=y
CONFIG_CMD_UUID=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
CONFIG_MTDIDS_DEFAULT="spi-nand0=spi0.1,nor0=spi0.0"
CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);spi0.1:-(nand)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
@ -73,6 +81,7 @@ CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_MTD_UBI_BEB_LIMIT=22
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MT7628_ETH=y
CONFIG_PHY=y
CONFIG_SPECIFY_CONSOLE_INDEX=y

13
drivers/pci/Kconfig
View file

@ -54,6 +54,19 @@ config PCI_REGION_MULTI_ENTRY
region type. This helps to add support for SoC's like OcteonTX/TX2
where every peripheral is on the PCI bus.
config PCI_MAP_SYSTEM_MEMORY
bool "Map local system memory from a virtual base address"
depends on PCI || DM_PCI
depends on MIPS
default n
help
Say Y if base address of system memory is being used as a virtual address
instead of a physical address (e.g. on MIPS). The PCI core will then remap
the virtual memory base address to a physical address when adding the PCI
region of type PCI_REGION_SYS_MEMORY.
This should only be required on MIPS where CONFIG_SYS_SDRAM_BASE is still
being used as virtual address.
config PCI_SRIOV
bool "Enable Single Root I/O Virtualization support for PCI"
depends on PCI || DM_PCI

9
drivers/pci/pci-uclass.c
View file

@ -1034,10 +1034,13 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node,
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
phys_addr_t start = bd->bi_dram[i].start;
if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY))
start = virt_to_phys((void *)(uintptr_t)bd->bi_dram[i].start);
pci_set_region(hose->regions + hose->region_count++,
bd->bi_dram[i].start,
bd->bi_dram[i].start,
bd->bi_dram[i].size,
start, start, bd->bi_dram[i].size,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
}
}

74
drivers/pci/pci_gt64120.c
View file

@ -8,7 +8,7 @@
* Maciej W. Rozycki <macro@mips.com>
*/
#include <common.h>
#include <dm.h>
#include <gt64120.h>
#include <init.h>
#include <log.h>
@ -114,6 +114,7 @@ static int gt_config_access(struct gt64120_pci_controller *gt,
return 0;
}
#if !IS_ENABLED(CONFIG_DM_PCI)
static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
int where, u32 *value)
{
@ -175,3 +176,74 @@ void gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys,
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
#else
static int gt64120_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
uint where, ulong *val,
enum pci_size_t size)
{
struct gt64120_pci_controller *gt = dev_get_priv(dev);
u32 data = 0;
if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, &data)) {
*val = pci_get_ff(size);
return 0;
}
*val = pci_conv_32_to_size(data, where, size);
return 0;
}
static int gt64120_pci_write_config(struct udevice *dev, pci_dev_t bdf,
uint where, ulong val,
enum pci_size_t size)
{
struct gt64120_pci_controller *gt = dev_get_priv(dev);
u32 data = 0;
if (size == PCI_SIZE_32) {
data = val;
} else {
u32 old;
if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, &old))
return 0;
data = pci_conv_size_to_32(old, val, where, size);
}
gt_config_access(gt, PCI_ACCESS_WRITE, bdf, where, &data);
return 0;
}
static int gt64120_pci_probe(struct udevice *dev)
{
struct gt64120_pci_controller *gt = dev_get_priv(dev);
gt->regs = dev_remap_addr(dev);
if (!gt->regs)
return -EINVAL;
return 0;
}
static const struct dm_pci_ops gt64120_pci_ops = {
.read_config = gt64120_pci_read_config,
.write_config = gt64120_pci_write_config,
};
static const struct udevice_id gt64120_pci_ids[] = {
{ .compatible = "marvell,pci-gt64120" },
{ }
};
U_BOOT_DRIVER(gt64120_pci) = {
.name = "gt64120_pci",
.id = UCLASS_PCI,
.of_match = gt64120_pci_ids,
.ops = &gt64120_pci_ops,
.probe = gt64120_pci_probe,
.priv_auto = sizeof(struct gt64120_pci_controller),
};
#endif

72
drivers/pci/pci_msc01.c
View file

@ -4,7 +4,7 @@
* Author: Paul Burton <paul.burton@mips.com>
*/
#include <common.h>
#include <dm.h>
#include <init.h>
#include <msc01.h>
#include <pci.h>
@ -62,6 +62,7 @@ static int msc01_config_access(struct msc01_pci_controller *msc01,
return 0;
}
#if !IS_ENABLED(CONFIG_DM_PCI)
static int msc01_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
int where, u32 *value)
{
@ -123,3 +124,72 @@ void msc01_pci_init(void *base, unsigned long sys_bus, unsigned long sys_phys,
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
#else
static int msc01_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
uint where, ulong *val, enum pci_size_t size)
{
struct msc01_pci_controller *msc01 = dev_get_priv(dev);
u32 data = 0;
if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where, &data)) {
*val = pci_get_ff(size);
return 0;
}
*val = pci_conv_32_to_size(data, where, size);
return 0;
}
static int msc01_pci_write_config(struct udevice *dev, pci_dev_t bdf,
uint where, ulong val, enum pci_size_t size)
{
struct msc01_pci_controller *msc01 = dev_get_priv(dev);
u32 data = 0;
if (size == PCI_SIZE_32) {
data = val;
} else {
u32 old;
if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where, &old))
return 0;
data = pci_conv_size_to_32(old, val, where, size);
}
msc01_config_access(msc01, PCI_ACCESS_WRITE, bdf, where, &data);
return 0;
}
static int msc01_pci_probe(struct udevice *dev)
{
struct msc01_pci_controller *msc01 = dev_get_priv(dev);
msc01->base = dev_remap_addr(dev);
if (!msc01->base)
return -EINVAL;
return 0;
}
static const struct dm_pci_ops msc01_pci_ops = {
.read_config = msc01_pci_read_config,
.write_config = msc01_pci_write_config,
};
static const struct udevice_id msc01_pci_ids[] = {
{ .compatible = "mips,pci-msc01" },
{ }
};
U_BOOT_DRIVER(msc01_pci) = {
.name = "msc01_pci",
.id = UCLASS_PCI,
.of_match = msc01_pci_ids,
.ops = &msc01_pci_ops,
.probe = msc01_pci_probe,
.priv_auto = sizeof(struct msc01_pci_controller),
};
#endif