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https://github.com/AsahiLinux/u-boot
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ppc4xx: Update 440SP/440SPe DDR SPD setup code to support 440SP
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
fdd1d6dcc9
commit
df29449747
2 changed files with 63 additions and 26 deletions
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@ -188,6 +188,7 @@ static void program_initplr(unsigned long *dimm_populated,
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ddr_cas_id_t selected_cas,
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int write_recovery);
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static unsigned long is_ecc_enabled(void);
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#ifdef CONFIG_DDR_ECC
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static void program_ecc(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks,
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@ -195,6 +196,7 @@ static void program_ecc(unsigned long *dimm_populated,
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static void program_ecc_addr(unsigned long start_address,
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unsigned long num_bytes,
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unsigned long tlb_word2_i_value);
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#endif
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static void program_DQS_calibration(unsigned long *dimm_populated,
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unsigned char *iic0_dimm_addr,
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unsigned long num_dimm_banks);
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@ -255,15 +257,6 @@ static void mtdcr_any(u32 dcr, u32 val)
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}
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}
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static void wait_ddr_idle(void)
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{
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u32 val;
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do {
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mfsdram(SDRAM_MCSTAT, val);
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} while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
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}
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static unsigned char spd_read(uchar chip, uint addr)
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{
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unsigned char data[2];
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@ -491,7 +484,7 @@ long int initdram(int board_type)
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(val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
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SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
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(SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
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| SDRAM_MEMODE_RTT_75OHM | SDRAM_MEMODE_DQS_ENABLE));
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| SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
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/*------------------------------------------------------------------
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* Program Initialization preload registers.
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@ -537,10 +530,12 @@ long int initdram(int board_type)
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*-----------------------------------------------------------------*/
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program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
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#ifdef CONFIG_DDR_ECC
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/*------------------------------------------------------------------
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* If ecc is enabled, initialize the parity bits.
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*-----------------------------------------------------------------*/
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program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, MY_TLB_WORD2_I_ENABLE);
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#endif
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#ifdef DEBUG
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ppc440sp_sdram_register_dump();
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@ -702,7 +697,7 @@ static void check_frequency(unsigned long *dimm_populated,
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*-----------------------------------------------------------------*/
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get_sys_info(&board_cfg);
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mfsdr(sdr_ddr0, sdr_ddrpll);
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mfsdr(SDR0_DDR0, sdr_ddrpll);
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sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
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/*
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@ -877,7 +872,11 @@ static void program_copt1(unsigned long *dimm_populated,
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unsigned long ddrtype;
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unsigned long val;
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#ifdef CONFIG_DDR_ECC
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ecc_enabled = TRUE;
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#else
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ecc_enabled = FALSE;
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#endif
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dimm_32bit = FALSE;
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dimm_64bit = FALSE;
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buf0 = FALSE;
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@ -1314,7 +1313,7 @@ static void program_mode(unsigned long *dimm_populated,
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*-----------------------------------------------------------------*/
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get_sys_info(&board_cfg);
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mfsdr(sdr_ddr0, sdr_ddrpll);
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mfsdr(SDR0_DDR0, sdr_ddrpll);
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sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
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/*------------------------------------------------------------------
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@ -1463,11 +1462,12 @@ static void program_mode(unsigned long *dimm_populated,
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mfsdram(SDRAM_MMODE, mmode);
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mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
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cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100);
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cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100);
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cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100);
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cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100);
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cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100);
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/* add 10 here because of rounding problems */
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cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
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cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
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cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
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cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
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cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
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if (sdram_ddr1 == TRUE) { /* DDR1 */
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if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
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@ -1498,7 +1498,11 @@ static void program_mode(unsigned long *dimm_populated,
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} else {
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printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
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printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
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printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
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printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
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printf("cas3=%d cas4=%d cas5=%d\n",
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cas_3_0_available, cas_4_0_available, cas_5_0_available);
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printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
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sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
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hang();
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}
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}
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@ -1575,7 +1579,7 @@ static void program_rtr(unsigned long *dimm_populated,
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/*------------------------------------------------------------------
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* Set the SDRAM Refresh Timing Register, SDRAM_RTR
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*-----------------------------------------------------------------*/
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mfsdr(sdr_ddr0, sdr_ddrpll);
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mfsdr(SDR0_DDR0, sdr_ddrpll);
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sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
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max_refresh_rate = 0;
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@ -1661,7 +1665,7 @@ static void program_tr(unsigned long *dimm_populated,
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*-----------------------------------------------------------------*/
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get_sys_info(&board_cfg);
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mfsdr(sdr_ddr0, sdr_ddrpll);
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mfsdr(SDR0_DDR0, sdr_ddrpll);
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sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
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/*------------------------------------------------------------------
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@ -2069,7 +2073,7 @@ static void program_memory_queue(unsigned long *dimm_populated,
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* Set the sizes
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*-----------------------------------------------------------------*/
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baseadd_size = 0;
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rank_size_bytes = 1024 * 1024 * rank_size_id;
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rank_size_bytes = 4 * 1024 * 1024 * rank_size_id;
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switch (rank_size_id) {
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case 0x02:
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baseadd_size |= SDRAM_RXBAS_SDSZ_8;
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@ -2106,8 +2110,8 @@ static void program_memory_queue(unsigned long *dimm_populated,
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for (i = 0; i < num_ranks; i++) {
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mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
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(rank_base_addr & SDRAM_RXBAS_SDBA_MASK) |
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baseadd_size);
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(SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
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baseadd_size));
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rank_base_addr += rank_size_bytes;
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}
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}
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@ -2130,9 +2134,10 @@ static unsigned long is_ecc_enabled(void)
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ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
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}
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return(ecc);
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return ecc;
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}
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#ifdef CONFIG_DDR_ECC
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/*-----------------------------------------------------------------------------+
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* program_ecc.
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*-----------------------------------------------------------------------------*/
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@ -2208,6 +2213,15 @@ static void check_ecc(void)
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}
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#endif
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static void wait_ddr_idle(void)
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{
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u32 val;
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do {
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mfsdram(SDRAM_MCSTAT, val);
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} while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
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}
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/*-----------------------------------------------------------------------------+
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* program_ecc_addr.
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*-----------------------------------------------------------------------------*/
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@ -2276,6 +2290,7 @@ static void program_ecc_addr(unsigned long start_address,
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#endif
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}
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}
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#endif
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/*-----------------------------------------------------------------------------+
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* program_DQS_calibration.
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@ -2531,7 +2546,6 @@ static void DQS_calibration_process(void)
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}
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} /* for rffd */
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/*------------------------------------------------------------------
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* Set the average RFFD value
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*-----------------------------------------------------------------*/
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@ -417,7 +417,9 @@
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#define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */
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#define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */
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#define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */
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#endif /* CONFIG_440SPE */
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#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
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/*----------------------------------------------------------------------------+
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| SDRAM Controller
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+----------------------------------------------------------------------------*/
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@ -453,9 +455,16 @@
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/*-----------------------------------------------------------------------------+
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| Memory Bank 0-7 configuration
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+-----------------------------------------------------------------------------*/
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#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
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#if defined(CONFIG_440SPE)
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#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
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#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2)
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#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2)
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#endif /* CONFIG_440SPE */
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#if defined(CONFIG_440SP)
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#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
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#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFF800000))
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#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFF800000))
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#endif /* CONFIG_440SP */
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#define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */
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#define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<6)
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#define SDRAM_RXBAS_SDSZ_DECODE(n) ((((unsigned long)(n))>>6)&0x3FF)
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@ -2167,6 +2176,20 @@
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/*-----------------------------------------------------------------------------+
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| SDR0 Bit Settings
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+-----------------------------------------------------------------------------*/
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#if defined(CONFIG_440SP)
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#define SDR0_SRST 0x0200
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#define SDR0_DDR0 0x00E1
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#define SDR0_DDR0_DPLLRST 0x80000000
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#define SDR0_DDR0_DDRM_MASK 0x60000000
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#define SDR0_DDR0_DDRM_DDR1 0x20000000
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#define SDR0_DDR0_DDRM_DDR2 0x40000000
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#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
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#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
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#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
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#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
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#endif
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#if defined(CONFIG_440SPE)
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#define SDR0_CP440 0x0180
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#define SDR0_CP440_ERPN_MASK 0x30000000
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