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arm: Replace v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL) with asm code
Lets be consistent and also replace v7_maint_dcache_all() with asm code for the invalidate case. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Hans de Goede
Tom Rini
parent
c09d29057a
commit
df120142f3
2 changed files with 74 additions and 96 deletions
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@ -10,15 +10,14 @@
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#include <asm/armv7.h>
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#include <asm/utils.h>
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#define ARMV7_DCACHE_INVAL_ALL 1
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#define ARMV7_DCACHE_CLEAN_INVAL_ALL 2
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#define ARMV7_DCACHE_INVAL_RANGE 3
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#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4
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#define ARMV7_DCACHE_INVAL_RANGE 1
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#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2
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#ifndef CONFIG_SYS_DCACHE_OFF
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/* Asm functions from cache_v7_asm.S */
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void v7_flush_dcache_all(void);
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void v7_invalidate_dcache_all(void);
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static int check_cache_range(unsigned long start, unsigned long stop)
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{
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@ -37,18 +36,6 @@ static int check_cache_range(unsigned long start, unsigned long stop)
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return ok;
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}
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/*
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* Write the level and type you want to Cache Size Selection Register(CSSELR)
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* to get size details from Current Cache Size ID Register(CCSIDR)
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*/
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static void set_csselr(u32 level, u32 type)
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{
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u32 csselr = level << 1 | type;
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/* Write to Cache Size Selection Register(CSSELR) */
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asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
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}
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static u32 get_ccsidr(void)
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{
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u32 ccsidr;
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@ -58,85 +45,6 @@ static u32 get_ccsidr(void)
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return ccsidr;
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}
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static u32 get_clidr(void)
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{
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u32 clidr;
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/* Read current CP15 Cache Level ID Register */
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asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr));
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return clidr;
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}
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static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
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u32 num_ways, u32 way_shift,
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u32 log2_line_len)
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{
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int way, set;
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u32 setway;
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/*
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* For optimal assembly code:
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* a. count down
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* b. have bigger loop inside
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*/
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for (way = num_ways - 1; way >= 0 ; way--) {
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for (set = num_sets - 1; set >= 0; set--) {
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setway = (level << 1) | (set << log2_line_len) |
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(way << way_shift);
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/* Invalidate data/unified cache line by set/way */
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asm volatile (" mcr p15, 0, %0, c7, c6, 2"
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: : "r" (setway));
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}
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}
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/* DSB to make sure the operation is complete */
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DSB;
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}
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static void v7_maint_dcache_level_setway(u32 level, u32 operation)
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{
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u32 ccsidr;
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u32 num_sets, num_ways, log2_line_len, log2_num_ways;
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u32 way_shift;
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set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED);
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ccsidr = get_ccsidr();
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log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
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CCSIDR_LINE_SIZE_OFFSET) + 2;
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/* Converting from words to bytes */
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log2_line_len += 2;
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num_ways = ((ccsidr & CCSIDR_ASSOCIATIVITY_MASK) >>
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CCSIDR_ASSOCIATIVITY_OFFSET) + 1;
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num_sets = ((ccsidr & CCSIDR_NUM_SETS_MASK) >>
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CCSIDR_NUM_SETS_OFFSET) + 1;
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/*
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* According to ARMv7 ARM number of sets and number of ways need
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* not be a power of 2
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*/
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log2_num_ways = log_2_n_round_up(num_ways);
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way_shift = (32 - log2_num_ways);
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v7_inval_dcache_level_setway(level, num_sets, num_ways,
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way_shift, log2_line_len);
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}
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static void v7_maint_dcache_all(u32 operation)
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{
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u32 level, cache_type, level_start_bit = 0;
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u32 clidr = get_clidr();
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for (level = 0; level < 7; level++) {
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cache_type = (clidr >> level_start_bit) & 0x7;
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if ((cache_type == ARMV7_CLIDR_CTYPE_DATA_ONLY) ||
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(cache_type == ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA) ||
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(cache_type == ARMV7_CLIDR_CTYPE_UNIFIED))
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v7_maint_dcache_level_setway(level, operation);
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level_start_bit += 3;
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}
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}
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static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len)
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{
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u32 mva;
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@ -223,7 +131,7 @@ static void v7_inval_tlb(void)
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void invalidate_dcache_all(void)
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{
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v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
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v7_invalidate_dcache_all();
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v7_outer_cache_inval_all();
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}
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@ -82,3 +82,73 @@ ENTRY(v7_flush_dcache_all)
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THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
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bx lr
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ENDPROC(v7_flush_dcache_all)
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/*
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* v7_invalidate_dcache_all()
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*
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* Invalidate the whole D-cache.
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*
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* Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
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*
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* Note: copied from __v7_flush_dcache_all above with
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* mcr p15, 0, r11, c7, c14, 2
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* Replaced with:
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* mcr p15, 0, r11, c7, c6, 2
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*/
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ENTRY(__v7_invalidate_dcache_all)
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dmb @ ensure ordering with previous memory accesses
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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mov r3, r0, lsr #23 @ move LoC into position
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ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
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beq inval_finished @ if loc is 0, then no need to clean
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mov r10, #0 @ start clean at cache level 0
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inval_levels:
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add r2, r10, r10, lsr #1 @ work out 3x current cache level
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mov r1, r0, lsr r2 @ extract cache type bits from clidr
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt inval_skip @ skip if no cache, or just i-cache
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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isb @ isb to sych the new cssr&csidr
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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and r2, r1, #7 @ extract the length of the cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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movw r4, #0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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clz r5, r4 @ find bit position of way size increment
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movw r7, #0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the index size
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inval_loop1:
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mov r9, r7 @ create working copy of max index
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inval_loop2:
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ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
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THUMB( lsl r6, r4, r5 )
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THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
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ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
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THUMB( lsl r6, r9, r2 )
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THUMB( orr r11, r11, r6 ) @ factor index number into r11
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mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
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subs r9, r9, #1 @ decrement the index
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bge inval_loop2
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subs r4, r4, #1 @ decrement the way
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bge inval_loop1
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inval_skip:
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add r10, r10, #2 @ increment cache number
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cmp r3, r10
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bgt inval_levels
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inval_finished:
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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dsb st
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isb
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bx lr
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ENDPROC(__v7_invalidate_dcache_all)
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ENTRY(v7_invalidate_dcache_all)
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ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
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THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
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bl __v7_invalidate_dcache_all
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ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
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THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
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bx lr
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ENDPROC(v7_invalidate_dcache_all)
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