Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-25 06:00:43 +00:00
Code Issues Projects Releases Packages Wiki Activity

aspeed: Refactor SCU to use consistent mask & shift

Browse source 
Refactor SCU header to use consistent Mask & Shift values.
Now, consistently, to read value from SCU register, mask needs
to be applied before shift.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
maxims@google.com 2017-04-17 12:00:33 -07:00 committed by Tom Rini
parent 3b95902d47
commit defb184904
3 changed files with 27 additions and 29 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
arch/arm/include/asm/arch-aspeed/scu_ast2500.h
View file

@ -8,8 +8,8 @@
#define SCU_UNLOCK_VALUE 0x1688a8a8
#define SCU_HWSTRAP_VGAMEM_MASK 3
#define SCU_HWSTRAP_VGAMEM_SHIFT 2
#define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT)
#define SCU_HWSTRAP_MAC1_RGMII (1 << 6)
#define SCU_HWSTRAP_MAC2_RGMII (1 << 7)
#define SCU_HWSTRAP_DDR4 (1 << 24)
@ -18,17 +18,17 @@
#define SCU_MPLL_DENUM_SHIFT 0
#define SCU_MPLL_DENUM_MASK 0x1f
#define SCU_MPLL_NUM_SHIFT 5
#define SCU_MPLL_NUM_MASK 0xff
#define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT)
#define SCU_MPLL_POST_SHIFT 13
#define SCU_MPLL_POST_MASK 0x3f
#define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT)
#define SCU_PCLK_DIV_SHIFT 23
#define SCU_PCLK_DIV_MASK 7
#define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT)
#define SCU_HPLL_DENUM_SHIFT 0
#define SCU_HPLL_DENUM_MASK 0x1f
#define SCU_HPLL_NUM_SHIFT 5
#define SCU_HPLL_NUM_MASK 0xff
#define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT)
#define SCU_HPLL_POST_SHIFT 13
#define SCU_HPLL_POST_MASK 0x3f
#define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT)
#define SCU_MACCLK_SHIFT 16
#define SCU_MACCLK_MASK (7 << SCU_MACCLK_SHIFT)

5
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
View file

@ -183,9 +183,8 @@ static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info *info)
static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info)
{
size_t vga_mem_size_base = 8 * 1024 * 1024;
u32 vga_hwconf = (readl(&info->scu->hwstrap)
>> SCU_HWSTRAP_VGAMEM_SHIFT)
& SCU_HWSTRAP_VGAMEM_MASK;
u32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK)
>> SCU_HWSTRAP_VGAMEM_SHIFT;
return vga_mem_size_base << vga_hwconf;
}

39
drivers/clk/aspeed/clk_ast2500.c
View file

@ -52,11 +52,11 @@ struct ast2500_div_config {
*/
static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
{
const ulong num = (mpll_reg >> SCU_MPLL_NUM_SHIFT) & SCU_MPLL_NUM_MASK;
const ulong denum = (mpll_reg >> SCU_MPLL_DENUM_SHIFT)
& SCU_MPLL_DENUM_MASK;
const ulong post_div = (mpll_reg >> SCU_MPLL_POST_SHIFT)
& SCU_MPLL_POST_MASK;
const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT;
const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK)
>> SCU_MPLL_DENUM_SHIFT;
const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK)
>> SCU_MPLL_POST_SHIFT;
return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
}
@ -67,11 +67,11 @@ static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
*/
static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
{
const ulong num = (hpll_reg >> SCU_HPLL_NUM_SHIFT) & SCU_HPLL_NUM_MASK;
const ulong denum = (hpll_reg >> SCU_HPLL_DENUM_SHIFT)
& SCU_HPLL_DENUM_MASK;
const ulong post_div = (hpll_reg >> SCU_HPLL_POST_SHIFT)
& SCU_HPLL_POST_MASK;
const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT;
const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK)
>> SCU_HPLL_DENUM_SHIFT;
const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK)
>> SCU_HPLL_POST_SHIFT;
return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
}
@ -136,11 +136,11 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
case BCLK_PCLK:
{
ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
>> SCU_PCLK_DIV_SHIFT) &
SCU_PCLK_DIV_MASK);
& SCU_PCLK_DIV_MASK)
>> SCU_PCLK_DIV_SHIFT);
rate = ast2500_get_hpll_rate(clkin,
readl(&priv->scu->
h_pll_param));
readl(&priv->
scu->h_pll_param));
rate = rate / apb_div;
}
break;
@ -223,17 +223,16 @@ static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate)
ulong clkin = ast2500_get_clkin(scu);
u32 mpll_reg;
struct ast2500_div_config div_cfg = {
.num = SCU_MPLL_NUM_MASK,
.denum = SCU_MPLL_DENUM_MASK,
.post_div = SCU_MPLL_POST_MASK
.num = (SCU_MPLL_NUM_MASK >> SCU_MPLL_NUM_SHIFT),
.denum = (SCU_MPLL_DENUM_MASK >> SCU_MPLL_DENUM_SHIFT),
.post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT),
};
ast2500_calc_clock_config(clkin, rate, &div_cfg);
mpll_reg = readl(&scu->m_pll_param);
mpll_reg &= ~((SCU_MPLL_POST_MASK << SCU_MPLL_POST_SHIFT)
| (SCU_MPLL_NUM_MASK << SCU_MPLL_NUM_SHIFT)
| (SCU_MPLL_DENUM_MASK << SCU_MPLL_DENUM_SHIFT));
mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK
| SCU_MPLL_DENUM_MASK);
mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT)
| (div_cfg.num << SCU_MPLL_NUM_SHIFT)
| (div_cfg.denum << SCU_MPLL_DENUM_SHIFT);