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spi: fsl_qspi: Support to use full AHB space on i.MX
i.MX platforms provide large AHB mapped space for QSPI, each controller has 256MB. However, current driver only maps small size (AHB buffer size) of AHB space, this implementation causes i.MX failed to boot M4 with QSPI XIP image. Add config CONFIG_FSL_QSPI_AHB_FULL_MAP (default enabled for i.MX) to address above problem. When the config is set: 1. Full AHB space is divided to each CS. 2. A dedicated LUT entry is used for AHB read only. 3. The MODE instruction in LUT is replaced to standard ADDR instruction 4. The address in spi_mem_op is used to SFAR and AHB read Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: Kuldeep Singh <kuldeep.singh@nxp.com>
This commit is contained in:
Ye Li
Stefano Babic
parent
93d6c8f7b7
commit
def88bce09
2 changed files with 97 additions and 23 deletions
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@ -155,6 +155,14 @@ config FSL_QSPI
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used to access the SPI NOR flash on platforms embedding this
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Freescale IP core.
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config FSL_QSPI_AHB_FULL_MAP
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bool "Use full AHB memory map space"
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depends on FSL_QSPI
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default y if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_IMX8M
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help
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Enable the Freescale QSPI driver to use full AHB memory map space for
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flash access.
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config ICH_SPI
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bool "Intel ICH SPI driver"
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help
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@ -46,6 +46,7 @@ DECLARE_GLOBAL_DATA_PTR;
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* read operation, so let's use the last entry (15).
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*/
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#define SEQID_LUT 15
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#define SEQID_LUT_AHB 14
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/* Registers used by the driver */
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#define QUADSPI_MCR 0x00
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@ -122,6 +123,10 @@ DECLARE_GLOBAL_DATA_PTR;
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#define QUADSPI_LUT_REG(idx) \
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(QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4)
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#define QUADSPI_AHB_LUT_OFFSET (SEQID_LUT_AHB * 4 * 4)
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#define QUADSPI_AHB_LUT_REG(idx) \
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(QUADSPI_LUT_BASE + QUADSPI_AHB_LUT_OFFSET + (idx) * 4)
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/* Instruction set for the LUT register */
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#define LUT_STOP 0
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#define LUT_CMD 1
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@ -189,6 +194,11 @@ DECLARE_GLOBAL_DATA_PTR;
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*/
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#define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
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/*
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* Controller only has Two CS on flash A, no flash B port
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*/
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#define QUADSPI_QUIRK_SINGLE_BUS BIT(6)
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struct fsl_qspi_devtype_data {
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unsigned int rxfifo;
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unsigned int txfifo;
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@ -236,7 +246,7 @@ static const struct fsl_qspi_devtype_data imx7ulp_data = {
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.txfifo = SZ_64,
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.ahb_buf_size = SZ_128,
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.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
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QUADSPI_QUIRK_USE_TDH_SETTING,
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QUADSPI_QUIRK_USE_TDH_SETTING | QUADSPI_QUIRK_SINGLE_BUS,
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.little_endian = true,
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};
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@ -269,6 +279,7 @@ struct fsl_qspi {
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void __iomem *iobase;
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void __iomem *ahb_addr;
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u32 memmap_phy;
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u32 memmap_size;
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const struct fsl_qspi_devtype_data *devtype_data;
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int selected;
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};
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@ -303,6 +314,11 @@ static inline int needs_tdh_setting(struct fsl_qspi *q)
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return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
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}
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static inline int needs_single_bus(struct fsl_qspi *q)
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{
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return q->devtype_data->quirks & QUADSPI_QUIRK_SINGLE_BUS;
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}
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/*
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* An IC bug makes it necessary to rearrange the 32-bit data.
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* Later chips, such as IMX6SLX, have fixed this bug.
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@ -405,18 +421,27 @@ static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
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lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
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op->cmd.opcode);
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/*
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* For some unknown reason, using LUT_ADDR doesn't work in some
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* cases (at least with only one byte long addresses), so
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* let's use LUT_MODE to write the address bytes one by one
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*/
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for (i = 0; i < op->addr.nbytes; i++) {
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u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
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if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
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if (op->addr.nbytes) {
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lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
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LUT_PAD(op->addr.buswidth),
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(op->addr.nbytes == 4) ? 0x20 : 0x18);
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lutidx++;
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}
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} else {
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/*
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* For some unknown reason, using LUT_ADDR doesn't work in some
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* cases (at least with only one byte long addresses), so
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* let's use LUT_MODE to write the address bytes one by one
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*/
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for (i = 0; i < op->addr.nbytes; i++) {
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u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
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lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
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LUT_PAD(op->addr.buswidth),
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addrbyte);
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lutidx++;
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lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE,
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LUT_PAD(op->addr.buswidth),
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addrbyte);
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lutidx++;
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}
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}
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if (op->dummy.nbytes) {
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@ -449,6 +474,14 @@ static void fsl_qspi_prepare_lut(struct fsl_qspi *q,
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for (i = 0; i < ARRAY_SIZE(lutval); i++)
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qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
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if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
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if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN &&
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op->addr.nbytes) {
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for (i = 0; i < ARRAY_SIZE(lutval); i++)
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qspi_writel(q, lutval[i], base + QUADSPI_AHB_LUT_REG(i));
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}
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}
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/* lock LUT */
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qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
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qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
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@ -491,10 +524,29 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave)
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fsl_qspi_invalidate(q);
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}
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static u32 fsl_qspi_memsize_per_cs(struct fsl_qspi *q)
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{
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if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
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if (needs_single_bus(q))
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return q->memmap_size / 2;
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else
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return q->memmap_size / 4;
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} else {
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return ALIGN(q->devtype_data->ahb_buf_size, 0x400);
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}
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}
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static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
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{
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void __iomem *ahb_read_addr = q->ahb_addr;
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if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
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if (op->addr.nbytes)
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ahb_read_addr += op->addr.val;
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}
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memcpy_fromio(op->data.buf.in,
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q->ahb_addr + q->selected * ALIGN(q->devtype_data->ahb_buf_size, 0x400),
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ahb_read_addr + q->selected * fsl_qspi_memsize_per_cs(q),
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op->data.nbytes);
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}
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@ -597,8 +649,13 @@ static int fsl_qspi_exec_op(struct spi_slave *slave,
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if (needs_amba_base_offset(q))
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addr_offset = q->memmap_phy;
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if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) {
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if (op->addr.nbytes)
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addr_offset += op->addr.val;
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}
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qspi_writel(q,
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q->selected * ALIGN(q->devtype_data->ahb_buf_size, 0x400) + addr_offset,
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q->selected * fsl_qspi_memsize_per_cs(q) + addr_offset,
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base + QUADSPI_SFAR);
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qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
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@ -655,7 +712,7 @@ static int fsl_qspi_adjust_op_size(struct spi_slave *slave,
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static int fsl_qspi_default_setup(struct fsl_qspi *q)
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{
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void __iomem *base = q->iobase;
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u32 reg, addr_offset = 0;
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u32 reg, addr_offset = 0, memsize_cs;
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/* Reset the module */
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qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
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@ -687,8 +744,13 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q)
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qspi_writel(q, 0, base + QUADSPI_BUF1IND);
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qspi_writel(q, 0, base + QUADSPI_BUF2IND);
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qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
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q->iobase + QUADSPI_BFGENCR);
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if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP))
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qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT_AHB),
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q->iobase + QUADSPI_BFGENCR);
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else
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qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),
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q->iobase + QUADSPI_BFGENCR);
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qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
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qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
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QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),
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@ -704,14 +766,17 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q)
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* We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD,
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* SFB2AD accordingly.
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*/
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qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) + addr_offset,
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memsize_cs = fsl_qspi_memsize_per_cs(q);
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qspi_writel(q, memsize_cs + addr_offset,
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base + QUADSPI_SFA1AD);
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qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) * 2 + addr_offset,
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qspi_writel(q, memsize_cs * 2 + addr_offset,
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base + QUADSPI_SFA2AD);
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qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) * 3 + addr_offset,
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base + QUADSPI_SFB1AD);
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qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) * 4 + addr_offset,
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base + QUADSPI_SFB2AD);
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if (!needs_single_bus(q)) {
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qspi_writel(q, memsize_cs * 3 + addr_offset,
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base + QUADSPI_SFB1AD);
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qspi_writel(q, memsize_cs * 4 + addr_offset,
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base + QUADSPI_SFB2AD);
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}
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q->selected = -1;
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@ -759,6 +824,7 @@ static int fsl_qspi_probe(struct udevice *bus)
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q->ahb_addr = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
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q->memmap_phy = res.start;
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q->memmap_size = res.end - res.start;
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dm_bus->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
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66000000);
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