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arm: armv7: omap3: Fix restore sequence in lowlevel_init

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The restore sequence in lowlevel_init was in the wrong order,
causing lr to lose its original value and be set equal to ip
instead. Also, its use of the stack clashes with that of
s_init, so move the s_init call after the restore and turn
it  into a tail-optimized branch.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Tested-by: Jeroen Hofstee <jeroen@myspectrum.nl>
This commit is contained in:
Albert ARIBAUD 2012-10-07 09:24:10 +00:00 committed by Tom Rini
parent 8cc64bafc0
commit dec96689ca
1 changed files with 4 additions and 5 deletions
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9
arch/arm/cpu/armv7/omap3/lowlevel_init.S
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@ -214,7 +214,7 @@ pll_div_val5:
ENTRY(lowlevel_init) ENTRY(lowlevel_init)
ldr sp, SRAM_STACK ldr sp, SRAM_STACK
str ip, [sp] /* stash old link register */ str ip, [sp] /* stash ip register */
mov ip, lr /* save link reg across call */ mov ip, lr /* save link reg across call */
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
/* /*
@ -224,12 +224,11 @@ ENTRY(lowlevel_init)
ldr r1, =SRAM_CLK_CODE ldr r1, =SRAM_CLK_CODE
bl cpy_clk_code bl cpy_clk_code
#endif /* NAND Boot */ #endif /* NAND Boot */
bl s_init /* go setup pll, mux, memory */
ldr ip, [sp] /* restore save ip */
mov lr, ip /* restore link reg */ mov lr, ip /* restore link reg */
ldr ip, [sp] /* restore save ip */
/* tail-call s_init to setup pll, mux, memory */
b s_init
/* back to arch calling code */
mov pc, lr
ENDPROC(lowlevel_init) ENDPROC(lowlevel_init)
/* the literal pools origin */ /* the literal pools origin */