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https://github.com/AsahiLinux/u-boot
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xtensa: add support for the xtensa processor architecture [1/2]
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Cadence. This is the first part of the basic architecture port with changes to common files. The 'arch/xtensa' directory, and boards and additional drivers will be in separate commits. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
parent
f225d39d30
commit
de5e5cea02
9 changed files with 179 additions and 6 deletions
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@ -454,6 +454,11 @@ S: Maintained
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T: git git://git.denx.de/u-boot-x86.git
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F: arch/x86/
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XTENSA
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M: Max Filippov <jcmvbkbc@gmail.com>
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S: Maintained
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F: arch/xtensa/
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THE REST
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M: Tom Rini <trini@konsulko.com>
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L: u-boot@lists.denx.de
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10
Makefile
10
Makefile
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@ -557,6 +557,14 @@ else
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include/config/auto.conf: ;
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endif # $(dot-config)
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#
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# Xtensa linker script cannot be preprocessed with -ansi because of
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# preprocessor operations on strings that don't make C identifiers.
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#
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ifeq ($(CONFIG_XTENSA),)
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LDPPFLAGS += -ansi
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endif
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ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
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KBUILD_CFLAGS += -Os
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else
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@ -1312,7 +1320,7 @@ $(timestamp_h): $(srctree)/Makefile FORCE
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# ---------------------------------------------------------------------------
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quiet_cmd_cpp_lds = LDS $@
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cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \
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cmd_cpp_lds = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) \
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-D__ASSEMBLY__ -x assembler-with-cpp -P -o $@ $<
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u-boot.lds: $(LDSCRIPT) prepare FORCE
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@ -524,6 +524,14 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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return 0;
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}
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#elif defined(CONFIG_XTENSA)
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int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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print_std_bdinfo(gd->bd);
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return 0;
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}
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#else
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#error "a case for this architecture does not exist!"
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#endif
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@ -54,6 +54,8 @@
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#include <asm/sections.h>
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#if defined(CONFIG_X86) || defined(CONFIG_ARC)
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#include <asm/init_helpers.h>
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#endif
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#if defined(CONFIG_X86) || defined(CONFIG_ARC) || defined(CONFIG_XTENSA)
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#include <asm/relocate.h>
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#endif
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#ifdef CONFIG_SANDBOX
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@ -271,7 +273,8 @@ static int setup_mon_len(void)
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gd->mon_len = (ulong)&__bss_end - (ulong)_start;
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#elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
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gd->mon_len = (ulong)&_end - (ulong)_init;
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#elif defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2)
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#elif defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2) || \
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defined(CONFIG_XTENSA)
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gd->mon_len = CONFIG_SYS_MONITOR_LEN;
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#elif defined(CONFIG_NDS32)
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gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
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@ -971,7 +974,7 @@ static init_fnc_t init_sequence_f[] = {
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* - board info struct
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*/
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setup_dest_addr,
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#if defined(CONFIG_BLACKFIN)
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#if defined(CONFIG_BLACKFIN) || defined(CONFIG_XTENSA)
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/* Blackfin u-boot monitor should be on top of the ram */
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reserve_uboot,
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#endif
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@ -1003,7 +1006,7 @@ static init_fnc_t init_sequence_f[] = {
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# endif
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#endif /* CONFIG_DM_VIDEO */
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reserve_trace,
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#if !defined(CONFIG_BLACKFIN)
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#if !defined(CONFIG_BLACKFIN) && !defined(CONFIG_XTENSA)
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reserve_uboot,
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#endif
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#ifndef CONFIG_SPL_BUILD
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@ -1036,6 +1039,9 @@ static init_fnc_t init_sequence_f[] = {
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clear_bss,
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do_elf_reloc_fixups,
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#endif
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#if defined(CONFIG_XTENSA)
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clear_bss,
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#endif
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#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
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jump_to_copy,
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#endif
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@ -93,6 +93,7 @@ static const table_entry_t uimage_arch[] = {
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{ IH_ARCH_ARM64, "arm64", "AArch64", },
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{ IH_ARCH_ARC, "arc", "ARC", },
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{ IH_ARCH_X86_64, "x86_64", "AMD x86_64", },
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{ IH_ARCH_XTENSA, "xtensa", "Xtensa", },
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{ -1, "", "", },
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};
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97
doc/README.xtensa
Normal file
97
doc/README.xtensa
Normal file
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@ -0,0 +1,97 @@
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U-Boot for the Xtensa Architecture
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==================================
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Xtensa Architecture and Diamond Cores
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-------------------------------------
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Xtensa is a configurable processor architecture from Tensilica, Inc.
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Diamond Cores are pre-configured instances available for license and
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SoC cores in the same manner as ARM, MIPS, etc.
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Xtensa licensees create their own Xtensa cores with selected features
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and custom instructions, registers and co-processors. The custom core
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is configured with Tensilica tools and built with Tensilica's Xtensa
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Processor Generator.
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There are an effectively infinite number of CPUs in the Xtensa
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architecture family. It is, however, not feasible to support individual
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Xtensa CPUs in U-Boot. Therefore, there is only a single 'xtensa' CPU
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in the cpu tree of U-Boot.
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In the same manner as the Linux port to Xtensa, U-Boot adapts to an
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individual Xtensa core configuration using a set of macros provided with
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the particular core. This is part of what is known as the hardware
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abstraction layer (HAL). For the purpose of U-Boot, the HAL consists only
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of a few header files. These provide CPP macros that customize sources,
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Makefiles, and the linker script.
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Adding support for an additional processor configuration
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--------------------------------------------------------
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The header files for one particular processor configuration are inside
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a variant-specific directory located in the arch/xtensa/include/asm
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directory. The name of that directory starts with 'arch-' followed by
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the name for the processor configuration, for example, arch-dc233c for
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the Diamond DC233 processor.
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core.h Definitions for the core itself.
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The following files are part of the overlay but not used by U-Boot.
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tie.h Co-processors and custom extensions defined
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in the Tensilica Instruction Extension (TIE)
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language.
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tie-asm.h Assembly macros to access custom-defined registers
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and states.
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Global Data Pointer, Exported Function Stubs, and the ABI
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---------------------------------------------------------
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To support standalone applications launched with the "go" command,
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U-Boot provides a jump table of entrypoints to exported functions
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(grep for EXPORT_FUNC). The implementation for Xtensa depends on
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which ABI (or function calling convention) is used.
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Windowed ABI presents unique difficulties with the approach based on
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keeping global data pointer in dedicated register. Because the register
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window rotates during a call, there is no register that is constantly
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available for the gd pointer. Therefore, on xtensa gd is a simple
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global variable. Another difficulty arises from the requirement to have
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an 'entry' at the beginning of a function, which rotates the register
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file and reserves a stack frame. This is an integral part of the
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windowed ABI implemented in hardware. It makes using a jump table to an
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arbitrary (separately compiled) function a bit tricky. Use of a simple
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wrapper is also very tedious due to the need to move all possible
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register arguments and adjust the stack to handle arguments that cannot
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be passed in registers. The most efficient approach is to have the jump
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table perform the 'entry' so as to pretend it's the start of the real
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function. This requires decoding the target function's 'entry'
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instruction to determine the stack frame size, and adjusting the stack
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pointer accordingly, then jumping into the target function just after
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the 'entry'. Decoding depends on the processor's endianness so uses the
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HAL. The implementation (12 instructions) is in examples/stubs.c.
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Access to Invalid Memory Addresses
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----------------------------------
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U-Boot does not check if memory addresses given as arguments to commands
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such as "md" are valid. There are two possible types of invalid
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addresses: an area of physical address space may not be mapped to RAM
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or peripherals, or in the presence of MMU an area of virtual address
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space may not be mapped to physical addresses.
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Accessing first type of invalid addresses may result in hardware lockup,
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reading of meaningless data, written data being ignored or an exception,
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depending on the CPU wiring to the system. Accessing second type of
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invalid addresses always ends with an exception.
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U-Boot for Xtensa provides a special memory exception handler that
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reports such access attempts and resets the board.
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------------------------------------------------------------------------------
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Chris Zankel
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Ross Morley
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@ -240,6 +240,53 @@ gd_t *global_data;
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" ld r10, [r10, %1]\n" \
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" j [r10]\n" \
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: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r10");
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#elif defined(CONFIG_XTENSA)
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/*
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* Global data ptr is in global_data, jump table ptr is in jt.
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* Windowed ABI: Jump just past 'entry' in target and adjust stack frame
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* (extract stack frame size from target 'entry' instruction).
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*/
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static void **jt;
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#if defined(__XTENSA_CALL0_ABI__)
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#define EXPORT_FUNC(f, a, x, ...) \
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asm volatile ( \
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" .extern jt\n" \
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" .globl " #x "\n" \
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" .align 4\n" \
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#x ":\n" \
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" l32i a8, %0, 0\n" \
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" l32i a8, a8, %1\n" \
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" jx a8\n" \
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: : "r"(jt), "i" (FO(x)) : "a8");
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#elif defined(__XTENSA_WINDOWED_ABI__)
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#if XCHAL_HAVE_BE
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# define SFT "8"
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#else
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# define SFT "12"
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#endif
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#define EXPORT_FUNC(f, a, x, ...) \
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asm volatile ( \
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" .extern jt\n" \
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" .globl " #x "\n" \
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" .align 4\n" \
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#x ":\n" \
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" entry sp, 16\n" \
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" l32i a8, %0, 0\n" \
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" l32i a8, a8, %1\n" \
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" l32i a9, a8, 0\n" \
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" extui a9, a9, " SFT ", 12\n" \
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" subx8 a9, a9, sp\n" \
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" movi a10, 16\n" \
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" sub a9, a10, a9\n" \
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" movsp sp, a9\n" \
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" addi a8, a8, 3\n" \
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" jx a8\n" \
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: : "r"(jt), "i" (FO(x)) : "a8", "a9", "a10");
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#else
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#error Unsupported Xtensa ABI
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#endif
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#else
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/*" addi $sp, $sp, -24\n" \
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" br $r16\n" \*/
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IH_ARCH_ARM64, /* ARM64 */
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IH_ARCH_ARC, /* Synopsys DesignWare ARC */
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IH_ARCH_X86_64, /* AMD x86_64, Intel and Via */
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IH_ARCH_XTENSA, /* Xtensa */
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IH_ARCH_COUNT,
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};
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#endif /* __MIPS__ */
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#if defined(__AVR32__) || defined(__SH__)
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#if defined(__AVR32__) || defined(__SH__) || defined(__XTENSA__)
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struct stat {
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unsigned long st_dev;
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unsigned long __unused5;
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};
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#endif /* __AVR32__ || __SH__ */
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#endif /* __AVR32__ || __SH__ || __XTENSA__ */
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#ifdef __cplusplus
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}
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