mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-03-17 15:27:00 +00:00
- mvebu: dts: Armada8k enable mdio (Sven) - a37xx: pci: Fix / enhance error handling (Pali) - mvebu: espressobin/turris_: Enable GPT partition support (Pali) - mvebu: sata_mv: Probe all ports (Tony) - a37xx: pci: Don't spam about PIO Response Status (Marek)
This commit is contained in:
commit
de5857d056
12 changed files with 76 additions and 24 deletions
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@ -175,6 +175,7 @@
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};
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&cp0_mdio {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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@ -295,6 +295,7 @@
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};
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&cp1_mdio {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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@ -270,6 +270,7 @@
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};
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&cp0_mdio {
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status = "okay";
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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@ -155,6 +155,7 @@
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};
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&cp0_mdio {
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status = "okay";
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ge_phy: ethernet-phy@0 {
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reg = <0>;
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};
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@ -163,7 +163,7 @@ void reset_phy(void)
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char *eth0_name = "ethernet-controller@72000";
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char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
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char *eth1_name = "ethernet-controller@76000";
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char *eth1_path = "/ocp@f1000000/ethernet-controller@72000/ethernet1-port@0";
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char *eth1_path = "/ocp@f1000000/ethernet-controller@76000/ethernet1-port@0";
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/* configure and initialize both PHY's */
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mv_phy_88e1116_init(eth0_name, eth0_path);
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@ -1,5 +1,5 @@
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SHEEVAPLUG BOARD
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M: Prafulla Wadaskar <prafulla@marvell.com>
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M: Tony Dinh <mibodhi@gmail.com>
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S: Maintained
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F: board/Marvell/sheevaplug/
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F: include/configs/sheevaplug.h
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@ -26,6 +26,7 @@ CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_BOARD_LATE_INIT=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_MTD=y
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@ -29,6 +29,7 @@ CONFIG_CMD_SHA1SUM=y
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CONFIG_CMD_CLK=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_MTD=y
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@ -40,6 +40,7 @@ CONFIG_SYS_ALT_MEMTEST=y
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CONFIG_CMD_SHA1SUM=y
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CONFIG_CMD_LZMADEC=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_MTD=y
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@ -1068,6 +1068,7 @@ static int sata_mv_probe(struct udevice *dev)
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int nr_ports;
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int ret;
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int i;
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int status = -ENODEV; /* If the probe fails to detected any SATA port */
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/* Get number of ports of this SATA controller */
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nr_ports = min(fdtdec_get_int(blob, node, "nr-ports", -1),
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@ -1078,7 +1079,7 @@ static int sata_mv_probe(struct udevice *dev)
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IF_TYPE_SATA, -1, 512, 0, &blk);
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if (ret) {
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debug("Can't create device\n");
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return ret;
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continue;
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}
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priv = dev_get_plat(blk);
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@ -1088,18 +1089,23 @@ static int sata_mv_probe(struct udevice *dev)
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ret = sata_mv_init_sata(blk, i);
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if (ret) {
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debug("%s: Failed to init bus\n", __func__);
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return ret;
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continue;
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}
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/* Scan SATA port */
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ret = sata_mv_scan_sata(blk, i);
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if (ret) {
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debug("%s: Failed to scan bus\n", __func__);
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return ret;
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continue;
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}
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/* If we got here, the current SATA port was probed
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* successfully, so set the probe status to successful.
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*/
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status = 0;
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}
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return 0;
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return status;
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}
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static int sata_mv_scan(struct udevice *dev)
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@ -234,19 +234,19 @@ static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
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*
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* Wait up to 1.5 seconds for PIO access to be accomplished.
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*
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* Return 1 (true) if PIO access is accomplished.
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* Return 0 (false) if PIO access is timed out.
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* Return positive - retry count if PIO access is accomplished.
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* Return negative - error if PIO access is timed out.
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*/
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static int pcie_advk_wait_pio(struct pcie_advk *pcie)
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{
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uint start, isr;
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uint count;
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for (count = 0; count < PIO_MAX_RETRIES; count++) {
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for (count = 1; count <= PIO_MAX_RETRIES; count++) {
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start = advk_readl(pcie, PIO_START);
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isr = advk_readl(pcie, PIO_ISR);
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if (!start && isr)
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return 1;
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return count;
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/*
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* Do not check the PIO state too frequently,
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* 100us delay is appropriate.
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@ -255,7 +255,7 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie)
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}
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dev_err(pcie->dev, "PIO read/write transfer time out\n");
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return 0;
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return -ETIMEDOUT;
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}
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/**
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@ -265,11 +265,13 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie)
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* @allow_crs: Only for read requests, if CRS response is allowed
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* @read_val: Pointer to the read result
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*
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* Return: 0 on success
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*/
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static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
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bool allow_crs,
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uint *read_val)
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{
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int ret;
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uint reg;
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unsigned int status;
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char *strcomp_status, *str_posted;
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@ -282,6 +284,7 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
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case PIO_COMPLETION_STATUS_OK:
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if (reg & PIO_ERR_STATUS) {
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strcomp_status = "COMP_ERR";
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ret = -EFAULT;
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break;
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}
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/* Get the read result */
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@ -289,40 +292,46 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
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*read_val = advk_readl(pcie, PIO_RD_DATA);
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/* No error */
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strcomp_status = NULL;
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ret = 0;
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break;
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case PIO_COMPLETION_STATUS_UR:
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strcomp_status = "UR";
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ret = -EOPNOTSUPP;
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break;
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case PIO_COMPLETION_STATUS_CRS:
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if (allow_crs && read_val) {
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/* For reading, CRS is not an error status. */
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*read_val = CFG_RD_CRS_VAL;
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strcomp_status = NULL;
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ret = 0;
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} else {
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strcomp_status = "CRS";
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ret = -EAGAIN;
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}
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break;
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case PIO_COMPLETION_STATUS_CA:
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strcomp_status = "CA";
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ret = -ECANCELED;
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break;
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default:
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strcomp_status = "Unknown";
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ret = -EINVAL;
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break;
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}
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if (!strcomp_status)
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return 0;
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return ret;
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if (reg & PIO_NON_POSTED_REQ)
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str_posted = "Non-posted";
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else
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str_posted = "Posted";
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dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
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dev_dbg(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
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str_posted, strcomp_status, reg,
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advk_readl(pcie, PIO_ADDR_LS));
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return -EFAULT;
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return ret;
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}
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/**
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@ -345,6 +354,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
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enum pci_size_t size)
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{
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struct pcie_advk *pcie = dev_get_priv(bus);
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int retry_count;
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bool allow_crs;
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uint reg;
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int ret;
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@ -358,7 +368,18 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
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return 0;
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}
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allow_crs = (offset == PCI_VENDOR_ID) && (size == 4);
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/*
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* Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to
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* OS is allowed only for 4-byte PCI_VENDOR_ID config read request and
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* only when CRSSVE bit in Root Port PCIe device is enabled. In all
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* other error PCIe Root Complex must return all-ones.
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* Aardvark HW does not have Root Port PCIe device and U-Boot does not
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* implement emulation of this device.
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* U-Boot currently does not support handling of CRS return value for
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* PCI_VENDOR_ID config read request and also does not set CRSSVE bit.
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* Therefore disable returning CRS response for now.
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*/
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allow_crs = false;
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if (advk_readl(pcie, PIO_START)) {
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dev_err(pcie->dev,
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return 0;
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}
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*valuep = pci_get_ff(size);
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return -EINVAL;
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return -EAGAIN;
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}
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/* Program the control register */
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advk_writel(pcie, reg, PIO_ADDR_LS);
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advk_writel(pcie, 0, PIO_ADDR_MS);
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retry_count = 0;
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retry:
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/* Start the transfer */
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advk_writel(pcie, 1, PIO_ISR);
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advk_writel(pcie, 1, PIO_START);
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if (!pcie_advk_wait_pio(pcie)) {
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ret = pcie_advk_wait_pio(pcie);
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if (ret < 0) {
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if (allow_crs) {
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*valuep = CFG_RD_CRS_VAL;
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return 0;
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}
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*valuep = pci_get_ff(size);
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return -EINVAL;
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return ret;
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}
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retry_count += ret;
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/* Check PIO status and get the read result */
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ret = pcie_advk_check_pio_status(pcie, allow_crs, ®);
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if (ret == -EAGAIN && retry_count < PIO_MAX_RETRIES)
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goto retry;
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if (ret) {
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*valuep = pci_get_ff(size);
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return ret;
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@ -461,7 +490,9 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
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enum pci_size_t size)
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{
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struct pcie_advk *pcie = dev_get_priv(bus);
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int retry_count;
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uint reg;
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int ret;
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dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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@ -476,7 +507,7 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
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if (advk_readl(pcie, PIO_START)) {
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dev_err(pcie->dev,
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"Previous PIO read/write transfer is still running\n");
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return -EINVAL;
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return -EAGAIN;
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}
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/* Program the control register */
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@ -504,16 +535,24 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
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advk_writel(pcie, reg, PIO_WR_DATA_STRB);
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dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
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retry_count = 0;
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retry:
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/* Start the transfer */
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advk_writel(pcie, 1, PIO_ISR);
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advk_writel(pcie, 1, PIO_START);
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if (!pcie_advk_wait_pio(pcie)) {
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return -EINVAL;
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}
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ret = pcie_advk_wait_pio(pcie);
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if (ret < 0)
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return ret;
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retry_count += ret;
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/* Check PIO status */
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return pcie_advk_check_pio_status(pcie, false, NULL);
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ret = pcie_advk_check_pio_status(pcie, false, NULL);
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if (ret == -EAGAIN && retry_count < PIO_MAX_RETRIES)
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goto retry;
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return ret;
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}
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/**
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@ -45,7 +45,7 @@
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230400, 460800, 500000, 576000, \
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921600, 1000000, 1152000, 1500000, \
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2000000, 2500000, 3125000, 4000000, \
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5150000 }
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5200000 }
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#endif
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/* auto boot */
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