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at91: modified NAND flash timing on meesc board

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Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
This commit is contained in:
Daniel Gorsulowski 2012-01-25 03:19:49 +00:00 committed by Albert ARIBAUD
parent 07c80bc232
commit dd80264d07
1 changed files with 4 additions and 4 deletions
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8
board/esd/meesc/meesc.c
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@ -73,20 +73,20 @@ static void meesc_nand_hw_init(void)
writel(csa, &matrix->csa[0]); writel(csa, &matrix->csa[0]);
/* Configure SMC CS3 for NAND/SmartMedia */ /* Configure SMC CS3 for NAND/SmartMedia */
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
&smc->cs[3].setup); &smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
&smc->cs[3].pulse); &smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
&smc->cs[3].cycle); &smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE | AT91_SMC_MODE_EXNW_DISABLE |
AT91_SMC_MODE_DBW_8 | AT91_SMC_MODE_DBW_8 |
AT91_SMC_MODE_TDF_CYCLE(3), AT91_SMC_MODE_TDF_CYCLE(12),
&smc->cs[3].mode); &smc->cs[3].mode);
/* Configure RDY/BSY */ /* Configure RDY/BSY */